CS4215中文资料

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芯海科技 CS1256 芯片使用者手册说明书

芯海科技 CS1256 芯片使用者手册说明书

CS1256芯片用户手册带24bits ADC和BIM的高性能REV 1.2版本历史目录版本历史 (2)目录 (3)图清单 (5)表清单 (6)1简介 (7)主要特性 (7)应用场合 (7)功能说明 (8)极限值 (8)电气特性 (9)可靠性指标 (10)产品型号及引脚 (10)典型应用电路 (11)2功能寄存器说明 (12)功能寄存器列表 (12)功能寄存器说明 (12)2.2.1SYS—系统配置寄存器(地址00H) (12)2.2.2ADC0— ADC配置寄存器(地址01H) (13)2.2.3ADC1— ADC配置寄存器1(地址02H) (13)2.2.4ADC3— ADC配置寄存器3(地址04H) (14)2.2.5ADC4— ADC配置寄存器4(地址05H) (14)2.2.6ADC5— ADC配置寄存器5(地址06H) (15)2.2.7BIM0— BIM配置寄存器0(地址07H) (15)2.2.8BIM1— BIM配置寄存器(地址08H) (16)2.2.9ADO— ADC转换数据寄存器(地址09H) (16)2.2.10ADS— ADC转换数据读取标准寄存器(地址0AH) (16)3功能描述 (17)输入选择 (17)PGA和ADC (17)数字滤波器 (18)3.3.1频率响应 (18)3.3.2建立时间 (18)人体阻抗测量 (19)3.4.1正弦信号发生器 (20)3.4.2激励电极及测量电极 (21)3.4.3整流 (21)3.4.4阻抗校准 (21)参考电压源 (22)内部时钟源 (22)测量模式及其切换 (22)多种工作模式 (22)复位和掉电 (23)4转换有效位 (24)5典型特性 (25)LDO典型特性 (25)内部时钟典型特性 (25)BIM典型特性 (26)6三线串行通讯接口 (28)读时序 (28)写时序 (29)7封装 (31)8包装材料信息 (32)9产品丝印图说明 (33)图清单图 1-1 CS1256原理框图 (8)图 1-2 CS1256引脚图 (10)图 1-3 CS1256典型应用电路 (11)图 3-1模拟输入结构图 (17)图 3-2 PGA和ADC结构图 (17)图 3-3 COMB滤波器的频率响应特性(Fs=331Hz,DR=10Hz,3阶COMB) (18)图 3-4 COMB建立过程 (19)图 3-5 BIM模块结构图 (20)图 3-6 CS1256低功耗工作示意图 (23)图 5-1 LDO全电压全温度范围的典型特性(LDOS[1:0]=00,负载1mA) (25)图 5-2内部时钟全电压全温度范围的典型特性 (25)图 5-3 FWR模式下220欧姆纯电阻网络的测试结果 (26)图 5-4 FWR模式下510欧姆纯电阻网络的测试结果 (26)图 5-5 FWR模式下1958欧姆纯电阻网络的测试结果 (27)图 6-1读操作时序1(读AD值) (29)图 6-2读操作时序2(除AD值之外的寄存器) (29)图 6-3写操作时序 (29)图 7-1 芯片封装尺寸信息 (31)图 8-1 SOP16料管尺寸 (32)图 9-1 产品丝印图 (33)表清单表 1-1 CS1256 极限值 (8)表 1-2 CS1256电气特性 (9)表 1-3 CS1256引脚说明 (11)表 2-1功能寄存器列表 (12)表 2-2 SYS寄存器说明 (12)表 2-3 ADC0寄存器说明 (13)表 2-4 ADC1寄存器说明 (13)表 2-5 ADC3寄存器说明 (14)表 2-6 ADC4寄存器说明 (14)表 2-7 ADC5寄存器说明 (15)表 2-8 BIM0寄存器说明 (15)表 2-9 BIM1寄存器说明 (16)表 2-10 ADO寄存器说明 (16)表 2-11 ADO寄存器说明 (16)表 4-1 ADC信号链不同配置下的有效位(ENOB) (24)表 6-1串口通讯命令列表 (28)表 6-2 三线串行通讯接口时序表 (30)1简介主要特性✧BIM•支持4电极测量•支持5K/10K/25K/50K/100K/250KHz多档频率测量•支持阻抗绝对值和相角测量✧ADC•24-bit分辨率•输出速率10~1280Hz 8档可选✧ADC有效位• 2.35V参考、40Hz速率、128倍增益下19.5bits有效位✧LDO及内部参考电压•自带LDO,输出2.35/2.45/2.8/3.0V可选✧支持高性能、普通、低功耗、休眠模式✧支持电压测量、BIM测量及手动测量模式,可通过单命令切换✧低漂移片上时钟✧三线串行通讯应用场合✧人体阻抗分析✧交流测脂功能说明CS1256原理框图如图1-1所示。

维京科技公司产品数据表 - CS系列电流感应芯片电阻说明书

维京科技公司产品数据表 - CS系列电流感应芯片电阻说明书

VIKING TECH CORPORATION KAOHSIUNG BRANCH VIKING ELECTRONICS (WUXI) CO., LTD.()Current Sensing Chip ResistorFeatures3 Watts power rating in 1 Watt size, 1225 packageLow TCR of ±100 PPM/°CResistance values from 1m to 1 ohmHigh purity alumina substrate for high power dissipationLong side terminations with higher power ratingRoHS ComplianceConstruction ApplicationsPower Management ApplicationsSwitching Power SupplyOver Current Protection in Audio ApplicationsVoltage Regulation Module (VRM)DC-DC Converter, Battery Pack, Charger, AdaptorDisk DriverDimensionsPart NumberingPart Number CS06FTFR100Part NumberCS06FTETR200N ( CS06 1W No Marking )Recommend Land PatternPad Layout ( For CS12: Ultra High Power RatingPad Layout (Except For CS12:Ultra High Power Rating Series)Soldering Condition (IPC/JEDEC J-STD-020) Standard Electrical SpecificationsHigh Power & Ultra High Power Rating Electrical SpecificationsCS06 1W: double side printed resistor element without marking.Low TCR Electrical SpecificationsOperating Current=√(P/R)Viking is capable of manufacturing the optional spec based o n customer’s requirement.RCWV(Rated Continuous Working Voltage)=√(P*R) or Max. Operating Voltage whichever is lower.■Storage Temperature: 15~28°C; Humidity < 80%RHPackagingPackaging Quantity & Reel Specifications Paper Tape SpecificationsTop Tape Bottom TapeEmboss Plastic Tape SpecificationsMarkingNo Marking for 0201/0402/1206(1W).1%, 5% for 0805/1206/1210/2010/2512/1225/3720/7520/0612 : 4 digits markingExample:5% for 0603: 3 digits marking in E241% for 0603: 3 digits marking with under-line in E96 (non-including E24 series)3 digits marking for E24 or R value suffix is zero in E96: R10=100mΩ; R28=280mΩ3 digits marking for E96: 243=243mΩ; 511=511mΩTop Tape11.4Min.R10243REVISION HISTORYREVISION DATE CHANGE NOTIFICATION DESCRIPTIONVersion D1Jun 03, 2014 --Electrical Specifications updated-CS25 Pad Layout updated-Environmental Characteristics updated Version D2Apr 30, 2015 - -Increase Product Size 0612Version D3Jul 15, 2016 --Remove Material Description-Modify Storage Temperature-CS12 Pad Layout updated-CS62 Resistance Range updated Version D4Jan 12, 2018 --Modify 1225 Dimension L, WVersion D5Jul 27, 2018 -- Increase 1206 1W Ultra High PowerElectrical SpecificationsVersion D6May 20, 2019 - - Modify TCR Test description- Electrical Specifications updatedVersion D7Mar 23, 2020 - - Environmental Characteristics : Added testvoltage for Voltage ProofVersion D8Mar 10, 2021 -- Modify Bending Test description-Modify 2010 Embossed Plastic Tape BSpecification-Modify Soldering Condition (IPC/JEDECJ-STD-020)。

NS4215用户手册V0.9

NS4215用户手册V0.9

N S4215用户手册V0.9深圳市纳芯威科技有限公司2013年03月修改历史日期版本作者修改说明目录1功能说明 (5)2主要特性 (5)3应用领域 (5)4典型应用电路 (5)5极限参数 (6)6电气特性 (7)7芯片管脚描述 (8)7.1 NS4215封装管脚分配图 (8)7.2 NS4215引脚功能描述 (8)8NS4215典型参考特性 (9)9NS4215应用说明 (11)9.1 芯片基本结构描述 (11)9.2 低功耗关断控制端/SD (11)9.3 防失真(NCN)功能 (11)9.4 超低EMI控制端/LEMI (12)9.5 并联BTL输出设置端PBTL (12)9.6 NS4215应用图示 (13)9.6.1 差分输入BTL输出立体声模式 (13)9.6.2 单端输入BTL输出立体声模式 (13)9.6.3 差分输入PBTL输出单声道模式 (14)9.6.4 单端输入PBTL输出单声道模式 (14)9.7 EMI增强技术 (15)9.8 NS4215应用参数设置 (15)9.8.1 放大器增益设置 (15)9.8.2 输入电容Ci的选取 (15)9.8.3 电源去耦电容 (16)9.9 输出滤波器 (16)9.10 layout建议 (17)9.11 测试电路 (17)10芯片的封装 (18)图目录图1 NS4215典型应用电路 (6)图2 NS4215封装管脚分配图(top view) (8)图3 NS4215原理框图 (11)图4 假设不受电源电压限制时的音频输出信号 (12)图5 普通工作模式下的音频输出信号 (12)图6 防失真工作模式下的音频输出信号 (12)图7 差分输入BTL输出立体声模式 (13)图8 单端输入BTL输出立体声模式 (13)图9 差分输入PBTL输出单声道模式 (14)图10 单端输入PBTL输出单声道模式 (14)图11 EMI测试频谱图 (15)图12 输入高通网络 (15)图13 输入高通滤波器曲线 (16)图14 输出端加磁珠应用图 (16)图15 负载为8Ω,转折频率为27kHz的LC输出滤波器 (17)图16 负载为4Ω,转折频率为27kHz的LC输出滤波器 (17)图17 NS4215测试电路 (17)图18 TSSOP-24封装尺寸图 (18)表目录表1 芯片最大物理极限值 (6)表2 NS4215电气特性 (7)表3 (8)NS4215管脚描述1功能说明NS4215是一款超低EMI,无需滤波器,每声道可输出10W的D类立体声音频功率放大器。

42105中文操作手册透气性

42105中文操作手册透气性

操作手册数显透气性仪编号. 42105-M-ASM/ 42105-ASM附件: 编号:壳型透气性附件 42105A-M / 42105A铸型透气性附件 42105B基本透气性附件 42105C-M / 42105C附加透气性附件 42105D-M / 42105D仪器相关信息标明如下:序列号或类型:备件号CE 认证:序列号:制造年份: 制造商的名称和地址:Simpson Technologies Corporation751 Shoreline DriveAurora, IL 60504USA电话: +1 (630) 978-0044传真: +1 (630) 978-0068邮箱: sales@© 2009 辛普森技术公司Aurora, IL 60504 USA版权所有.目录1 安全 (1)1.1 操作手册说明 (1)1.2 原理 (2)1.3 依据使用目的 (2)1.4 组织测量 (2)1.5 人员资格 (3)2 简要说明和规格 (4)2.1 数显透气性仪的使用 (4)2.2 介绍 (4)2.3 尺寸和重量 (6)2.4 附件 (7)2.4.1 壳型透气性附件(42105A) (7)2.4.2 铸型透气性附件(42105B) (7)2.4.3 基本透气性附件(42105C/42105C-M) (8)2.4.4 附件透气性附件(42105D/42105D-M) (8)3 运输 (9)4 位置和布置 (10)4.1 操作者使用的工作台 (10)4.2 安装地点 (10)4.3 地基 (10)5 安全操作指导 (11)5.1 数显透气性仪 (11)5.1.1 取出仪器和部件清单 (11)5.1.2 电气连接 (11)5.1.3 数显透气性仪注入混合液 (13)5.1.4 更改数显透气性仪内部时间 (13)5.2 仪器使用/操作 (15)5.2.1 多种操作模式介绍 (15)5.2.2 更改试样信息 (16)5.3 透气性仪直接测量(常规模式) (17)5.4 壳型透气性附件 (19)5.4.1 描述 (19)5.4.2 操作 (20)5.5 铸型透气性附件 (23)5.5.1 描述 (23)5.5.2 操作 (24)5.6 基本透气性附件 (28)5.6.1 描述 (28)5.6.2 操作 (29)5.7 附加透气性附件 (33)5.7.1 描述 (33)5.7.2 操作 (33)6 装配,停止使用,搬运,废料处理 (36)6.1 装配,拆卸,停止使用 (36)6.2 搬运,机械量 (36)6.3 废料处理 (36)7 维护和校准 (37)7.1 每周维护 (37)7.2 季度性维护 (37)7.3 校准 (38)7.3.1 校准附件 (38)7.3.2 调平 (38)7.3.3 水位 (38)7.3.4 密封性 (39)7.3.5 渗透压力控制 (39)7.3.6 透气性标准量具 (41)8 机载噪音排放 (42)9 仪器配置&备件清单 (43)9.1 仪器配置 (43)图1:透气性仪后视图 (43)图2:透气性仪正面图 (44)图3:定量贮气筒 (45)图4:无定量贮气筒的透气性顶部 (46)图5:控制面板 (47)图6:数显 (47)图7:压力计组件 (48)图8:”U”形管压力计 (49)图9:压力计的闭塞阀 (50)图10:定量贮气筒的顶部 (50)图11:装配好的调压器/过滤器 (51)9.2 备件清单 (52)1. 安全1.1操作手册说明此手册不包括任何担保,仅作为提供技术资料的目的。

CSC4115中文资料

CSC4115中文资料

Continental Device India LimitedAn IS/ISO 9002 and IECQ Certified ManufacturerNPN EPITAXIAL PLANAR SILICON TRANSISTORCSC4115 (9AW) TO-92 BCEMARKING : CSC4115 BCABSOLUTE MAXIMUM RATINGS(Ta=25deg C unless otherwise specified)DESCRIPTION SYMBOL VALUEUNITCollector -Base VoltageBVCBO 40V Collector Emitter VoltageBVCEO 20V Emitter Base VoltageBVEBO 6.0V Collector CurrentIC 2.0A Collector Current PeakICP* 5.0A Collector Power DissipationPC 0.4W Operating And Storage JunctionTj, Tstg -55 to +150deg CTemperature Range *Single Pulse Pw=10msELECTRICAL CHARACTERISTICS (Ta=25 deg C Unless Otherwise Specified)DESCRIPTION SYMBOL TEST CONDITION MINTYP MAX UNIT Collector -Base VoltageBVCBO IC=50uA, IE=040--V Collector Emitter VoltageBVCEO IC=1mA, IB=020--V Emitter Base VoltageBVEBO IE=50uA, IC=0 6.0--V Collector Cut off CurrentICBO VCB=30V, IE=0--0.1uA ICEO VCE=20V, IB=0-- 1.0uA Emitter Cut off CurrentIEBO VEB=5V, IC=0--0.1uA DC Current GainhFE VCE=2V, IC=0.1A 120-560Collector Emitter Saturation VoltageVCE(Sat) IC=2A, IB=0.1A -- 1.0V Dynamic CharacteristicsTransition Frequencyft VCE=2V, IC=0.5A,-150-MHz f=100MHzCollector Output CapacitanceCob VCB=10V, IE=0-25-pFf=1MHzHfe Classifications A 120-270; B 180-390; C 270-560;"For BC" 180- 560IS/ISO 9002Lic# QSC/L- 000019.2IS / IECQC 700000IS / IECQC 750100TO-92 Transistors on Tape and Ammo PackTO-92 Plastic PackageTO-92 Bulk TO-92 T&A1K/polybag 2K/ammo box200 gm/1K pcs 645 gm/2K pcs3" x 7.5" x 7.5"12.5" x 8" x 1.8"5.0K 2.0K17" x 15" x 13.5"17" x 15" x 13.5"80.0K 32.0K23 kgs 12.5 kgsPACKAGENet Weight/Qty DetailsSTANDARD PACKINNER CARTON BOXQty OUTER CARTON BOXQty Gr Wt SizeSizePacking Detail1. M AX IM UM A LIG NM E NT D EV IATIO N B ETW EEN LE ADS NOT TO B E G RE ATER TH AN 0.2 m m.2. M AX IM UM NO N-CU M ULATIV E VAR IATIO N BETW EE N TAP E FE ED HO LE S SH ALL NO T EX CE ED 1 m m IN 20 PIT CH ES.3. H OLD D OW N TAP E NO T TO E XC EE D B EY OND T HE ED G E(S) O F CA RR IER TA PE AND T HE RE S H ALL BE NO EX PO SU R E O F AD H ESIV E.4. NO M O R E TH AN 3 C ONSE CU TIV E M ISS ING C O M PO NE NT S AR E PER M ITTE D.5. A TA PE TR A ILE R, H AVING AT LEA ST TH R EE F EED H OLE S A RE RE QU IR ED AFTE R T HE LAST CO M PO NENT.6. SP LICE S S HA LL NO T INTE RFE RE W ITH TH E SP R OC KE T FEE D H OLE S.A l l d i m i n s i o n s i n m m .DIM MIN.MAX.A 4.32 5.33B 4.45 5.20C 3.18 4.19D 0.410.55E 0.350.50F 5 DEG G 1.14 1.40H 1.14 1.53K12.70—PIN CONFIGURATION 1. BASE2. COLLECTOR3. EMITTERNotesDisclaimerThe product information and the selection guides facilitate selection of the CDIL's Discrete Semiconductor Device(s)best suited for application in your product(s)as per your requirement.It is recommended that you completely review our Data Sheet(s)so as to confirm that the Device(s)meet functionality parameters for your application.The information furnished on the CDIL Web Site/CD is believed to be accurate and reliable.CDIL however,does not assume responsibility for inaccuracies or incomplete information.Furthermore,CDIL does not assume liability whatsoever,arising out of the application or use of any CDIL product; neither does it convey any license under its patent rights nor rights of others.These products are not designed for use in life saving/support appliances or systems.CDIL customers selling these products(either as individual Discrete Semiconductor Devices or incorporated in their end products),in any life saving/support appliances or systems or applications do so at their own risk and CDIL will not be responsible for any damages resulting from such sale(s).CDIL strives for continuous improvement and reserves the right to change the specifications of its products without prior notice.CDIL is a registered Trademark ofContinental Device India LimitedC-120 Naraina Industrial Area, New Delhi 110 028, India.Telephone + 91-11-579 6150 Fax + 91-11-579 9569, 579 5290e-mail sales@ 。

ec4215磁芯参数

ec4215磁芯参数

ec4215磁芯参数1.引言1.1 概述磁芯是一种常见的电子元件,广泛应用于各种电气设备中。

磁芯的参数是指其物理性质和特性,对于磁芯的使用和性能具有重要的影响。

本文将对磁芯参数进行详细介绍和分析。

首先,磁芯的参数可以分为几个方面。

一是磁导率,磁导率是衡量材料导磁性能的重要参数,可以反映磁芯对磁场的响应能力。

它的大小决定了磁芯在电磁场中的感应电流和电磁能量的转换效果,因此磁导率的选择和优化对于提高磁芯的性能至关重要。

第二,磁芯的磁阻也是一项重要参数。

磁阻是磁通通过磁芯时所遇到的阻力,对于磁芯的导磁能力和传导磁场的效果有着直接的影响。

通过合理地选择磁芯的材料和尺寸,并控制磁芯的磁阻,可以提高磁芯的磁场传输效率,从而提高电气设备的性能。

此外,磁芯的磁化特性也是需要关注的参数之一。

磁化特性涵盖了磁芯的磁感应强度、矫顽力和剩磁等方面。

这些参数直接关系到磁芯在正常工作状态下的磁化效果和稳定性。

通过调整磁芯的磁化特性,可以满足不同电磁场条件下的工作要求,提高磁芯的适应性和可靠性。

综上所述,磁芯的参数是衡量磁芯性能和应用效果的重要指标。

磁导率、磁阻和磁化特性等参数相互影响,需要综合考虑和优化才能达到更好的性能。

在后续的文章中,我们将对磁芯参数进行进一步的详细介绍和分析,以便读者更好地理解和应用磁芯技术。

文章结构:本文主要介绍了ec4215磁芯的参数。

文章分为引言、正文和结论三个部分。

引言部分包括以下内容:1.1 概述:介绍磁芯在电子设备中的重要性和应用领域。

同时指出ec4215磁芯的特点和优势。

1.2 文章结构:说明文章的整体结构和各个部分的内容安排。

1.3 目的:阐明本文的写作目的,即介绍ec4215磁芯的参数并对其进行分析和总结。

正文部分分为2.1和2.2两个子节,分别介绍了磁芯参数1和磁芯参数2的内容。

2.1 磁芯参数1:详细介绍ec4215磁芯的某个重要参数,例如磁感应强度、矫顽力、饱和磁感应强度等。

阐述这些参数的意义和影响因素,并给出具体数值和对应的实验结果或理论推导。

CS42438_07中文资料

CS42438_07中文资料

FEATURESSix 24-bit A/D, Eight 24-bit D/A Converters ADC Dynamic Range–105 dB Differential –102 dB Single-Ended DAC Dynamic Range–108 dB Differential –105 dB Single-Ended ADC/DAC THD+N–-98 dB Differential –-95 dB Single-EndedCompatible with Industry-Standard TimeDivision Multiplexed (TDM) Serial InterfaceDAC Sampling Rates up to 192 kHz ADC Sampling Rates up to 96 kHzProgrammable ADC High-Pass Filter for DCOffset CalibrationLogarithmic Digital Volume Control Hardware Mode or Software I²C ® & SPI ™ Supports Logic Levels Between 5V and 1.8VGENERAL DESCRIPTIONThe CS42438 CODEC provides six multi-bit analog-to-digital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with ei-ther differential or single-ended inputs and outputs, in a 52-pin MQFP package.Six fully differential, or single-ended, inputs are avail-able on stereo ADC1, ADC2, and ADC3. When operating in Single-Ended Mode, an internal MUX be-fore ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection.All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs.An auxiliary serial input is available for an additional two channels of PCM data.The CS42438 is available in a 52-pin MQFP package in Commercial (-10°C to +70°C) and Automotive (-40°C to +105°C) grades. The CDB42438 Customer Demonstra-tion board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 61 for complete ordering information.The CS42438 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems.CS42438TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE MODE (6)1.1 Digital I/O Pin Characteristics (8)2. PIN DESCRIPTIONS - HARDWARE MODE (9)3. TYPICAL CONNECTION DIAGRAMS (11)4. CHARACTERISTICS AND SPECIFICATIONS (13)RECOMMENDED OPERATING CONDITIONS (13)ABSOLUTE MAXIMUM RATINGS (13)ANALOG INPUT CHARACTERISTICS (COMMERCIAL) (14)ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) (15)ADC DIGITAL FILTER CHARACTERISTICS (16)ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) (17)ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) (18)COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (20)SWITCHING SPECIFICATIONS - ADC/DAC PORT (21)SWITCHING CHARACTERISTICS - AUX PORT (22)SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (23)SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (24)DC ELECTRICAL CHARACTERISTICS (25)DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS (25)5. APPLICATIONS (26)5.1 Overview (26)5.2 Analog Inputs (27)5.2.1 Line-Level Inputs (27)5.2.1.1 Hardware Mode (27)5.2.1.2 Software Mode (27)5.2.2 ADC3 Analog Input (28)5.2.3 Hardware Mode (29)5.2.4 Software Mode (29)5.2.5 High-Pass Filter and DC Offset Calibration (29)5.2.5.1 Hardware Mode (29)5.2.5.2 Software Mode (29)5.3 Analog Outputs (30)5.3.1 Initialization (30)5.3.2 Line-Level Outputs and Filtering (30)5.3.3 Digital Volume Control (32)5.3.3.1 Hardware Mode (32)5.3.3.2 Software Mode (32)5.3.4 De-Emphasis Filter (32)5.4 System Clocking (33)5.4.1 Hardware Mode (33)5.4.2 Software Mode (33)5.5 CODEC Digital Interface (33)5.5.1 TDM (33)5.5.2 I/O Channel Allocation (34)5.6 AUX Port Digital Interface Formats (34)5.6.1 Hardware Mode (34)5.6.2 Software Mode (34)5.6.3 I²S (34)5.6.4 Left-Justified (35)5.7 Control Port Description and Timing (35)5.7.1 SPI Mode (35)5.7.2 I²C Mode (36)5.8 Recommended Power-Up Sequence (37)5.8.1 Hardware Mode (37)5.8.2 Software Mode (38)5.9 Reset and Power-Up (38)5.10 Power Supply, Grounding, and PCB Layout (38)6. REGISTER QUICK REFERENCE (39)7. REGISTER DESCRIPTION (41)7.1 Memory Address Pointer (MAP) (41)7.1.1 Increment (INCR) (41)7.1.2 Memory Address Pointer (MAP[6:0]) (41)7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) (41)7.2.1 Chip I.D. (CHIP_ID[3:0]) (41)7.2.2 Chip Revision (REV_ID[3:0]) (41)7.3 Power Control (Address 02h) (42)7.3.1 Power Down ADC Pairs (PDN_ADCX) (42)7.3.2 Power Down DAC Pairs (PDN_DACX) (42)7.3.3 Power Down (PDN) (42)7.4 Functional Mode (Address 03h) (43)7.4.1 MCLK Frequency (MFREQ[2:0]) (43)7.5 Miscellaneous Control (Address 04h) (43)7.5.1 Freeze Controls (FREEZE) (43)7.5.2 Auxiliary Digital Interface Format (AUX_DIF) (43)7.6 ADC Control & DAC De-Emphasis (Address 05h) (44)7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) (44)7.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) (44)7.6.3 DAC De-Emphasis Control (DAC_DEM) (44)7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) (44)7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) (44)7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) (45)7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) (45)7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) (45)7.7 Transition Control (Address 06h) (45)7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) (45)7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) (46)7.7.3 Auto-Mute (AMUTE) (46)7.7.4 Mute ADC Serial Port (MUTE ADC_SP) (47)7.8 DAC Channel Mute (Address 07h) (47)7.8.1 Independent Channel Mute (AOUTX_MUTE) (47)7.9 AOUTX Volume Control (Addresses 08h- 0Fh) (47)7.9.1 Volume Control (AOUTX_VOL[7:0]) (47)7.10 DAC Channel Invert (Address 10h) (48)7.10.1 Invert Signal Polarity (INV_AOUTX) (48)7.11 AINX Volume Control (Address 11h-16h) (48)7.11.1 AINX Volume Control (AINX_VOL[7:0]) (48)7.12 ADC Channel Invert (Address 17h) (49)7.12.1 Invert Signal Polarity (INV_AINX) (49)7.13 Status (Address 19h) (Read Only) (49)7.13.1 CLOCK ERROR (CLK ERROR) (49)7.13.2 ADC Overflow (ADCX_OVFL) (49)7.14 Status Mask (Address 1Ah) (49)8. EXTERNAL FILTERS (50)8.1 ADC Input Filter (50)8.1.1 Passive Input Filter (51)8.1.2 Passive Input Filter w/Attenuation (52)9. ADC FILTER PLOTS (54)10. DAC FILTER PLOTS (56)11. PARAMETER DEFINITIONS (58)12. REFERENCES (59)13. PACKAGE INFORMATION (60)13.1 Thermal Characteristics (60)14. ORDERING INFORMATION (61)15. REVISION HISTORY (61)LIST OF FIGURESFigure 1.Typical Connection Diagram (Software Mode) (11)Figure 2.Typical Connection Diagram (Hardware Mode) (12)Figure 3.Output Test Circuit for Maximum Load (19)Figure 4.Maximum Loading (19)Figure 5.TDM Serial Audio Interface Timing (21)Figure 6.Serial Audio Interface Slave Mode Timing (22)Figure 7.Control Port Timing - I²C Format (23)Figure 8.Control Port Timing - SPI Format (24)Figure 9.Full-Scale Input (28)Figure 10.ADC3 Input Topology (28)Figure 11.Audio Output Initialization Flow Chart (31)Figure 12.Full-Scale Output (32)Figure 13.De-Emphasis Curve (33)Figure 14.TDM Serial Audio Format (34)Figure 15.AUX I²S Format (34)Figure 16.AUX Left-Justified Format (35)Figure 17.Control Port Timing in SPI Mode (36)Figure 18.Control Port Timing, I²C Write (36)Figure 19.Control Port Timing, I²C Read (37)Figure 20.Single to Differential Active Input Filter (50)Figure 21.Single-Ended Active Input Filter (50)Figure 22.Passive Input Filter (51)Figure 23.Passive Input Filter w/Attenuation (52)Figure 24.Active Analog Output Filter (53)Figure 25.Passive Analog Output Filter (53)Figure 26.SSM Stopband Rejection (54)Figure 27.SSM Transition Band (54)Figure 28.SSM Transition Band (Detail) (54)Figure 29.SSM Passband Ripple (54)Figure 30.DSM Stopband Rejection (54)Figure 31.DSM Transition Band (54)Figure 32.DSM Transition Band (Detail) (55)Figure 33.DSM Passband Ripple (55)Figure 34.SSM Stopband Rejection (56)Figure 35.SSM Transition Band (56)Figure 36.SSM Transition Band (detail) (56)Figure 37.SSM Passband Ripple (56)Figure 38.DSM Stopband Rejection (56)Figure 39.DSM Transition Band (56)Figure 40.DSM Transition Band (detail) (57)Figure 41.DSM Passband Ripple (57)Figure 42.QSM Stopband Rejection (57)Figure 44.QSM Transition Band (detail) (57)Figure 45.QSM Passband Ripple (57)LIST OF TABLESTable 1. I/O Power Rails (8)Table 2. Hardware Configurable Settings (26)Table 3. AIN5 Analog Input Selection (29)Table 4. AIN6 Analog Input Selection (29)Table 5. MCLK Frequency Settings (33)Table 6. Serial Audio Interface Channel Allocations (34)Table 7. MCLK Frequency Settings (43)Table 8. Example AOUT Volume Settings (47)Table 9. Example AIN Volume Settings (48)1.PIN DESCRIPTIONS - SOFTWARE MODEPin Name#Pin DescriptionSCL/CCLK1Serial Control Port Clock (Input) - Serial clock for the control port interface.SDA/CDOUT2Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data.AD0/CS3Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI Mode.AD1/CDIN4Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data.RST5Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low.VLC6Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page8.FS7Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD8Digital Power (Input) - Positive power supply for the digital section.DGND9,18Digital Ground (Input) -VLS10Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-faces. See “Digital I/O Pin Characteristics” on page8.SCLK11Serial Clock(Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. MCLK12Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.ADC_SDOUT13Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.DAC_SDIN14DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.AUX_LRCK15Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line.AUX_SCLK16Auxiliary Serial Clock(Output) - Serial clock for the Auxiliary serial audio interface.AUX_SDIN17Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple-ment serial audio data.AOUT1 +,-AOUT2 +,-AOUT3 +,-AOUT4 +,-AOUT5 +,-AOUT6 +,-AOUT7 +,-AOUT8 +,-20,1921,2224,2325,2628,2729,3031,3233,34Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs may also be used single-ended.AGND35,48Analog Ground (Input) - Ground reference for the analog section.VQ36Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA37,46Analog Power (Input) - Positive power supply for the analog section.AIN1 +,-AIN2 +,-AIN3 +,-AIN4 +,-AIN5 +,-AIN6 +,-39,3841,4043,4245,4450,4952,51Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven tocommon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.AIN5 A,B AIN6 A,B 50,4952,51Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allowsselection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table.FILT+47Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-cuits.1.1Digital I/O Pin CharacteristicsVarious pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.Power Rail Pin NameSW/(HW)I/O Driver ReceiverVLC RST Input- 1.8 V - 5.0 V, CMOS SCL/CCLK(AIN5_MUX)Input- 1.8 V - 5.0 V, CMOS, with HysteresisSDA/CDOUT (AIN6_MUX)Input/Output1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS, with HysteresisAD0/CS(MFREQ)Input- 1.8 V - 5.0 V, CMOS AD1/CDIN(ADC3_HPF)Input- 1.8 V - 5.0 V, CMOS VLS MCLK Input- 1.8 V - 5.0 V, CMOS LRCK Input- 1.8 V - 5.0 V, CMOSSCLK Input- 1.8 V - 5.0 V, CMOSADC_SDOUT3 (ADC3_SINGLE)Input/Output1.8 V - 5.0 V, CMOS-DAC_SDIN Input- 1.8 V - 5.0 V, CMOS AUX_LRCK Output 1.8 V - 5.0 V, CMOS-AUX_SCLK Output 1.8 V - 5.0 V, CMOS-AUX_SDIN Input- 1.8 V - 5.0 V, CMOSTable 1. I/O Power Rails2.Pin Name#Pin DescriptionAIN5_MUX AIN6_MUX 12Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of ADC3.MFREQ3MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock.ADC3_HPF4ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtractedfrom the conversion result.RST5Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low.VLC6Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page8.FS7Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD8Digital Power (Input) - Positive power supply for the digital section.DGND9,18Digital Ground (Input) - Ground reference for the digital section.VLS10Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-faces. See “Digital I/O Pin Characteristics” on page8.SCLK11Serial Clock(Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. MCLK12Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.ADC_SDOUT13Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.DAC_SDIN14DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.AUX_LRCK15Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line.AUX_SCLK16Auxiliary Serial Clock(Output) - Serial clock for the Auxiliary serial audio interface.AUX_SDIN17Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple-ment serial audio data.AOUT1 +,-AOUT2 +,-AOUT3 +,-AOUT4 +,-AOUT5 +,-AOUT6 +,-AOUT7 +,-AOUT8 +,-20,1921,2224,2325,2628,2729,3032,31,33,34Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs mayalso be used single-ended.AGND35,48Analog Ground (Input) - Ground reference for the analog section.VQ36Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA37,46Analog Power (Input) - Positive power supply for the analog section.AIN1 +,-AIN2 +,-AIN3 +,-AIN4 +,-AIN5 +,-AIN6 +,-39,3841,4043,4245,4450,4952,51Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven tocommon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.AIN5 A,B AIN6 A,B 50,4952,51Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allowsselection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table.FILT+47Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-cuits.3.TYPICAL CONNECTION DIAGRAMSFigure 1. Typical Connection Diagram (Software Mode)Figure 2. Typical Connection Diagram (Hardware Mode)4.CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS(AGND=DGND=0 V, all voltages with respect to ground.)ABSOLUTE MAXIMUM RATINGS(AGND = DGND = 0 V; all voltages with respect to ground.)WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operationis not guaranteed at these extremes.Notes:1.Typical Analog input/output performance will slightly degrade at VA = 3.3 V.2.The ADC_SDOUT may not meet timing requirements in Double-Speed Mode.3.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not causeSCR latch-up.4.The maximum over/under voltage is limited by the input current.ParametersSymbol MinMax Units DC Power Supply Analog (Note 1)VA 3.14 5.25V Digital VD 3.14 3.47V Serial Audio Interface (Note 2)VLS 1.71 5.25V Control Port Interface VLC 1.71 5.25V Ambient TemperatureCommercial -CMZAutomotive -DMZT A-10-40+70+105°C °CParametersSymbol Min Max Units DC Power SupplyAnalogDigitalSerial Port Interface Control Port InterfaceVA VD VLS VLC -0.3-0.3-0.3-0.3 6.06.06.06.0V V V V Input Current(Note 3)I in -±10mA Analog Input Voltage (Note 4)V IN AGND-0.7VA+0.7V Digital Input Voltage Serial Port Interface (Note 4)Control Port InterfaceV IND-S V IND-C -0.3-0.3VLS+ 0.4VLC+ 0.4V V Ambient Operating Temperature (power applied)T A -50+125°C Storage TemperatureT stg-65+150°C(Test Conditions (unless otherwise specified): T A=-10to+70°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10Hz to 20kHz.)Differential Single-EndedParameter Min Typ Max Min Typ Max Unit Fs=48 kHz, 96 kHzDynamic Range A-weightedunweighted40 kHz bandwidth unweighted 9996-10510299---96931029996---dBdBdBTotal Harmonic Distortion + Noise -1dB (Note 5) -20dB-60dB40 kHz bandwidth -1 dB -----98-82-42-90-92--------95-79-39-90-89---dBdBdBdBADC1-3 Interchannel Isolation-90--90-dB ADC3 MUX Interchannel Isolation-90--90-dB DC AccuracyInterchannel Gain Mismatch-0.1--0.1-dB Gain Drift-±100--±100-ppm/°C Analog InputFull-Scale Input Voltage 1.06*VA 1.12*VA 1.18*VA0.53*VA0.56*VA0.59*VA Vpp Differential Input Impedance (Notes 6 & 8)232932kΩSingle-Ended Input Impedance(Notes 7 & 8)---232932kΩCommon Mode Rejection Ratio (CMRR)-82----dB(Test Conditions (unless otherwise specified): T A =-40 to +85°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10Hz to 20kHz.)Notes:5.Referred to the typical full-scale voltage.6.Measured between AINx+ and AINx-.7.Measured between AINxx and AGND.8.The input impedance scales inversely proportionate to the sample rate of the ADC modulatorDifferentialSingle-Ended ParameterMin Typ MaxMin Typ MaxUnitFs=48 kHz, 96 kHz Dynamic RangeA-weighted unweighted 40 kHz bandwidth unweighted 9794-10510299---9491-1029996---dB dBdBTotal Harmonic Distortion + Noise -1dB(Note 5) -20dB-60dB40 kHz bandwidth -1 dB-----98-82-42-87-90--------95-79-39-87-87---dB dB dB dB ADC1-3 Interchannel Isolation -90--90-dB ADC3 MUX Interchannel Isolation -85--85-dB DC AccuracyInterchannel Gain Mismatch -0.1--0.1-dB Gain Drift -±100--±100-ppm/°C Analog InputFull-Scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp Differential Input Impedance (Notes 6 & 8)232932k ΩSingle-Ended Input Impedance(Notes 7 & 8)---232932k ΩCommon Mode Rejection Ratio (CMRR)-82----dBADC DIGITAL FILTER CHARACTERISTICSNotes:9.Filter response is guaranteed by design.10.Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26to 33) havebeen normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.Parameter (Notes 9, 10)MinTypMaxUnitSingle-Speed Mode (Note 10)Passband (Frequency Response) to -0.1 dB corner0-0.4896Fs Passband Ripple --0.08dB Stopband0.5688--Fs Stopband Attenuation 70--dB Total Group Delay-12/Fs-sDouble-Speed Mode (Note 10)Passband (Frequency Response) to -0.1 dB corner0-0.4896Fs Passband Ripple --0.16dB Stopband0.5604--Fs Stopband Attenuation 69--dB Total Group Delay-9/Fs-sHigh-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB -120--Hz Hz Phase Deviation @ 20Hz-10-Deg Passband Ripple --0dB Filter Settling Time -105/Fss(Test Conditions (unless otherwise specified): T A=-10 to +70°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale 997 Hz output sine wave (see Note 12) into passive filter in Figure 26 on page 54 and active filter in Fig-ure 26 on page 54; Measurement Bandwidth is 10Hz to 20kHz.)ParameterDifferentialMin Typ MaxSingle-EndedMin Typ Max UnitFs = 48 kHz, 96 kHz, 192 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10299--1081059996----9996--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-92-----------95-82-42-90-73-33-89-----dBdBdBdBdBdBInterchannel Isolation (1 kHz)-100--100-dB Analog OutputFull-Scale Output 1.235•VA 1.300•VA 1.365•VA0.618•VA0.650•VA0.683•VA Vpp Interchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C Output Impedance-100--100-ΩDC Current draw from an AOUT pin(Note 11)--10--10μA AC-Load Resistance (R L)(Note 13)3--3--kΩLoad Capacitance (C L)(Note 13)--100--100pF(Test Conditions (unless otherwise specified): T A =-40to +85°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale 997 Hz output sine wave (see Note 12) in Figure 26 on page 54 and Figure 26 on page 54; Measure-ment Bandwidth is 10Hz to 20kHz.)Notes:11.Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pindue to typical leakage through the electrolytic DC-blocking capacitors.12.One-half LSB of triangular PDF dither is added to data.13.Guaranteed by design. See Figure 3. R L and C L reflect the recommended minimum resistance andmaximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit to-pology, C L will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See “External Filters” on page 50 for a recommended output filter.ParameterDifferentialMin Typ MaxSingle-EndedMin Typ MaxUnitFs = 48 kHz, 96 kHz, 192 kHz Dynamic Range18 to 24-Bit A-weightedunweighted16-Bit A-weightedunweighted10097--1081059996----9794--1051029693----dB dB dB dB Total Harmonic Distortion + Noise18 to 24-Bit 0 dB-20 dB-60 dB16-Bit 0 dB-20 dB-60 dB-------98-85-45-93-76-36-90------------95-82-42-90-73-33-87-----dB dB dB dB dB dB Interchannel Isolation (1 kHz)-100--100-dBAnalog Output Full-Scale Output 1.210•VA 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA Vpp Interchannel Gain Mismatch -0.10.25-0.10.25dB Gain Drift -±100--±100-ppm/°C Output Impedance -100--100-ΩDC Current draw from an AOUT pin (Note 11)--10--10μAAC-Load Resistance (R L ) (Note 13)3--3--k ΩLoad Capacitance (C L )(Note 13)--100--100pFFigure 3. Output Test Circuit for Maximum Load Figure 4. Maximum LoadingCOMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSENotes:14.Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 34to 45) havebeen normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.15.Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs.Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs.16.De-emphasis is only available in Single-Speed Mode.Parameter (Notes 9, 14)MinTypMaxUnitSingle-Speed ModePassband (Frequency Response)to -0.05dB corner to -3dB corner00--0.47800.4996Fs Fs Frequency Response 10Hz to 20kHz -0.2-+0.08dB StopBand0.5465--Fs StopBand Attenuation (Note 15)50--dB Group Delay-10/Fs -sDe-emphasis Error (Note 16)Fs = 32kHz Fs = 44.1 kHz Fs = 48 kHz------+1.5/+0+0.05/-0.25-0.2/-0.4dB dB dBDouble-Speed ModePassband (Frequency Response)to -0.1dB corner to -3dB corner00--0.46500.4982Fs Fs Frequency Response 10Hz to 20kHz -0.2-+0.7dB StopBand0.5770--Fs StopBand Attenuation (Note 15)55--dB Group Delay -5/Fs-sQuad-Speed ModePassband (Frequency Response)to -0.1dB corner to -3dB corner00--0.3970.476Fs Fs Frequency Response 10Hz to 20kHz -0.2-+0.05dB StopBand0.7--Fs StopBand Attenuation (Note 15)51--dB Group Delay - 2.5/Fs-sSWITCHING SPECIFICATIONS - ADC/DAC PORT(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C LOAD = 15 pF.)Notes:17.After powering up the CS42438, RST should be held low after the power supplies and clocks are settled.18.See Table 7 on page 43 for suggested MCLK frequencies.19.VLS is limited to nominal 2.5 V to 5.0V operation only.20.ADC does not meet timing specification for Quad-Speed Mode.Parameters Symbol Min Max UnitsSlave ModeRST pin Low Pulse Width(Note 17)1-ms MCLK Frequency 0.51250MHz MCLK Duty Cycle(Note 18)4555%Input Sample Rate (FS pin)Single-Speed ModeDouble-Speed Mode (Note 19)Quad-Speed Mode (Note 20)F s F s F s 45010050100200kHz kHz kHz SCLK Duty Cycle 4555%SCLK High Time t sckh 8-ns SCLK Low Timet sckl 8-ns FS Rising Edge to SCLK Rising Edge t fss 5-ns SCLK Rising Edge to FS Falling Edget fsh 16-ns DAC_SDIN Setup Time Before SCLK Rising Edge t ds 3-ns DAC_SDIN Hold Time After SCLK Rising Edge t dh 5-ns DAC_SDIN Hold Time After SCLK Rising Edge t dh15-ns ADC_SDOUT Hold Time After SCLK Rising Edge t dh210-ns ADC_SDOUT Valid Before SCLK Rising Edget dval15-nsFigure 5. TDM Serial Audio Interface Timing。

CS45资料

CS45资料

Symbol Conditions Maximum RatingsI T(RMS)T VJ = T VJM75A I T(AV)M T C = 75°C; 180° sine 48A I TSMT VJ = 45°C t = 10 ms (50 Hz), sine 520A V R = 0 V t = 8.3 ms (60 Hz), sine 560A T VJ = T VJM t = 10 ms (50 Hz), sine 460A V R = 0 Vt = 8.3 ms (60 Hz), sine 500A I 2tT VJ = 45°C t = 10 ms (50 Hz), sine 1350A 2s V R = 0 V t = 8.3 ms (60 Hz), sine 1300A 2s T VJ = T VJM t = 10 ms (50 Hz), sine 1050A 2s V R = 0 Vt = 8.3 ms (60 Hz), sine1030A 2s (di/dt)crT VJ = T VJM repetitive, I T = 40 A 150A/µsf = 50 Hz, t P = 200 µs V D = 2/3 V DRM I G = 0.3 A non repetitive, I T = I T(AV)M 500A/µs di G /dt = 0.3 A/µs(dv/dt)cr T VJ = T VJM ;V DR = 2/3 V DRM1000V/µs R GK = ¥; method 1 (linear voltage rise)P GM T VJ = T VJM t P =30 µs 10W I T = I T(AV)Mt P =300 µs5W P G(AV)0.5W V RGM 10V T VJ -40...+140°C T VJM 140°C T stg -40...+125°C M d Version io1:mounting torque M30.8...1.2Nm F C Version io1R:mounting force with clip 20 (120)N V ISOL *50/60 Hz, RMS, t = 1 minute, leads-to-tab2500V~Weight6g* Verson io1R onlyFeatures•Thyristor for line frequency •International standard package JEDEC TO-247•Planar passivated chip•Long-term stability of blocking currents and voltages •Version AR isolated and UL registered E153432qEpoxy meets UL 94V-0Applications •Motor control •Power converter •AC power controller•Switch-mode and resonant mode power supplies•Light and temperature controlAdvantages•Easy to mount with 1 screw (isolated mounting screw hole)•Space and weight savings •Simple mounting•Improved temperature and power cyclingData according to IEC 60747IXYS reserves the right to change limits, test conditions and dimensionsPhase Control ThyristorV RSM V RRM TypeV DSM V DRM V V 900 800CS 45-08io113001200CS 45-12io117001600CS 45-16io1CS 45-16io1R030ACGC = Cathode, A = Anode, G = GateTO-247 ADISOPLUS 247TMVersion io1Version io1RGC A GCA back surface** Patent pendingV RRM = 800-1600 V I T(RMS)= 75 A I T(AV)M = 48 A1010010001101001000µst gdI G1101001000100000.1110I GV GmA VmA Symbol ConditionsCharacteristic ValuesI R , I D T VJ = T VJM ; V R = V RRM ; V D = V DRM £5mA V T I T= 80 A; T VJ = 25°C£1.64V V T0For power-loss calculations only (T VJ = 125°C)0.85V r T 11m W V GT V D = 6 V;T VJ = 25°C £ 1.5V T VJ = -40°C £ 1.6V I GT V D = 6 V;T VJ = 25°C £100mA T VJ = -40°C £200mA V GD T VJ = T VJM ;V D = 2/3 V DRM£0.2V I GD £10mA I L T VJ = 25°C; t P = 10 m s£150mAI G = 0.3 A; di G /dt = 0.3 A/µs I H T VJ = 25°C; V D = 6 V; R GK = ¥£100mA t gd T VJ = 25°C; V D = ½ V DRM£2µs I G = 0.3 A; di G /dt = 0.3 A/µs R thJC DC current 0.62K/W R thJH DC current0.82K/W aMax. acceleration, 50 Hz50m/s 2Fig. 1Gate trigger rangeFig. 2Gate controlled delay time t gd204060801001201400204060801000.00.51.0I T A P T W Z thJCFig. 8Fig. 3Fig. 6。

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ACTERISTICS
Parameter *
(Continued) Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
44-pin PLCC 100-pin TQFP
CMOUT LINL LINR MINL MINR SDIN CLKIN CLKOUT XTL1IN XTL1OUT XTL2IN XTL2OUT PIO0 PIO1 D/C RESET PDN VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2 Control Interface and Registers Clock Generator 8 unsigned µ -law A-law decode + D/A Monitor Attenuator + Voltage Reference Serial Input/Output M U X Gain A/D A/D unsigned µ -law A-law encode TSIN TSOUT VREF MOUT1 MOUT2 D/A Output Attenuator Mute LOUTR LOUTL HEADC HEADR HEADL SDOUT SCLK FSYNC
DAC Resolution DAC Differential Nonlinearity Total Dynamic Range Instantaneous Dynamic Range (OLB = 1) Total Harmonic Distortion (OLB = 1) Interchannel Isolation Interchannel Gain Mismatch Frequency Response (Note 1) Programmable Attenuation Attenuation Step Size Absolute Attenuation Step Error Offset Voltage Line Out (All Outputs) TDR IDR THD 16 80 -0.5 0.2 2.55 3.6 7.3 1.8 1.8 3.6 (22 kHz to 100 kHz) Line Out 95 85 80 40 1.5 10 2.8 4.0 8.0 2.0 2.0 4.0 100 -60 ±0.9 0.025 0.2 0.32 0.5 0.5 +0.2 -94.7 0.75 3.08 4.4 8.8 2.2 2.2 4.4 1 Bits LSB dB dB % % % dB dB dB dB dB dB dB dB mV Vpp Vpp Vpp Vpp Vpp Vpp ppm/°C Degree dB
Semiconductor Corporation
CS4215
General Description
The CS4215 is an MwaveTM audio codec.
16-Bit Multimedia Audio Codec
Features
• • • • • • • • • •
Sample Frequencies from 4 kHz to 50 kHz
Line Out (Note 5) Headphone Out (Note 6) Speaker Out (Note 6) Line Out (Note 5) Headphone Out (Note 6) Line Out Headphone (0 to 0.45 Fs) (All Outputs)
Ordering Information: CS4215-KL 0°C to 70°C CS4215-KQ 0°C to 70°C CDB4215 Evaluation Board modems. The analog-to-digital and digital-to-analog converters are 64×oversampled delta-sigma converters with on-chip filters which adapt to the sample frequency selected. The +5V only power requirement makes the CS4215 ideal for use in workstations and personal computers. Integration of microphone and line level inputs, input and output gain setting, along with headphone and monitor speaker driver, results in a very small footprint.
LSB Vpp Vpp Vpp ppm/°C kΩ pF V
Gain Drift Input Resistance Input Capacitance CMOUT Output Voltage (Maximum output current = 400 µA)
Notes: 1. This specification is guaranteed by characterization, not production testing. 2. Very low frequency signals will be slightly distorted when using the HPF. 3. Input resistance is for the input selected. Non-selected inputs have a very high (>1M Ω) input resistance. 4. DC current only. If dynamic loading exists, then CMOUT must be buffered or the performance of ADC’s and DAC’s may be degraded. * Parameter definitions are given at the end of this data sheet. Mwave™ is a trademark of the IBM Corporation. 2 Specifications are subject to change without notice. DS76F2
16-bit Linear, 8-bit Linear, µ-Law, or A-Law Audio Data Coding The CS4215 is a single-chip, stereo, CMOS multimedia codec that supports CD-quality music, Programmable Gain for Analog Inputs FM radio-quality music, telephone-quality speech, and Programmable Attenuation for Analog Outputs On-chip Oscillators +5V Power Supply Microphone and Line Level Analog Inputs Headphone, Speaker, and Line Outputs On-chip Anti-Aliasing/Smoothing Filters Serial Digital Interface
Full Scale Output Voltage Line Output (Note 5) with OLB = 0 Headphone Output (Note 6) Speaker Output-Differential (Note 6) Full Scale Output Voltage Line Output (Note 5) with OLB = 1 Headphone Output (Note 6) Speaker Output-Differential (Note 6) Gain Drift Deviation from Linear Phase Out of Band Energy
This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and previous versions, see Appendix A.
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581
Parameter * Symbol Min Typ Max Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution ADC Differential Nonlinearity Instantaneous Dynamic Range Total Harmonic Distortion Interchannel Isolation Interchannel Gain Mismatch Frequency Response (Note 1) Programmable Input Gain Gain Step Size Absolute Gain Step Error Offset Error with HPF = 0 (No Gain) Offset Error with HPF = 1 (Notes 1,2) (No Gain) Full Scale Input Voltage: Line Inputs (AC Coupled) Line Inputs (DC Coupled) Mic Inputs Line Inputs (AC Coupled) Line Inputs (DC Coupled) Mic Inputs (MLB=0) Mic Inputs (MLB=1) Mic Inputs Line Inputs Line Inputs Mic Inputs Line Inputs Mic Inputs Line to Line Inputs Line to Mic Inputs Line Inputs Mic Inputs (0 to 0.45 Fs) Line Inputs Mic Inputs IDR THD 16 80 72 -0.5 -0.2 19.8 0.250 2.50 2.50 (Note 3) 20 (Note 4) 1.9 84 78 80 60 1.5 ±150 ±10 ±400 0 0 0 0.28 2.8 2.8 100 2.1 ±0.9 0.012 0.032 0.5 0.5 +0.2 23.5 44 0.75 ±400 ±150 ±5 ±5 ±5 0.310 3.10 3.10 15 2.3 Bits LSB dB dB % % dB dB dB dB dB dB dB dB dB LSB
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