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HCS08系列微控制器参考手册(中文)

HCS08系列微控制器参考手册第一册苏州大学飞思卡尔嵌入式系统研发中心翻译 2009年11月目录第一章通用信息与结构框图 (1)1.1HCS08系列微控制器介绍 (1)1.2HCS08CPU编程模型 (2)1.3外设模块 (2)1.4MC9S08GB60的特点 (3)1.4.1 HCS08系列的共性 (3)1.4.2 MC9S08GB60的特点 (3)1.5MC9S08GB60的结构框图 (4)第二章引脚及其连接 (5)2.1简介 (5)2.2推荐的系统连接 (5)2.2.1 电源 (7)2.2.2 MC9S08GB60振荡器 (7)2.2.3 复位 (8)2.2.4 背景/模式选择(BKGD/MS) (8)2.2.5 通用I/O及外设端口 (8)第三章工作模式 (10)3.1简介 (10)3.2特征 (10)3.3运行模式 (10)3.4背景调试模式 (11)3.5等待模式 (12)3.6停止模式 (12)3.6.1 Stop1模式 (13)3.6.2 Stop2模式 (13)3.6.3 Stop3模式 (14)3.6.4 停止模式下激活BDM使能 (14)3.6.5 设置OSCSTEN位 (15)3.6.6 停止模式下LVD使能 (15)3.6.7 停止模式下的片上外设模块 (15)3.6.8 系统选择寄存器(SOPT) (17)3.6.9 系统电源管理状态和控制寄存器1(SPMSC1) (18)3.6.10 系统电源管理状态和控制寄存器2(SPMSC2) (19)第四章片上存储器 (21)4.1简介 (21)4.2HCS08核定义的存储器组织 (21)4.2.1 HCS08存储器组织 (21)4.2.2 MC9S08GB60存储映像 (22)4.2.3 复位和中断向量表 (23)4.3寄存器地址和位分配 (24)4.4RAM (29)4.560K字节的FLASH (29)4.5.1 特征 (30)4.5.2 写入、擦除和空白检测命令 (30)4.5.3 命令时间和突发模式写入 (32)4.5.3.1 行和FLASH的组织结构 (32)4.5.3.2 程序命令时序 (33)4.5.4 访问错误 (34)4.5.5 向量重定向 (34)4.5.6 FLASH块保护(MC9S08GB60) (34)4.6MC9S08GB60的安全性 (35)4.7MC9S08GB60的FLASH寄存器和控制位 (36)4.7.1 FLASH时钟分频寄存器(FCDIV) (36)4.7.2 FLASH选项寄存器(FOPT和NVOPT) (37)4.7.3 FLASH配置寄存器(FCNFG) (38)4.7.4 FLASH保护寄存器(FPROT和NVPROT) (38)4.7.5 FLASH状态寄存器(FSTAT) (39)4.7.6 FLASH命令寄存器(FCMD) (40)4.8FLASH存储器应用实例 (41)4.8.1 FLASH模块时钟的初始化 (41)4.8.2 擦除FLASH的一页(512字节) (42)4.8.3 DoOnStack子程序 (43)4.8.4 SpSub子程序 (45)4.8.5 FLASH的字节编程 (46)第五章复位和中断 (47)5.1简介 (47)5.2MC9S08GB60复位和中断的特征 (47)5.4计算机正常操作监控模块(COP)看门狗 (48)5.5中断 (48)5.5.1 中断堆栈结构 (49)5.5.2 外部中断请求(IRQ)引脚 (50)5.5.2.1 引脚配置选项 (50)5.5.2.2 边沿/电平触发 (50)5.5.3 中断向量、中断源和局部屏蔽 (51)5.6低电压检测系统(LVD) (52)5.6.1 上电复位操作 (52)5.6.2 LVD复位操作 (52)5.6.3 LVD中断操作 (53)5.6.4 低电压警告(LVW) (53)5.7实时中断(RTI) (53)5.8复位、中断以及系统控制寄存器和控制位 (53)5.8.1 中断请求状态和控制寄存器(IRQSC) (54)5.8.2 系统复位状态寄存器(SRS) (55)5.8.3 系统背景调试强制复位寄存器(SBDFR) (56)5.8.4 系统选项寄存器(SOPT) (56)5.8.5 系统设备识别寄存器(SDIDH、SDIDL) (57)5.8.6 系统实时中断状态和控制寄存器(SRTISC) (57)5.8.7 系统电源管理状态控制寄存器1(SPMSC1) (58)5.8.8 系统电源管理状态和控制寄存器2(SPMSC2) (59)第六章中央处理单元 (61)6.1简介 (61)6.2编程结构和CPU寄存器 (61)6.2.1 累加器(A) (62)6.2.2 变址寄存器(H:X) (63)6.2.3 堆栈指针(SP) (64)6.2.4 程序计数器(PC) (66)6.2.5 条件码寄存器(CCR) (66)6.3寻址方式 (70)6.3.1 隐含寻址方式(INH) (71)6.3.2 相对寻址方式(REL) (71)6.3.3 立即寻址方式(IMM) (72)6.3.4 直接寻址方式(DIR) (72)6.3.5 扩展寻址方式(EXT) (72)6.3.6.1 无偏移量变址方式(IX) (73)6.3.6.2 无偏移量变址、变址加1寻址方式(IX+) (73)6.3.6.3 8位偏移量变址方式(IX1) (73)6.3.6.4 8位偏移量变址、变址加1寻址方式(IX1+) (73)6.3.6.5 16位偏移量变址方式(IX2) (73)6.3.6.6 8位偏移量堆栈寻址方式(SP1) (74)6.3.6.7 16位偏移量堆栈寻址方式(SP2) (74)6.4特殊操作 (75)6.4.1 复位序列 (75)6.4.2 中断 (76)6.4.3 等待模式 (76)6.4.4 停止模式 (76)6.4.5 背景模式 (77)6.4.6 总线周期的用户观点 (77)6.5通过指令类别进行指令集描述 (78)6.5.1 数据传送指令 (78)6.5.1.1 加载与存储 (78)6.5.1.2 位的置位与清零 (81)6.5.1.3 存储器到存储器的传送 (82)6.5.1.4 寄存器传输和半字节交换 (82)6.5.2 算术运算指令 (83)6.5.2.1 加、减、乘和除指令 (83)6.5.2.2 加一、减一、清零和求补 (88)6.5.2.3 比较和测试 (88)6.5.2.4 BCD的计算 (88)6.5.3 逻辑操作指令 (89)6.5.3.1 与、或、异或与求补 (90)6.5.3.2 位测试指令 (91)6.5.4 移位类指令 (91)6.5.5 跳转、转移和循环控制指令 (93)6.5.5.1 无条件跳转和转移指令 (94)6.5.5.2 简单转移 (95)6.5.5.3 有符号转移 (95)6.5.5.4 无符号转移 (95)6.5.5.5 位条件转移 (96)6.5.5.6 循环控制 (96)6.5.6 相关堆栈指令 (97)6.6指令简表 (102)6.7汇编语言指南 (114)6.7.1 列表行 (115)6.7.2 汇编指令 (116)6.7.2.1 BASE——设定编译器的缺省数进制 (116)6.7.2.2 INCLUDE——指定附加源文件 (116)6.7.2.3 NOLIST/LIST——关闭或打开程序列表 (116)6.7.2.4 ORG——设置程序的起始位置 (117)6.7.2.5 EQU——把一个标号和一个数值相关联 (118)6.7.2.6 dc.b——定义存储器中字节化常量 (119)6.7.2.7 dc.w——在存储器中定义16位(字)常量 (119)6.7.2.8 ds.b——定义存储(保留)内存变量字节 (120)6.7.3 标号 (121)6.7.4 表达式 (122)6.7.5 通用文件协议 (123)6.7.6 目标代码(S19)文件 (125)第七章开发支持 (129)7.1介绍 (129)7.2特点 (130)7.3背景调试控制器(BDC) (130)7.3.1 BKGD引脚描述 (131)7.3.2 通信细节 (132)7.3.2.1 BDC通信速率考虑事项 (132)7.3.2.2 位时序细节 (133)7.3.3 BDC寄存器和控制位 (135)7.3.3.1 BDC状态和控制寄存器 (135)7.3.3.2 BDC断点匹配寄存器 (137)7.3.4 BDC命令 (137)7.3.4.1 SYNC——要求时序参考脉冲 (138)7.3.4.2 ACK_ENABLE (139)7.3.4.3 ACK_DISABLE (139)7.3.4.4 BACKGROUND (139)7.3.4.5 READ_STATUS (140)7.3.4.6 WRITE_CONTROL (140)7.3.4.7 READ_BYTE (141)7.3.4.8 READ_BYTE_WS (142)7.3.4.10 WRITE_BYTE (143)7.3.4.11 WRITE_BYTE_WS (143)7.3.4.12 READ_BKPT (144)7.3.4.13 WRITE_BKPT (144)7.3.4.14 GO (144)7.3.4.15 TRACE1 (145)7.3.4.16 TAGGO (145)7.3.4.17 READ_A (145)7.3.4.18 READ_CCR (145)7.3.4.19 READ_PC (146)7.3.4.20 READ_HX (146)7.3.4.21 READ_SP (147)7.3.4.22 READ_NEXT (147)7.3.4.23 READ_NEXT_WS (148)7.3.4.24 WRITE_A (148)7.3.4.25 WRITE_CCR (148)7.3.4.26 WRITE_PC (149)7.3.4.27 WRITE_HX (149)7.3.4.28 WRITE_SP (149)7.3.4.29 WRITE_NEXT (149)7.3.4.30 WRITE_ NEXT_WS (150)7.3.5 串行接口硬件握手协议 (150)7.3.6 取消握手协议 (152)7.3.7 BDC硬件断点 (155)7.3.8 与M68HC12BDM的不同之处 (155)7.3.8.1 8位体系结构 (156)7.3.8.2 命令格式 (156)7.3.8.3 状态位的读写 (156)7.3.8.4 BDM与停止和等待模式 (157)7.3.8.5 SYNC指令 (157)7.3.8.6 硬件断点 (157)7.4标识部分和BDC强制复位 (158)7.4.1 系统设备识别寄存器(SDIDH:SDIDL) (158)7.4.2 系统背景调试强制复位寄存器 (158)7.5片上调试系统(DBG) (159)7.5.1 比较器A和B (159)7.5.2总线信息捕捉和FIFO操作 (160)7.5.4 标记与强制断点和触发器 (161)7.5.5 CPU断点请求 (162)7.5.6 触发模式 (162)7.5.6.1 单独A触发模式 (163)7.5.6.2 A或B触发模式 (163)7.5.6.3 A然后B触发模式 (163)7.5.6.4 事件B触发模式(存储数据) (163)7.5.6.5 A然后事件B触发模式(存储数据) (163)7.5.6.6 A和B数据触发(全模式) (164)7.5.6.7 A与非B数据触发(全模式) (164)7.5.6.8 触发范围内：A≤地址≤B (164)7.5.6.9 触发范围外：地址<A 或者地址>B (164)7.5.7 DBG寄存器和控制位 (165)7.5.7.1 调试比较器Ａ的高地址页寄存器(DBGCAH) (165)7.5.7.2 调试比较器Ａ的低位寄存器(DBGCAL) (165)7.5.7.3 调试比较器B的高地址页寄存器(DBGCAH) (165)7.5.7.4 调试比较器B的低位寄存器(DBGCAL) (165)7.5.7.5 调试FIFO高地址页寄存器(DBGFH) (165)7.5.7.6 调试FIFO低位寄存器(DBGFL) (165)7.5.7.7 调试控制寄存器(DBGC) (166)7.5.7.8 调试触发寄存器(DBGT) (167)7.5.7.9 调试状态寄存器(DBGS) (168)7.5.8 应用信息与举例 (169)7.5.8.1 定向的调试器例子 (171)7.5.8.2 例1：终止对地址A的处理 (171)7.5.8.3 例2：终止对地址A指令的处理 (172)7.5.8.4 例3：终止在地址A或B上的指令处理 (172)7.5.8.5 例4：开始跟踪在地址A的指令 (173)7.5.8.6 例5：A到B顺序后停止的尾部跟踪 (173)7.5.8.7 例6：起始跟踪数据B写入地址A (174)7.5.8.8 例7：从地址B中读取被捕获的首八位数据 (174)7.5.8.9 例8：捕获在读地址A后写入到地址B的值 (175)7.5.8.10 例9：在一个例程中触发所有的执行命令 (175)7.5.8.11 例10：通过触发来试图处理外部FLASH (176)7.5.9 硬件断点和ROM修补 (176)附录A 指令集详述 (177)A.2命名规则 (177)A.3规范定义 (180)A.4指令集 (180)ADC Add with Carry(带进位位加) (180)ADD Add without Carry(无进位位加) (181)AIS Add Immediate Value to Stack Pointer(立即数加到SP) (182)AIX Add Immediate Value to Index Register(立即数加到HX) (182)AND Logical AND(逻辑与) (183)ASL Arithmetic Shift Left(算术左移) (184)ASR Arithmetic Shift Right(算术右移) (184)BCC Branch if Carry Bit Clear(C为0则转移) (185)BCLR n Clear Bit n in Memory(内存单元n位清零) (185)BCS Branch if Carry Bit Set(C为1则转移) (186)BEQ Branch if Equal(等于则转移) (187)BGE Branch if Greater Than or Equal To(大于或等于则转移) (187)BGND Background(进入背景调试模式) (188)BGT Branch if Greater Than(大于则转移) (188)BHCC Branch if Half Carry Bit Clear(H为0则转移) (189)BHCS Branch if Half Carry Bit Set(H为1则转移) (189)BHI Branch if Higher(大于则转移) (190)BHS Branch if Higher or Same(大于或等于则转移) (191)BIH Branch if IRQ Pin High(引脚IRQ为1则转移) (191)BIL Branch if IRQ Pin Low(引脚IRQ为0则转移) (192)BIT Bit Test(位测试) (192)BLE Branch if Less Than or Equal To(小于或等于则转移) (193)BLO Branch if Lower(小于则转移) (193)BLS Branch if Lower or Same(小于或等于则转移) (194)BLT Branch if Less Than(小于则转移) (195)BMC Branch if Interrupt Mask Clear(I为0则转移) (195)BMI Branch if Minus(结果为负则转移) (196)BMS Branch if Interrupt Mask Set(I为1则转移) (196)BNE Branch if Not Equal(不等于则转移) (197)BPL Branch if Plus(结果为正则转移) (197)BRA Branch Always(无条件短转移) (198)BRCLR n Branch if Bit n in Memory Clear(M位n为0则转移) (199)BRN Branch Never(三个总线周期的空操作) (200)BRSET n Branch if Bit n in Memory Set(M位n为1则转移) (200)BSET n Set Bit n in Memory(M位n置1) (201)BSR Branch to Subroutine(转移到子程序) (201)CBEQ Compare and Branch if Equal(比较，等于则转移) (202)CLC Clear Carry Bit(进位位C清零) (203)CLI Clear Interrupt Mask Bit(中断屏蔽位I清零) (203)CLR Clear(清零) (204)CMP Compare Accumulator with Memory(A与M比较) (204)COM Complement(按位取反) (205)CPHX Compare Index Register with Memory(HX与M比较) (206)CPX Compare X with Memory(X与M比较) (207)DAA Decimal Adjust Accumulator(A十进制调整) (208)DBNZ Decrement and Branch if Not Zero(减1不为0则转移) (209)DEC Decrement(自减1) (209)DIV Divide(无符号除法) (210)EOR Exclusive-OR Memory with Accumulator(M与A异或) (211)INC Increment(自加1) (211)JMP Jump(无条件跳转) (212)JSR Jump to Subroutine(跳转到子程序) (213)LDA Load Accumulator form Memory(取M内容到A) (213)LDHX Load Index Register form Memory(取M内容到HX) (214)LDX Load X from Memory(取M内容到X) (215)LSL Logical Shift Left(逻辑左移) (215)LSR Logical Shift Right(逻辑右移) (216)MOV Move(M单元间数据传送) (217)MUL Unsigned Multiply(无符号数乘法) (218)NEG Negate(Two’s Complement) (求补) (218)NOP No Operation(空操作) (219)NSA Nibble Swap Accumulator(A的高低4位对调) (219)ORA Inclusive-OR Accumulator and Memory(逻辑或) (220)PSHA Push Accumulator onto Stack(A进栈) (220)PSHH Push H onto Stack(H进栈) (221)PSHX Push X onto Stack(X进栈) (221)PULA Pull Accumulator from Stack(A出栈) (222)PULH Pull H from Stack(H出栈) (222)PULX Pull X from Stack(X出栈) (223)ROL Rotate Left through Carry(带进位位的循环左移) (223)ROR Rotate Right through Carry(带进位位的循环右移) (224)RSP Reset Stack Pointer(堆栈指针置$FF) (224)RTI Return from interrupt(中断返回) (225)RTS Return from Subroutine(子程序返回) (226)SBC Subtract with Carry(带借位减法) (226)SEC Set Carry Bit(进位位置位) (227)SEI Set Interrupt Mask Bit(中断屏蔽位置位) (227)STA Store Accumulator in Memory(A存入M) (228)STHX Store Index Register(HX存入M) (229)STOP Enable IRQ Pin, Stop Processing(停机) (229)STX Store X in Memory(X存入M) (230)SUB Subtract(无借位减法) (231)SWI Software Interrupt(软件中断) (231)TAP Transfer Accumulator to Processor Status Byte(写CCR) (232)TAX Transfer Accumulator to X(A复制到X) (233)TPA Transfer Processor Status Byte to Accumulator(读CCR) (233)TST Test for Negative or Zero(小于或等于0测试) (234)TSX Transfer Stack Pointer to index Register(复制SP到HX) (235)TXA Transfer X to Accumulator(复制X到A) (235)TXS Transfer Index Register Low to Stack Pointer(HX-1写入SP) (235)WAIT Enable Interrupts; Stop Processor(待机) (236)附录B 通用文件规范 (237)B.1引言 (237)B.2存储映射区域划分 (238)B.3中断向量定义 (238)B.4位定义的两种方式 (239)B.5MC9S08GB60完整的通用文件 (240)第一章通用信息与结构框图1.1 HCS08系列微控制器介绍新型的FreescaleHCS08系列微控制器，尽管包含新指令，可以执行快速调试和开发功能，但仍然和旧的M68HC08系列完全兼容。

数据手册_HR6P60HL_Datasheet_C V2.2

关于芯片的开发环境
海尔 MCU 芯片具有完整的软/硬件开发环境，并受知识产权保护。选择上海海尔集成电路有限公司或其指定的第三方公司的汇编器、编译器、编程器、硬件仿真器开发环境，必须遵循与芯片相关的规定和说明。
注：在产品开发时，如遇到不清楚的地方，请用下述联系方式与上海海尔集成电路有限公司联系。
V2.2 版权所有©上海海尔集成电路有限公司
关于芯片的 ESD 防护措施
海尔 MCU 芯片具有满足工业级 ESD 标准保护电路。建议用户根据芯片存储/应用的环境采取适当静电防护措施。应注意应用环境的湿度；建议避免使用容易产生静电的绝缘体；存放和运输应在抗静电容器、抗静电屏蔽袋或导电材料容器中；包括工作台在内的所有测试和测量工具必须保证接地；操作者应该佩戴静电消除手腕环手套，不能用手直接接触芯片等。
HR6P60HL 数据手册
海尔 MCU 芯片使用注意事项
关于芯片的上/下电海尔 MCU 芯片具有独立电源管脚。当 MCU 芯片应用在多电源供电系统时，应先对 MCU 芯片上电，再对系统其他部件上电；反之，下电时，先对系统其他部件下电，再对 MCU 芯片下电。若操作顺序相反则
可能导致芯片内部元件过压或过流，从而导致芯片故障或元件退化。具体可参照芯Hale Waihona Puke 的数据手册说明。关于芯片的时钟
海尔 MCU 芯片具有内部和外部时钟源。内部时钟源会随着温度、电压变化而偏移，可能会影响时钟源精度；外部时钟源采用陶瓷、晶体振荡器电路时，建议使能起振延时；使用 RC 振荡电路时，需考虑电容、电阻匹配；采用外部有源晶振或时钟输入时，需考虑输入高/低电平电压。具体可参照芯片的数据手册说明。
3. 2
第 4 章 4. 1 4. 2 4. 3 4. 4 4. 5

EP2C8Q208C8中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」

Cyclone II器件手册,第1卷ii内容章修订日期............................................... ............................喜关于本手册............................................... .............................十三如何触点Altera ..........................................................................................................................十三印刷约定....................................................................................................................十三第一节Cyclone II器件系列数据表修订记录.................................................................................................................................... 1-1第1章简介简介............................................................................................................................................低成本嵌入式处理解决方案............................................ ......................................低成本DSP解决方案.................................................................................................................特征...................................................................................................................................................参考文献.........................................................................................................................文档修订历史记录.................................................................................................................1–1 1–1 1–1 1–2 1–9 1–9第2章Cyclone II架构功能说明.......................................................................................................................... 2-1逻辑元件....................................................................................................................................... 2-2LE操作模式........................................................................................................................ 2-4逻辑阵列模块................................................................................................................................ 2-7LAB互连............................................................................................................................ 2-8LAB控制信号......................................................................................................................... 2-8MultiTrack互联..................................................................................................................... 2-10行互连.......................................................................................................................... 2-10列互连.................................................................................................................... 2-12设备路由............................................................................................................................... 2-15全局时钟网络和锁相环.......................................... ..................................... 2-16专用时钟管脚..................................................................................................................... 2-20双用时钟引脚.............................................................................................................. 2-20全局时钟网络................................................................................................................... 2-21全局时钟网络分布.............................................. .............................................. 2-23锁相环.................................................................................................................................................. 2-25嵌入式存储器............................................................................................................................. 2-27内存模式............................................................................................................................... 2-30时钟模式.................................................................................................................................... 2-31M4K路由接口.................................................................................................................. 2-31iii内容嵌入式乘法器........................................................................................................................乘法器模式............................................................................................................................嵌入式乘法器路由接口.............................................. .......................................I / O结构及特点....................................................................................................................外部存储器接口.......................................................................................................可编程驱动强度.....................................................................................................漏极开路输出........................................................................................................................摆率控制...........................................................................................................................总线防护持..........................................................................................................................................可编程上拉电阻............................................. .................................................. ...高级I / O标准支持............................................ .................................................. ..高速差分接口............................................. .................................................系列片上端接.........................................................................................................I / O组........................................................................................................................................多电压I / O接口.................................................................................................................2–32 2–35 2–36 2–37 2–44 2–49 2–50 2–51 2–51 2–51 2–52 2–53 2–55 2–57 2–60第3章配置与测试IEEE标准. 1149.1（JTAG）边界扫描支持........................................... ..................................构造.........................................................................................................................................操作模式...................................................................................................................................配置计划......................................................................................................................... Cyclone II自动单粒子翻转检测........................................... ...........................定制电路....................................................................................................................软件界面.............................................................................................................................文档修订历史记录.................................................................................................................3–1 3–5 3–5 3–6 3–7 3–7 3–7 3–8第4章热插拔和上电复位简介............................................................................................................................................旋风II热插拔规格............................................ ................................................设备可以在电源时会驱动.......................................... ...........................................I / O引脚防护持三态电期间...................................... ......................................在Cyclone II器件热插拔功能实现......................................... ..............上电复位电路...................................................................................................................."唤醒"时间Cyclone II器件........................................ ...............................................结论..............................................................................................................................................文档修订历史记录.................................................................................................................4–1 4–1 4–2 4–2 4–3 4–5 4–5 4–7 4–7第5章直流特性和时序规范运行条件........................................................................................................................... 5-1单端I / O标准.......................................................................................................... 5-5差分I / O标准.............................................................................................................. 5-7DC特性不同针类型............................................ ......................................... 5-11片上端接规格............................................. .............................................. 5-12能量消耗........................................................................................................................... 5-13时序规格.......................................................................................................................... 5-14预,决赛时序规范............................................. ................................ 5-14演出.................................................................................................................................... 5-15 ivCyclone II器件手册,第1卷内容内部时序...............................................................................................................................Cyclone II时钟时序参数............................................. ..............................................时钟网络偏移加法器.......................................................................................................IOE可编程延迟.............................................................................................................不同I默认容性负载/ O标准......................................... .................I / O延迟.......................................................................................................................................最大输入和输出时钟频率............................................ ........................................高速I / O时序规格........................................... ............................................外部存储器接口规范.............................................. ....................................JTAG时序规范..........................................................................................................PLL时序规范............................................................................................................占空比失真.........................................................................................................................DCD测量技术............................................... .................................................. ..参考文献.......................................................................................................................文档修订历史记录...............................................................................................................5–18 5–23 5–29 5–30 5–31 5–33 5–46 5–55 5–63 5–64 5–66 5–67 5–68 5–74 5–74第6章参考和订购信息软体..................................................................................................................................................器件引脚输出.....................................................................................................................................订购信息...........................................................................................................................文档修订历史记录.................................................................................................................6–1 6–1 6–1 6–2第二节.时钟管理修订记录.................................................................................................................................... 6-1第7章锁相环在Cyclone II器件简介............................................................................................................................................ 7-1Cyclone II PLL硬件概述............................................. .................................................. ... 7-2PLL参考时钟产生.............................................. .................................................. ... 7-6时钟反馈模式....................................................................................................................... 7-10正常模式.................................................................................................................................. 7-10零延迟缓冲器模式................................................................................................................ 7-11无补偿模式............................................................................................................... 7-12源同步模式........................................................................................................... 7-13硬件特性.............................................................................................................................. 7-14时钟倍频和科.............................................. .................................................. .. 7-14可编程占空比........................................................................................................... 7-15移相实施.............................................. .................................................. .... 7-16控制信号................................................................................................................................ 7-17手动时钟切换............................................................................................................. 7-20时钟................................................................................................................................................ 7-21全局时钟网络................................................................................................................... 7-21时钟控制模块....................................................................................................................... 7-24全局时钟网络时钟源产生............................................ .......................... 7-26全局时钟网络掉电............................................. .............................................. 7-28vCyclone II器件手册,第1卷。

催化-8-2

带入上面得: ErI = q - S/2 + U/2 = q –(QAB + QCD)
ErII = -q + S/2 + U/2= -q +( QAC + QBD) 对某一反应: U, S 是常数, ErI , ErII 只与吸附q有关, 而不同的催化剂有不同的q. 若以q和E为坐标做图，当反应物为吸热反应时，QAB + QCD > QAC + QBD, U<0, 曲线如图a, 当反应物为放热反应时，QAB + QCD<QAC + QBD, U>0, 曲线如b，均为火山型曲线。其中曲线交点E，意味着ErI =ErII, 这时, q = S/2, ErI =ErII = 1U/2，对于反应所选某一催化剂，若它与反应物及生成物的总吸附键能q位于E点左侧，即q<S/2，吸附能小于反应物和产物键能和
(100)
(110)
(111)
当n-m为0.248时， = 105, 当n-m为0.351时， = 122.6 由于105-109=4太小，强吸附，加氢活性差。而在100，110晶面上有0.351nm的m-m，所以加氢活性比在(111)
8.2.2 与d%关联
晶面好，由于Rh,Pd,Pt晶体内m-m介于0.36-0.36nm，更大，所以活性好，而Fe,W 则由于太大，乙烯无法双位吸附，所以活性小。
Q, kcal/mol
8.2.2 与d%关联
140
8.2.2 与d%关联
金属Cat表面与反应物的作用强弱，与金属Cat表面原子的电子性质有关，而吸附热的强弱,催化反应活性大小只是它们相互之间作用强弱的表现形式，催化过程要求这种相互作用既不特强又不特弱,作用太强，成为反应控制的化学计量反应，速度慢，太弱，不能使反应物活化，这就是火山型关系揭示的催化作用的一个性质。 8.2.3: 多位理论：上世纪50年代由苏联科学家bilanjin提出的. 多位理论：在金属催化反应中，需要几个具有一定几何排布的的金属原子（活性中心）协同作用才能完成反应，这几个被称为活性中心的金属原子组成一个多位体，多位体的几何性质与反应物的几何结构要相适应－几何对应原则，反应物吸附活化所放出的能量与产物脱附所需要的能量相对应－能量对应原则。

SL2.2S规格书,usb HUB大全,替换FE1.1S,GL850,GL852,PL2586

USB2.0 HUB控制器集成电路USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLERSL2.2s数据手册Data Sheet内容目录第一章管脚分配 (3)1.1 SL2.2S管脚图 (3)1.2 SL2.2S管脚定义 (3)第二章功能叙述 (5)2.1综述 (5)2.2指示灯 (5)2.2.1单灯方案 (5)2.2.2多灯方案 (6)2.2.3 LED指示定义 (6)2.3过流保护 (6)2.4充电支持 (6)2.5I2C接口 (7)2.6EEPROM设置 (7)第三章电气特性 (8)3.1极限工作条件 (8)3.2工作范围 (8)3.3直流电特性 (8)3.4HS/FS/LS电气特性 (8)3.5ESD特性 (8)附录一封装 (9)表格目录表格1: 端口LED定义 (6)表格 2 : ACTIVE LED定义 (6)表格3：EEPROM数据结构定义 (7)表格4: 最大额定值 (8)表格5: 工作范围 (8)表格6: 直流电特性 (8)插图目录图1：SSOP28 管脚图 (3)图2：单灯方案配置 (5)图3: 5灯方案配置 ............................................................................... (6)图 4：附录封装图 ................................................................................... .9第一章管脚分配1.1SL2.2s管脚图图1：SSOP28 管脚图1.2SL2.2s管脚定义管脚名称28Die IO类型定义Pin#VSS 1 P 芯片地XOUT 2 O晶振PAD XIN 3 IDM4 4 B下行口4的USB信号DP4 5 BDM3 6 B下行口3的USB信号DP3 7 BDM2 8 B下行口2的USB信号DP2 9 BDM1 10 B下行口1的USB信号DP1 11 BVDD18 12 P 模拟1.8vVDD33 13 P 模拟3.3v - 14 NCUDM 15 B上行口的USB信号UDP 16 BRESET_N 17 I,Pu 芯片外部复位输入- 18 NCPSELF 19 I,Pu 高为自供电，低为总线供电VDD5 20 P 5v输入VDD33 21 P 3.3v输出DRV 22 B,Pu 点灯驱动信号LED1 23 B,Pu 点灯驱动信号LED2 24 B,Pu 点灯驱动信号PWRN 25 B,Pu 下行口电源输出控制，低有效OVCRN/SDA 26 B,PuI2C SDA数据线，内部上拉；芯片初始化完成后作为过流保护输入脚，低有效SCL 27 B,Pu I2C SCL时钟输出VDD18 28 P 数字1.8v注释：O，输出；I 输入；B 双向；P 电源/接地；Pu 上拉；Pd 下拉；NC 悬空；第二章功能叙述2.1综述SL2.2s 是一颗高集成度,高性能,低功耗的USB2.0集线器主控芯片；该芯片采用STT 技术,单电源供电方式，芯片供电电压为5v , 内部集成5V 转3.3V,只需在外部电源添加滤波电容；芯片自带复位电路，低功耗技术让他更加出众。

H8206用户手册00

H8206 典型参考特性
H8206
操作说明：
6W 双通道 F 类，带耳机驱动、无 FM 干扰、过热保护功能音频功放
1.如果 H8206 有接 LC 滤波电路时，应当先接上喇叭再上电，否则极易损坏芯片。 2.如果 H8206 没有接 LC 滤波电路时，应当在输出端增加一个磁珠，以抑制电磁干扰。 3.H8206 的工作电压为 5.5V。如果 H8206 要用 4 个电池供电时，建议不要使用 4 个全新的电池或者碱性电池，因为这样供电电压会超过 6V，高于 H8206 的工作电压，极易损坏设备。因此我们们推荐使用 4 个镍氢电池（镍氢）充电电池或三个干电池供电。 4.使用 H8206 时，输入信号不应过大，大信号输入会导致输出信号出现削波失真，同时大信号大增益时将会损坏芯片。 5.H8206 没有接 LC 滤波电路时，如果用假负载电阻代替喇叭作测试，测出的 THD 及效率都会比用喇叭时测试的效果要差。因此，建议用喇叭进行测试。
低电压保护(UVLO)
H8206还集成了低电压保护电路，当电压低于2.0V时就关断功放输出，该设计可有效防止低电压工作时产生的噪音。
短路保护 (SCP)
H8206在输出端导入了短路保护功能，可有效防止输出之间短接或者输出接地时对功放芯片造成的损害。当输出短路，芯片马上会终止输出，直到检输出接线正常，芯片会自动恢重正常工作。
H8206 原理框图
ቤተ መጻሕፍቲ ባይዱ
H8206
芯片定购信息
芯片型号 H8206ESOP
6W 双通道 F 类，带耳机驱动、无 FM 干扰、过热保护功能音频功放
封装类型 ESOP16
包装类型管装
最小包装数量（PCS） 50/管
备注带散热片

第2章 Freescale HC(S)08系列单片机概述

第2章Freescale HC08/S08/RS08 MCU概述Freescale的08系列单片机由于其稳定性高、开发周期短、成本低、型号多种多样、兼容性好而被广泛应用。

本章概要介绍08系列单片机的类型、基本结构，并从总体上阐述其性能特点。

主要内容有：在介绍08系列单片机的命名规则和资源状况的基础上，分别以MC908GP32、MC9S08GB60及MC9RS08KA2为例讲述HC08系列、HCS08系列及RS08系列单片机的基本结构和特点。

了解这些基本知识，不仅可以为实际开发应用中的单片机选型提供参考，也对后续章节的学习有很大的帮助。

本书以GP32为主要芯片阐述嵌入式系统基本硬件与软件原理，2.2节讨论的GP32引脚功能、硬件最小系统及GP32的存储器框图是重点掌握的内容。

硬件最小系统是芯片运行的基本条件，应该对此有清晰的理解。

对于GP32不具备的功能，本书将使用其他芯片进行阐述，但编程语言体系是相同的。

2.1 08系列单片机简介目前，Freescale的08系列单片机主要有HC08、HCS08和RS08三种类型。

HC08是1999年开始推出的产品，种类也比较多，针对不同场合的应用都可以选到合适的型号。

HCS08是2004年左右推出的8位MCU，资源丰富，功耗低，性价比很高，是08系列单片机的发展趋势。

HC08与HCS08的最大区别是调试方法不同与最高频率的变化。

RS08是HCS08架构的简化版本，于2006年推出，其内核体积比传统的内核小30%，带有精简指令集，满足用户对体积更小、更加经济高效的解决方案的需求。

RAM及Flash 空间大小差异、封装形式不同、温度范围不同、频率不同、I/O资源差异等形成了不同型号，为嵌入式应用产品的开发提供了丰富的选型。

2.1.1 Freescale单片机的命名规则Freescale单片机的型号庞大，但同一系列的CPU是相同的，也就是说具有相同的指令系统，多种型号只是为了适用于不同的场合。

安富利 68HC08 PWM 控制应用笔记 AN2876说明书

Freescale Semiconductor Application NoteAN2876 Rev. 1.0, 07/2005Programming the Pulse-Width Modulator for Motor Control(PWMMC) on HC08 MicrocontrollersUsing MC68HC08MR Series to Demonstrate PWM Techniques By Jorge Zambada TinocoRTAC AmericasMexico 2005IntroductionThis document is intended to serve as a quick reference for an embedded engineer to get thepulse-width-modulation (PWM) module up and running for any HC08 MCU that includes this module. Basic knowledge about the functional description and configuration options will give the user a better understanding on how the PWM module works. This application note provides an example that demonstrates one use of the PWM module within the HC08 Family of microcontrollers. The examples mentioned are intended to be modified to suit the specific needs for any application.The complete software files for the example described in this document is available as AN2876SW.zip free-of-charge from the Freescale Semiconductor web site: PWM ModulePWM ModuleThe PWM module included in the MC68HC08MR Series of microcontrollers is a motor-control-oriented pulse-width modulator capable of generating three complementary PWM pairs or six independent PWM signals. A 12-bit timer PWM counter is common to all six channels. PWM resolution is one clock period for edge-aligned operation and two clock periods for center-aligned operation. The clock period is dependent on the internal operating frequency (f OP) and a programmable prescaler. The highest resolution for edge-aligned operation is 125 ns (f OP = 8 MHz) and the highest resolution for center-aligned operation is 250 ns (f OP = 8 MHz). Some of the features of the PWM module are:•Three complementary pairs or six independent PWM signals on six output pins•Edge-aligned PWM signals or center-aligned PWM signals•PWM signals polarity control•20-mA current sink capability on PWM pins•Manual PWM output control through software•Programmable fault protection (two FAULT input pins on the MR8 and four FAULT input pins on the MR16/32)•Complementary mode featuring:–Dead-time insertion–Separate top/bottom pulse-width correction via current sensing (three pins on MR16/32) or programmable software bits (on all MR MCUs)Registers DescriptionThe main PWM module registers are:1.The Configuration Register (CONFIG)–Determines the alignment of the PWM signals (bit 7 — EDGE)–Selects the top and bottom PWM polarities (bits 6:5 — BOTNEG, TOPNEG)–Enables or disables the complementary fashion (bit 4 — INDEP)2.The PWM Control Register 1 (PCTL1)–Disables or re-enables the PWM pins in banks X and Y (bits 7:6 — DISX, DISY)1–Enables or disables PWM counter overflow interrupts (bit 5 — PWMINT)–Flags a PWM counter overflow (bit 4 — PWMF)–Configures the current correction bits (bits 3:2 — ISENS1, ISENS0)2–Loads prescaler, modulus, and PWM values to the working registers (bit 1 — LDOK)–Enables the PWM module (bit 0 — PWMEN)Notes:1. For for details concerning disable mapping, see the Fault Protection section of the data sheet.2. The current distortion correction feature is not covered in this application note. Refer to the Output Control section of thedata sheet.3. The number of fault pins depends on the device and package. See the Pin Assignments section of the data sheet.PWM Module3.The PWM Control Register 2 (PCTL2)–Selects the PWM CPU load frequency (bits 7:6 — LDFQ1:LDFQ0)–Selects the PWM register used for the current correction when achieved by software (bits4:2— IPOL1:IPOL3)2–Selects the prescaler for the PWM clock frequency (bits 1:0 — PRSC1:PRSC0)4.The Fault Control Register (FCR)–Enables or disables the fault interrupts of each fault input (bits 7, 5, 3, 1 — FINT4:FINT1)3–Selects the fault operating mode of each fault input (bits 6, 4, 2, 0 — FMODE4:FMODE1)35.The Fault Status Register (FSR)–Reflects the fault pin logic level (bits 7, 5, 3, 1 — FPIN4:FPIN1)3–Flags when a fault input as been asserted (bits 6, 4, 2, 0 — FFLAG4:FFLAG1)36.The Fault Acknowledge Register (FTACK)–Acknowledges the fault input flags when asserted (bits 6, 4, 2, 0 — FTACK4:FTACK1)37.The PWM Output Control Register (PWMOUT)–Selects the PWM output control, either manually or by the PWM generator (bit 6 — OUTCTL)–Determines the PWM pin logic level when configured as manual control (bits 5:0 — OUT6:OUT1)8.The PWM Counter Register (PCNTH:PCNTL)–Displays the 12-bit up/down counter (center aligned) or up-only counter (edge aligned)9.The PWM Counter Modulo Register (PMODH:PMODL)–Holds a 12-bit unsigned number that determines the maximum count for the up/down or up-only counter10.The PWM 1:6 Value Registers (PVAL1H:L, PVAL6H:L)–Holds a 16-bit signed value that determines the duty cycle of the PWM11.The Dead-Time Write-Once Register (DEADTM) which:–Holds an 8-bit value that determines the number of PWM cycles to turn off the PWM pairs when configured in complementary fashion12.The PWM Disable Mapping Write-Once Register (DISMAP)–Holds an 8-bit value that determines which PWM pins will be disabled if an external fault or software disable occurs1Notes:1. For for details concerning disable mapping, see the Fault Protection section of the data sheet.2. The current distortion correction feature is not covered in this application note. Refer to the Output Control section of thedata sheet.3. The number of fault pins depends on the device and package. See the Pin Assignments section of the data sheet.Application ExampleApplication ExampleIn this example PWM application, a three-phase AC induction motor will be driven by the microcontroller using an inverter topology. As shown in the Schematics section of this document, the PWM pins are connected to the gate driver IC. This gate driver is used to convert the MCU voltage levels to the required gate-to-source voltages of the switching transistors. The IGBTs used for this example are in the range of 10 V to 20 V typically. As a protection scheme, there is a sense resistor, where its voltage drop will represent the total current fed to the motor’s coils. An amplifier and comparator will generate a FAULT signal to protect the power stage and the motor against an overcurrent condition.as shown inApplication Example As an example, a 60-Hz signal with these shapes will be generated by the microcontroller using the PWM at a 15.625 kHz. This frequency is just above the audible noise level and low enough to avoid electrical noise generation. The number of PWM cycles to achieve a 60 Hz signal would be:15.625 kHz/60 Hz = 260.4167For convenience, a power-of-two value of 256 PWM cycles can be used. At this point, a table of 256 duty cycle values is needed to generate a 60-Hz signal with a PWM frequency of 15.625 kHz, but there is a trade-off between the number of different duty cycle values and the CPU usage. Therefore, a different PWM load frequency will be used to relieve the CPU. With a PWM load frequency of each 4 PWM cycles, a table of 256 / 4 = 64 values is to be stored in FLASH for each PWM pair and CPU use is reduced significantly.Another important parameter, known as dead-time insertion, must be considered on these applications. The dead-time value will depend on the motor coil’s characteristics, the layout, and the gate driving circuitry. For this particular example, a dead-time value of 2 microseconds is inserted between the turn off of a channel (e.g., PWM 1) and the turn on of its complementary channel (e.g., PWM 2) to prevent a short circuit condition. That value can be computed as follows:PWM module input clock (8 MHz with prescaler of 1) * 2 µs = 16.Application ExampleSchematicsCode and ExplanationThe following C code is an example using an MC68HC908MR8 microcontroller. This code configures and uses the PWM module to start and stop a three-phase AC induction motor. The software consists of the following steps:•Initialize the PWM module.•Check the input pin. If the pin is open, the motor is stopped. If the switch is closed, the motor is continuously running.•The PWM duty cycles are reloaded continuously so that the output frequency seen by the motor coils is a three-phase sinusoid 60-Hz signal on a PWM frequency of 15.625 kHz. See the flowchartin Figure4.Application ExampleFigure 4. PWM Interrupt Service Routine Flowchart1. Initialization RoutineFollowing these steps, the user will be able to use the PWM for a typical motor application.1.1Configure the PWM fashion and polarityCONFIG = 0x01; /* Center aligned mode enabled, all PWM pins in positive polarity, complementary mode enabled, COP disabled */Application Example1.2Initialize the PWM counter modulus to have a frequency of 15.625 kHzThe software initializes the PLL1to speed up the operating frequency to the maximum of 8 MHz with the external crystal of 4.00 MHz. In this step, the prescaler is also selected.PMOD = 0x0100; /* With a FOP of 8MHz, the PWM Frequency would be:Fbus 8 MHzPWM Frequency = --------------- = --------- = 15.625 kHz‘2’ x PMODH:L 2 x 256The ‘2’ factor of the divisor is because a center-alignedoperation is used, so the PWM counter counts up and down. */PCTL2 = 0x80; /* Reload PWM values every 4 PWM cycles. Select a prescaler by 1 */1.3Initialize the disable mapping registers. When a FAULT occurs, turn off every PWM output. Configure theFAULT1 pin as automatic operation without interrupts.DISMAP = 0xFF; /* Disable all PWM pins when a FAULT occurs */FCR = 0x01; /* Fault 1 in Automatic mode without interrupts */1.4Select a dead-time of 2 microseconds. This value depends on the power electronics topology, the layout andthe motor characteristics.DEADTM = 0x10; /* Deadtime of 2 us. This is dependent of the hardware topology */DEADTM = Fbus x 2 us = 8 MHz x 2 us = 16 */1.5Initialize the duty cycle registers to the minimum value of 0%. In the complementary mode, it is sufficient toload duty cycle values to the odd PWM channels.PVAL1 = 0x0000; /* Minimum duty cycle for pair PWM1:2 */PVAL3 = 0x0000; /* Minimum duty cycle for pair PWM3:4 */PVAL5 = 0x0000; /* Minimum duty cycle for pair PWM5:6 */1.6Load data to the working registers by setting the LDOK bit and enable the PWM module by setting thePWMEN bit. Enable PWM interrupts to reload duty cycle registers with new values.PCTL1 = 0x22; /* Load data to buffers by setting the LDOK bit and EnablePWM Interrupts */PCTL1 |= 0x01; /* Enable the PWM module by setting the PWMEN bit */Because an interrupt-based algorithm is being implemented, the global interrupt enable mask must be cleared as follows:EnableInterrupts; /* __asm CLI; */1. PLL module is not covered in this application note. Refer to the Clock Generator Module section of the data sheet.Considerations 2. Interrupt Service Routine (ISR)From this point on, the code execution is performed inside the PWM interrupt service routine. The ISR: 2.1Clears PWM interrupt flag.PCTL1 &= ~(0x10); /* Clear PWM Interrupt Flag */2.2Reloads the PWM value registers with the next duty cycle value stored in a constant table. The value to bestored depends on the state of the push button. If it is read as logic 0, a value from the table is stored in the PWM channels, and if it is read as logic 1, a value of 0x0000 (0% duty cycle) is stored in the channels.if ((PTA & 0x08) == 0x00) /* Check external switch connected to PTA3 */{PVAL1 = PHASE_A[TableIndex];PVAL3 = PHASE_B[TableIndex];PVAL5 = PHASE_C[TableIndex];}else{PVAL1 = 0x0000; /* Minimum Duty Cycle on PWM1:2 pair */PVAL3 = 0x0000; /* Minimum Duty Cycle on PWM1:2 pair */PVAL5 = 0x0000; /* Minimum Duty Cycle on PWM1:2 pair */}2.3Updates the TableIndex variable, which is used to point to the next value to be stored in the PWM channels. Itis restarted when a maximum value of 64 is reached.TableIndex++; /* Update Table Index */if (TableIndex == 64){TableIndex = 0; /* Reset Table Index */}2.4Sets the LDOK bit to use the new stored values.PCTL1 |= 0x02; /* Load new PWM values */ConsiderationsThis example code was developed using Metrowerks CodeWarrior IDE version 3.0 for HC08, and was expressly made for the MC68HC908MR8 in the DIP package. Changes to the code may be required to for use with other MCUs because pin availability differ for among devices. Table1 shows the available pins for each member and package option for the MC68HC08MR Series of MCU.ConclusionConclusionThis document describes how to use the PWM module to drive a three-phase AC induction motor with an MC68HC908MR8 microcontroller. For further information on how an application of this type is implemented in detail, visit the Freescale Semiconductor web site: .ReferencesRefer to the following documents for more information on subjects in this application note.•AN2876SW.zip: Complete software files for the example described in this application note •MC68HC908MR8 data sheet •MC68HC908MR32 data sheet•AN1712: Get Your Motor Running with the MC68HC708MP16•AN2154: Low-Cost, 3-Phase, AC Motor Control System with Power Factor Correction Based on MC68HC908MR32•AN2355: Sensorless BLDC Motor Control on MC68HC908MR32 Software Description •DRM007: BLDC Motor Control Board for Industrial and Appliance Applications •Freescale Semiconductor’s Motor Control Automotive Application pageTable 1. PWM Pin AvailabilityPinsPWM Pins 1–6PWM GND Pin FAULT1FAULT2FAULT3FAULT4ISENS Pins M i c r o c o n t r o l l e rM R 4/832-Pins LQFP Yes No Yes No No Yes No 28-Pins DIP/SOIC Yes No Yes No No No No M R 16/64-Pin QFP Yes Yes Yes Yes Yes Yes Yes 56-PinYesYesYesYesYesYesYes。

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Description•Surface mount inductors, 4.0mm height,designed for higher speed switch modeapplications requiring low voltage and high current •155°C maximum total operating temperature•Design utilizes high temperature powder iron material with a non-organic binder to eliminate thermal aging •Inductance offering expanded for applications requiring higher inductance.•Inductance Range from 0.175 uH to 47.3 uH •Current Range from 39.0 to 2.4 Amps •Frequency Range 1kHz to 500kHz Applications•Next generation microprocessors •High current DC-DC converters •VRM, multi-phase buck regulator •PC, Workstations, Routers•T elecom soft switches, Base Stations Environmental Data•Storage temperature range:-40°C to +155°C•Operating ambient temperature range:-40°C to +155°C (range is application specific)•Solder reflow temperature:+260°C max.for 10 seconds max.Packaging•Supplied in tape and reel packaging, 800 parts per reelPart Rated OCL (1)Irms (2)Isat (3)Isat (4)DCR (m Ω)Volts (5)Number Inductancenominal Amperes Amperes Amperes max.@µSec (VµS)µH +/-20% µH (Typ.)15% rolloff30% rolloff20°C (ref.)HC8-R15-R 0.150.17539.043760.80 1.5HC8-R39-R 0.390.39028.32645 1.55 2.5HC8-R75-R 0.750.76618.818.532.7 3.40 3.5HC8-1R2-R 1.2 1.3216.014.425.5 4.70 4.5HC8-1R9-R 1.9 1.9012.411.820.97.7 5.5HC8-2R6-R 2.6 2.6510.210.017.711.4 6.5HC8-3R5-R 3.5 3.528.508.715.316.57.5HC8-4R5-R 4.5 4.528.007.713.518.68.5HC8-5R6-R 5.6 5.65 6.70 6.912.126.39.5HC8-6R9-R 6.9 6.90 6.40 6.210.928.910.5HC8-8R2-R 8.28.27 5.50 5.710.039.611.5HC8-100-R 10.09.77 5.20 5.29.243.612.5HC8-150-R 15.015.02 4.10 4.27.468.615.5HC8-220-R 22.021.40 3.40 3.5 6.299.518.6HC8-330-R 33.031.65 2.70 2.9 5.115422.6HC8-470-R47.047.282.202.4 4.223727.61) T est Parameters:100KHz, 1.0Vrms2) Irms Amperes for approximately ∆T of 40°C above 85°C ambient 3) Isat Amperes Peak for approximately 15% rolloff (@20°C)4) Isat Amperes Peak for approximately 30% rolloff (@20°C)5) Applied Volt-Time product (V-µS) across the inductor.This value represents the applied V-µS at operating frequency necessary to generate additional core loss which contributes to the 40°C temperature rise.De-rating of the Irms is required to prevent excessive temperature rise.The 100% V-uS rating is equivalent to a ripple current Ip-p of 20% of Isat (30% rolloff option).It is recommended that the temperature of the part not exceed 155°C under worst case operating conditions verified in the end application.Part number definition:HC8-XXX-RHC8 = Product code and size XXX = Inductance value in uH.R =Decimal point.If no R is present, third character = #of zeros -R suffix indicates RoHS compliantHIGH CURRENT 8Power InductorsMechanical DiagramsTOP VIEWFRONT VIEWSIDE VIEW0.55RECOMMENDED PCB PAD LAYOUT12SCHEMATIC4.0MaxC LA ref3.952plcs refA mm 1R 2.11R9thru 4702.7R39R75R15PN2.12.12.1 FRONT VIEWTABLE wwllyy = Date code R = Revision level xxx = Inductance valueRoHS 2002/95/ECHIGH CURRENT 8Power InductorsUser direction of feedDimensions in MillimetersIrms DERATING WITH CORE LOSS84868890929496981001030507090110130150170190%Applied Volt-u Seconds%o f I r m s s p e c i f i e d f r o m z e r o r i p p l e a p p l i c a t i o nOCL vs Isat01002304050607080901000102030405060708090100110120130140150160170180190200%of Isat%o f O C LInductance CharacteristicsCore LossVisit us on the Web at 1225 Broken Sound Pkwy.Suite F Boca Raton, FL 33487T el:+1-561-998-4100 T oll Free:+1-888-414-2645 Fax:+1-561-241-6640This bulletin is intended to present product design solutions and technical information that will help the end user with design applications. Cooper Electronic Technologies reserves the right, without notice, to change design or construction of any products and to discontinue or limit distribution of any products. Cooper Electronic Technologies also reserves the right to change or update, without notice, any technical information contained in this bulletin. Once a product has been selected, it should be tested by the user in all possible applications.Life Support Policy: Cooper Electronic Technologies does not authorize the use of any of its products for use in life support devices or systems without the express written approval of an officer of the Company.Life support systems are devices which support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.PM-4120 3/07©Cooper Electronic T echnologies 2007。