YD2025资料.pdf
图集规范总目录
90T911（二）R型离心热水泵基础及安装.pdf 90T911（一）IS型离心水泵基础及安装.pdf 91D401-2 吊车裸滑触线安装.pdf 92（03）G410—1～3: 92S214-2: 92S214钢筋混凝土化粪池.rar 92S214钢筋混凝土化粪池: 93（03）G320: 93（03）G321: 93T921-1汽-水换热器.pdf 94D101-5 35kV及以下电缆敷设.pdf 94D164 35KV及以下电缆敷设.PDF 94T903集气罐制作及安装.pdf 95（03）G314: 95（03）G323: 95（03）G325: 95（03）G337: 95（03）G415—6～10: 95（03）G426: 95（03）G439: 95S124自控恒温装置: 95S516排水管道基础及接口: 96（03）G353—1～6: 96（03）SG612: 96（03）SG613—1～2: 96D702-2 常用灯具安装.pdf 96S406: 97（03）G329—3～6: 97（03）G361: 97R412室外热力管道支座.pdf 97S501-1: 98（03）SG372: 98ZJ 中南标2002版 共390页.pdf 99（03）ZG408: 99D303-2 常用风机控制电路图.pdf 99D501-1 建筑物防雷设施安装.pdf 99S202: 99S202室内消火栓安装: 99S304 P1-P129卫生设备安装: 99S304: 99S304卫生设备安装: 99X601 住宅智能化电气设计施工图集.pdf A-4电图.dwg A-4放线图.dwg A-4立面（勋）.dwg A-4平面，天花布置图(2.dwg A-4平面，天花布置图(3).dwg A-4新平面.dwg A-4新新新平面.dwg A-5电图.dwg
RDD050N20资料
Transistors1/510V Drive Nch MOSFETRDD050N20z StructureSilicon N-channel MOSFETz Features1) Low on-resistance. 2) Low input capacitance.3) Exellent resistance to damage from static electricity .z Application Switching z Dimensions (Unit : mm)z Packaging specificationsz Absolute maximum ratings (T a=25°C)∗1∗2∗2ParameterV V DSS Symbol 200V V GSS ±30A I D±5A I DP ±20A mJ I AS 20755W E AS 150°C °CP D T ch T stg−55 to +150Limits Unit Drain-Source Voltage Gate-Source Voltage Drain Current Total Power Dissipation (T C =25°C)Channel Temperature Avalanche Current Avalanche EnergyStorage TemperatureContinuous Pulsed ∗1A A I S5I SP 20Source Current (Body Diode)Continuous Pulsed∗1 Pw ≤ 10µs, Duty cycle ≤ 1%∗2 L 4.5mH, V DD =50V, R G =25Ω, 1Pulse, Tch =25°Cz Equivalent Circuitthe source terminals to protect the diode against static electricity when the product is in use. Use the protection circuit when the fixed voltages are exceeded.z Thermal resistanceParameter°C/WRth(ch-c)Symbol Limits Unit Channel to case6.25Transistors2/5z Electrical characteristics (T a=25°C)z Body diode characteristics (Source-drain) (T a=25°C)V SD −− 1.5V I S = 5.0A, V GS =0V Forward voltaget rr −117−ns I DR = 5.0A, V GS =0V di/dt= 100A / µsReverse recovery time Q rr−0.37−µC Reverse recovery charge∗ PulsedParameterSymbol Min.Typ.Max.Unit Conditions∗Transistors3/5z Electrical characteristic curves 0.010.1110100D R A I N C U R RE N T :I D (A )DRAIN-SOURCE VOLTAGE : I D (A)Fig.1 Maximum Safe Operating AreaDRAIN-SOURCE VOLTAGE : V DS (V)Fig.2 Typical Output CharacteristicsD R A I N C U R RE N T : I D (A )GATE-SOURCE VOLTAGE : V GS (V)D R A I N C U R RE N T : I D (A )Fig.3 Typical TransferCharacteristicsCHANNEL TEMPERATURE : T ch (°C)G A T E T H R E S H O L D V O L T A G E : V G S (t h ) (V )Fig.4 Gate Threshold Voltagevs. Channel TemperatureDRAIN CURRENT : I D (A)S T A T I C D R A I N -S O U R C E O N -S T A T E R E S I S T A N C E : R D S (o n ) (Ω)Fig.5 Static Drain-SourceOn-State Resistance vs. Drain CurrentGATE-SOURCE VOLTAGE : V GS (V)Fig.6 Static Drain-SourceOn-State Resistance vs.Gate-Source VoltageS T A T I C D R A I N -S O U R C E O N -S T A T E R E S I S T A N C E : R D S (o n ) (Ω)CHANNEL TEMPERATURE : T ch (°C)Fig.7 Static Drain-SourceOn-State Resistance vs.Channel TemperatureS T A T I C D R A I N -S O U R C E O N -S T A T E R E S I S T A N C E : R D S (o n ) (Ω)DRAIN CURRENT : I D (A)F O R W A R D T R A N S F E R A D M I T T A N C E :⏐Y f s ⏐(S )Fig.8 Forward Transfer Admittancevs. Drain CurrentSOURCE-DRAIN VOLTAGE : V SD (V)R E V E R S E D R A I N C U R R E N T : I D R (A )Fig.9 Reverse Drain Current vs.Source-Drain VoltageTransistors4/5DRAIN SOURCE VOLTAGE : V DS (V)C A P A C I T A N C E : C (p F )Fig.10 Typical Capacitance vs.Drain-Source VoltageTOTAL GATE CHARGE : Q g (nC)Fig.11 Dynamic Input CharacteristicsD R A I N -S O U R CE V O L T A G E : I D S (V )G A T E -S O U R C E V O L T A G E : V G S (V )REVERSE DRAIN CURRENT : I DR (A)R E V E R S E R E C O V E R Y T I M E: t r r (n s )Fig.12 Reverse Recovery Timevs. Reverse Drain CurrentDRAIN CURRENT : I D (A)S W I T C H I N G T I M E : t (n s )Fig.13 Switching CharacteristcsTransistors5/5zSwitching characteristics measurement circuitFig.1-1 Switching time measurement circuit Fig.1-2 Switching waveformsFig.2-1 Gate charge measurement circuit Fig.2-2 Gate charge waveformFig.3-1 Avalanche measurement circuit Fig.3-2 Avalanche waveformAppendix1-Rev2.0Thank you for your accessing to ROHM product informations.More detail product informations and catalogs are available, please contact your nearest sales office.ROHM Customer Support SystemTHE AMERICAS / EUPOPE / ASIA / JAPANContact us : webmaster@rohm.co.jpAppendix。
M2S28D20ATP-75资料
128M Double Data Rate Synchronous DRAMPRELIMINARYSome of contents are subject to change without notice.DESCRIPTIONM2S28D20ATP is a 4-bank x 8388608-word x 4-bit,M2S28D30ATP is a 4-bank x 4194304-word x 8-bit,M2S28D40ATP is a 4-bank x 2097152-word x 16-bit,double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals arereferenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves veryhigh speed data rate up to 133MHz, and are suitable for main memory in computer systems. FEATURES- Vdd=Vddq=2.5V+0.2V- Double data rate architecture;two data transfers per clock cycle- Bidirectional, data strobe (DQS) is transmitted/received with data- Differential clock inputs (CLK and /CLK)- DLL aligns DQ and DQS transitionswith CLK transitions edges of DQS- Commands entered on each positive CLK edge;- data and data mask referenced to both edges of DQS- 4 bank operation controlled by BA0, BA1 (Bank Address)- /CAS latency- 2.0/2.5 (programmable)- Burst length- 2/4/8 (programmable)- Burst type- sequential / interleave (programmable)- Auto precharge / All bank precharge controlled by A10- 4096 refresh cycles /64ms (4 banks concurrent refresh)- Auto refresh and Self refresh- Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)- SSTL_2 Interface- 400-mil, 66-pin Thin Small Outline Package (TSOP II)- FET switch control(/QFC) for x4/ x8- JEDEC standard128M Double Data Rate Synchronous DRAMCLK,/CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQ0-7: Data I/O DQS : Data Strobe DM : Write Mask /QFC : FET Switch Control for x4/x8Vref : Reference Voltage123456789101112131415161718192021222324252627282930313233666564636261605958575655545352515049484746454443424140393837363534VDD DQ0VDDQ DQ1DQ2VSSQ DQ3DQ4VDDQ DQ5DQ6VSSQ DQ7NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0BA1A10/APA0A1A2A3VDDVSS DQ15VSSQ DQ14DQ13VDDQ DQ12DQ11VSSQ DQ10DQ9VDDQ DQ8NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC NC A11A9A8A7A6A5A4VSS66pin TSOP(II)400mil widthx875mil length 0.65mm Lead PitchROW A0-11ColumnA0-9,11(x4)A0-9 (x8)A0-8 (x16)VDD DQ0VDDQNC DQ1VSSQNC DQ2VDDQNC DQ3VSSQ NC NC VDDQNC NC VDD NU,/QFCNC /WE /CAS /RAS /CS NC BA0BA1A10/APA0A1A2A3VDDVSS DQ7VSSQ NC DQ6VDDQ NC DQ5VSSQ NC DQ4VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11A9A8A7A6A5A4VSSA0-11: Address InputBA0,1: Bank Address Input Vdd : Power SupplyVddQ : Power Supply for Output Vss : GroundVssQ : Ground for OutputVSS NC VSSQ NC DQ3VDDQ NC NC VSSQ NC DQ2VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11A9A8A7A6A5A4VSSVDD NC VDDQ NC DQ0VSSQ NC NC VDDQ NC DQ1VSSQ NC NC VDDQ NC NC VDD NU,/QFCNC /WE /CAS /RAS /CS NC BA0BA1A10/APA0A1A2A3VDDPIN CONFIGURATION(TOP VIEW)x8 x16x4128M Double Data Rate Synchronous DRAMType Designation CodeThis rule is applied to only Synchronous DRAM family.Mitsubishi Main DesignationSpeed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0 75: 133MHz@CL=2.5,100MHz@CL=2.0Package Type TP: TSOP(II)Process GenerationFunction Reserved for Future Use Organization 2n 2: x4, 3: x8, 4: x16DDR Synchronous DRAM Density 28: 128M bitsInterface V:LVTTL, S:SSTL_3, _2Memory Style (DRAM) M 2 S 28 D 3 0 A TP -75BLOCK DIAGRAM/CS /RAS /CAS /WEUDM,LDMMemoryArray Bank #0DQ0 - 15I/O Buffer Memory Array Bank #1Memory Array Bank #2Memory Array Bank #3Mode RegisterControl CircuitryAddress BufferA0-11BA0,1Clock BufferCLK, /CLK CKEControl Signal Buffer/QFC for x4/x8QFC&QS BufferUDQS,LDQSDLL128M Double Data Rate Synchronous DRAMPIN FUNCTIONCLK, /CLK InputClock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing).CKE InputClock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomesasynchronous input. Self refresh is maintained as long as CKE is low./CS Input Chip Select: When /CS is high, any command means No Operation./RAS, /CAS, /WEInputCombination of /RAS, /CAS, /WE defines basic commands.A0-11InputA0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address isspecified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged.BA0,1InputDQ0-15(x16),DQ0-7(x8),DQ0-3(x4),Input / OutputDQSVdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry.VddQ, VssQPower SupplyVddQ and VssQ are supplied to the Output Buffers only.Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.Data Input/Output: Data busData Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15SYMBOLTYPEDESCRIPTION/QFC OutputFET Control: Optional. Output during every Read and Write access. Can be used to control isolation switches on modules. Open drain output.DMInputInput Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15.Input / OutputVrefInputSSTL_2 reference voltage.128M Double Data Rate Synchronous DRAMBASIC FUNCTIONSThe M2S28D20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table./CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE CommandCKE Refresh Option @refresh commandA10Precharge Option @precharge or read/write commandCLK define basic commands/CLK Activate (ACT) [/RAS =L, /CAS =/WE =H]ACT command activates a row in an idle bank indicated by BA.Read (READ) [/RAS =H, /CAS =L, /WE =H]READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA)Write (WRITE) [/RAS =H, /CAS =/WE =L]WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.128M Double Data Rate Synchronous DRAMCOMMAND TRUTH TABLEH=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number COMMAND MNEMONIC CKE n-1CKE n /CS /RAS /CAS /WE BA0,1A10/AP A0-9,11Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Address Entry &Bank Activate ACT H H L L H H V V V Single Bank Precharge PRE H H L L H L V L X Precharge All Banks PREA H H L L H L H X Column Address Entry& Write WRITEHHLHLLVLVColumn Address Entry& Write with Auto-Precharge WRITEA H H L H L L V H VColumn Address Entry& Read READ H H L H L H V L VColumn Address Entry& Read with Auto-PrechargeREADA H H L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TERM H H L H H L X X X Mode RegisterSetMRSHHLLLLLLVX note 1NOTE:1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts.BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0=1 ,BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the 22.op-code to be written to the selected Mode Register.128M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLECurrent State/CS/RAS/CAS/WE Address Command Action Notes IDLE H X X X X DESEL NOPL H H H X NOP NOPL H H L BA TERM ILLEGAL2L H L X BA, CA, A10READ / WRITE ILLEGAL2L L H H BA, RA ACT Bank Active, Latch RAL L H L BA, A10PRE / PREA NOP4L L L H X REFA Auto-Refresh5L L L L Op-Code, Mode-AddMRS Mode Register Set5ROW ACTIVE H X X X X DESEL NOP L H H H X NOP NOPL H H L BA TERM NOPL H L H BA, CA, A10READ / READA Begin Read, Latch CA, Determine Auto-PrechargeL H L L BA, CA, A10WRITE / WRITEA Begin Write, Latch CA, Determine Auto-PrechargeL L H H BA, RA ACT Bank Active / ILLEGAL2 L L H L BA, A10PRE / PREA Precharge / Precharge AllL L L H X REFA ILLEGALL L L L Op-Code, Mode-AddMRS ILLEGALH X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TERM Terminate BurstL H L H BA, CA, A10READ / READA Terminate Burst, Latch CA, BeginNew Read, Determine Auto-Precharge3L H L L BA, CA, A10WRITE / WRITEA ILLEGALL L H H BA, RA ACT Bank Active / ILLEGAL2 L L H L BA, A10PRE / PREA Terminate Burst, PrechargeL L L H X REFA ILLEGALL L L L Op-Code, Mode-AddMRS ILLEGALREAD(Auto-Precharge Disabled)128M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE (continued)Current State/CS/RAS/CAS/WE Address Command Action NotesH X X X X DESEL NOP (Continue Burst to END)L H H H X NOP NOP (Continue Burst to END)L H H L BA TERM ILLEGALL H L H BA, CA, A10READ / READA Terminate Burst, Latch CA, BeginRead, Determine Auto-Precharge3L H L L BA, CA, A10WRITE / WRITEA Terminate Burst, Latch CA, BeginWrite, Determine Auto-Precharge3L L H H BA, RA ACT Bank Active / ILLEGAL2 L L H L BA, A10PRE / PREA Terminate Burst, PrechargeL L L H X REFA ILLEGALL L L L Op-Code, Mode-AddMRS ILLEGALH X X X X DESEL NOP (Continue Burst to END)L H H H X NOP NOP (Continue Burst to END)L H H L BA TERM ILLEGALL H L H BA, CA, A10READ / READA ILLEGALL H L L BA, CA, A10WRITE / WRITEA ILLEGALL L H H BA, RA ACT Bank Active / ILLEGAL2 L L H L BA, A10PRE / PREA Precharge / ILLEGAL2 L L L H X REFA ILLEGALL L L L Op-Code, Mode-AddMRS ILLEGALH X X X X DESEL NOP (Continue Burst to END)L H H H X NOP NOP (Continue Burst to END)L H H L BA TERM ILLEGALL H L H BA, CA, A10READ / READA ILLEGALL H L L BA, CA, A10WRITE / WRITEA ILLEGALL L H H BA, RA ACT Bank Active / ILLEGAL2 L L H L BA, A10PRE / PREA Precharge / ILLEGAL2 L L L H X REFA ILLEGALL L L L Op-Code, Mode-AddMRS ILLEGALWRITE(Auto-PrechargeDisabled) READ with Auto-Precharge WRITE with Auto-Precharge128M Double Data Rate Synchronous DRAMFUNCTION TRUTH TABLE (continued)Current State /CS /RAS /CAS /WE Address Command ActionNotesH X X X X DESEL NOP (Idle after tRP)L H H H X NOP NOP (Idle after tRP)L H H L BA TERMILLEGAL 2L H L X BA, CA, A10READ / WRITE ILLEGAL 2L L H H BA, RA ACTILLEGAL2L L H L BA, A10PRE / PREA NOP (Idle after tRP)4L L L H XREFA ILLEGAL L L L LOp-Code, Mode-AddMRSILLEGALH X X X XDESEL NOP (Row Active after tRCD)L H H H XNOP NOP (Row Active after tRCD)L H H L BA TERMILLEGAL 2L H L X BA, CA, A10READ / WRITE ILLEGAL 2L L H H BA, RA ACTILLEGAL 2L L H L BA, A10PRE / PREA ILLEGAL 2L L L H XREFA ILLEGAL L L L LOp-Code, Mode-AddMRSILLEGAL H X X X XDESEL NOP L H H H XNOP NOP L H H L BA TERMILLEGAL 2L H L X BA, CA, A10READ / WRITE ILLEGAL 2L L H H BA, RA ACTILLEGAL 2L L H L BA, A10PRE / PREA ILLEGAL 2L L L H XREFA ILLEGAL L L L LOp-Code, Mode-Add MRSILLEGALROWACTIVATINGWRITE RE-COVERINGPRE-CHARGING128M Double Data Rate Synchronous DRAMFUNCTION TRUTH TABLE (continued)ABBREVIATIONS:H=High Level, L=Low Level, X=Don't CareBA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OperationNOTES:1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.3. Must satisfy bus contention, bus turn around, write recovery requirements.4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.5. ILLEGAL if any bank is not idle.ILLEGAL = Device operation and/or data-integrity are not guaranteed.Current State /CS /RAS /CAS /WE Address Command ActionNotesREFRESHING H X X X XDESEL NOP (Idle after tRC)LH H H X NOP NOP (Idle after tRC)L H H L BATERMILLEGAL L H L X BA, CA, A10READ / WRITE ILLEGAL L L H H BA, RA ACTILLEGAL L L H L BA, A10PRE / PREA ILLEGAL L L L H XREFA ILLEGAL LL L L Op-Code, Mode-Add MRSILLEGALH X X X X DESEL NOP (Row Active after tRSC)L H H H X NOP NOP (Row Active after tRSC)L H H L BATERMILLEGAL L H L X BA, CA, A10READ / WRITE ILLEGAL L L H H BA, RA ACTILLEGAL L L H L BA, A10PRE / PREA ILLEGAL L L L H XREFA ILLEGAL LLLLOp-Code, Mode-AddMRSILLEGALMODE REGISTER SETTING128M Double Data Rate Synchronous DRAMFUNCTION TRUTH TABLE for CKEABBREVIATIONS:H=High Level, L=Low Level, X=Don't Care NOTES:1. CKE Low to High transition will re-enable CLK and other inputs asynchronously..A minimum setup time must be satisfied before any command other than EXIT.2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.3. Must be legal command.Current State CKE n-1CKE n /CS /RAS /CAS /WE AddressActionNotes H X X X X X X INVALID1L H H X X X X Exit Self-Refresh (Idle after tRC)1L H L H H H X Exit Self-Refresh (Idle after tRC)1L H L H H L X ILLEGAL 1L H L H L X X ILLEGAL 1L H L L X X X ILLEGAL1LL X X X X X NOP (Maintain Self-Refresh)1H X X X X X X INVALIDL H X X X X XExit Power Down to IdleLL X X X X X NOP (MaintainSelf-Refresh)H H X X X X X Refer to Function Truth Table 2H L L L L H X Enter Self-Refresh 2H L H X X X X Enter PowerDown 2H L L H H H X Enter Power Down 2H L L H H L XILLEGAL2H L L H L X X ILLEGAL 2H L L L X X X ILLEGAL2L X X X X X X Refer to Current State =Power Down 2HH X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle 3L H X X X X X Exit CLK Suspend at Next Cycle 3LLXXXXXMaintain CLKSuspendANY STATE other than listedaboveSELF-REFRESHINGPOWER DOWNALL BANKSIDLE128M Double Data Rate Synchronous DRAMSIMPLIFIED STATE DIAGRAMROW ACTIVEIDLEPRE CHARGEPOWER DOWNREADREADAWRITE WRITEAPOWER ONACT REFAREFSREFSX CKELCKEHMRSCKELCKEHWRITEREADWRITEAWRITEAREADAREADPREREADA READAPREPREPREAPOWER APPLIEDMODE REGISTERSETSELF REFRESHAUTO REFRESHActive Power DownAutomatic Sequence Command SequenceWRITEREADPRE CHARGE ALLMRSBURST STOPTERM128M Double Data Rate Synchronous DRAMPOWER ON SEQUENCEBefore starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or multifunctioning.1. Apply VDD before or the same time as VDDQ2. Apply VDDQ before or at the same time as VTT & Vref3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL4. Issue precharge command for all banks of the device5. Issue EMRS6. Issue MRS for the Mode Register and to reset the DLL7. Issue 2 or more Auto Refresh commands8. Maintain stable condition for 200 cycleAfter these sequence, the DDR SDRAM is idle state and ready for normal operation.MODE REGISTERBurst Length, Burst Type and /CAS Latency can beprogrammed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the DDR SDRAM is ready for new command./CS /RAS /CAS /WE A11-A0/CLK VCLK BA0BA1R: Reserved for Future Use0NO 1YESDLL Reset0Sequential 1InterleavedBurst TypeBT=0BT=1000R R 001220104401188100R R 101R R 110R R 111R RBL Burst Length/CAS Latency000R 001R 0102011R 100R 101R 110 2.5111R CL Latency ModeBA1BA0A11A10A9A8A7A6A5A4A3A2A1A00DRBTLTMODEBL128M Double Data Rate Synchronous DRAMEXTENDED MODE REGISTERDLL disable / enable mode can be programmed by setting the extendedmode register (EMRS). The extended mode register stores these datauntil the next EMRS command, which may be issued when all banks arein idle state. After tRSC from a EMRS command, the DDR SDRAM is ready for new command./CS /RAS /CAS/WE A11-A0VBA0BA1/CLK CLK BA1BA0A11A10A9A8A7A6A5A4A3A2A1A00QFC DSDD0Disable 1EnableQFC0Normal 1WeakDrive Strength 0DLL Enable 1DLL Disable DLL Disable128M Double Data Rate Synchronous DRAM/CAS LatencyBurst LengthCL= 2BL= 4Burst LengthA2A1A0Initial Address BLSequentialInterleavedColumn Addressing000001010011100101110111-00-01-10-11--001234567012345671234567010325476234567012301674534567012321076544567012345670123567012345476103267012345674523017012012312302301300176540123103223013201--1121345632111842Command Address DQ YYRead Write DQS Q0Q1Q2Q3D0D1D2D3/CLK CLK128M Double Data Rate Synchronous DRAMABSOLUTE MAXIMUM RATINGSDC OPERATING CONDITIONS(Ta=0 ~ 70o C, unless otherwise noted)CAPACITANCE(Ta=0 ~ 70o C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, unless otherwise noted)Min.Max.CI(A)Input Capacitance, address pin 2.0 3.0pF 11CI(C)Input Capacitance, control pin VI=1.25v 2.0 3.0pF 11CI(K)Input Capacitance, CLK pin f=100MHz 2.0 3.00.25pF 11CI/O I/O Capacitance, I/O, DQS, DM pinVI=25mVrms4.05.0pF 11CO(QF)Output Capacitance, /QFC2.03.0pF 11NotesLimits Symbol ParameterTest ConditionUnit DeltaCap.(Max.)0.500.50M in.T yp.M a x.V dd Supply V olta ge 2.3 2.5 2.7V V ddQ Supply V olta ge for O utput 2.3 2.5 2.7V V re f Input R e fe re nc e V oltage 0.49*V ddQ 0.50*V ddQ0.51*V ddQ V 5V IH (D C )H igh-L e ve l Input V olta ge V re f + 0.18V ddQ +0.3V V IL (D C )L ow -L e ve l Input V olta ge -0.3V re f - 0.18V V IN (D C )Input V olta ge L e ve l, C L K a nd /C L K -0.3V ddQ + 0.3V V ID (D C )Input D iffe re ntia l V olta ge , C L K a nd /C L K 0.36V ddQ + 0.6V 7V T T I/O T e rm ina tion V olta geV re f - 0.04V re f + 0.04V6N ote s L im its Sym bol P a ra m e te rU nit Symbol Parameter Conditions Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 3.7V VddQ Supply Voltage for Outputwith respect to VssQ -0.5 ~ 3.7V VI Input Voltage with respect to Vss -0.5 ~ Vdd+0.5V VO Output Voltage with respect to VssQ-0.5 ~ VddQ+0.5V IO Output Current 50mA Pd Power Dissipation Ta = 25 oC1000mWTopr Operating Temperature 0 ~ 70o C TstgStorage Temperature-65 ~ 150oC128M Double Data Rate Synchronous DRAM-75-10x410595x8110105x16120115x4110100x8115110x16135130x46055x86560x167570x4150140x8170160x16210200x4145135x8165155x16200180 IDD5AUTO REFRESH CURRENT: t RC = t RFC (MIN) x4/x8/x16190180 IDD6SELF REFRESH CURRENT: CKE < 0.2Vx4/x8/x16339x4/x8/x164040Limits(Max.)mASymbolOrganizationParameter/Test ConditionsIDD4R OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank active;Address and control inputs changing once per clock cycle;CL=2.5; t CK = t CKMIN; IOUT = 0 mA PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; CKE <VIL (MAX); t CK = t CK MINx4/x8/x16IDD2PIDD2N IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changingonce per clock cycle IDD4W OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;Address and control inputs changing once per clock cycle; CL=2.5; t CK = t CKMIN;DQ, DM and DQS inputs changing twice per clock cycle IDD3PACTIVE POWER-DOWN STANDBY CURRENT: One bank active; power-down mode; CKE < VIL (MAX); t CK = t CK MINACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM andDQS inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD3Nx4/x8/x16OPERATING CURRENT: One Bank; Active-Precharge; t RC = t RC MIN; t CK= t CK MIN; DQ, DM and DQS inputs changing twice per clock cycle; addressand control inputs changing once per clock cycle IDD0 IDD1OPERATING CURRENT: One Bank; Active-Read-Precharge;Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0mA;Address and control inputs changing once per clock cycle 4040UnitNotes2020AVERAGE SUPPLY CURRENT from Vdd(Ta=0 ~ 70o C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)AC OPERATING CONDITIONS AND CHARACTERISTICS(Ta=0 ~ 70o C, Vdd = VddQ = 2.5V + 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)M in.M ax.V IH (A C )H igh-Level Input V oltage (A C )V ref + 0.35V IL(A C )Lo w -Level Input V oltage (A C )V ref - 0.35V ID (A C )Input D ifferential V oltage, C LK and /C LK 0.7V ddQ + 0.67V IX (A C )Input C ro ssing P oint V oltage, C LK and /C LK 0.5*V d dQ - 0.20.5*V d dQ + 0.28IO Z O ff-state O utp ut C urrent /Q floating V o=0~V d dQ -55µA II Input C urrent / V IN =0 ~ V dd Q -22µA IO H O utput H igh C urrent (V O U T = 1.95 V )-16.8IO LO utput H igh C urrent (V O U T = 0.35 V )16.8mA mAN otesLimitsS ymb ol P arameter / Test C ond itio nsU nit V V V V128M Double Data Rate Synchronous DRAMAC TIMING REQUIREMENTS(Ta=0 ~ 70o C, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)Min.Max Min.Max tAC DQ Output Valid data delay time from CLK//CLK -0.750.75-0.80.8ns tDQSCK DQ Output Valid data delay time from CLK//CLK-0.750.75-0.80.8ns tCH CLK High level width 0.450.550.450.55ns tCL CLK Low level width 0.450.550.450.55ns 7.515815ns 10151015ns tDH Input Setup time (DQ,DM)0.50.6ns tDS Input Hold time(DQ,DM)0.50.6ns tDIPW DQ and DM input pulse width (for each input) 1.752ns tHZ Data-out-high impedance time from CLK//CLK -0.750.75-0.80.8ns 14tLZData-out-low impedance time from CLK//CLK-0.750.75-0.80.8ns 14tDQSQ DQ Valid data delay time from DQS -0.50.5-0.60.6ns tHP Clock half period tCLmin or tCHmin tCLmin or tCHmin ns tQH Output DQS valid windowtHP-0.75tHP-1.0ns tDQSSWrite command to first DQS latching transition0.75 1.250.75 1.25tCK tDQSH DQS input High level width 0.350.35tCK tDQSL DQS input Low level width 0.350.35tCK tDSS DQS falling edge to CLK setup time 0.20.2tCK tDSH DQS falling edge hold time from CLK 0.20.2tCK tMRDMode Register Set command cycle time1515ns tWPRES Write preamble setup time 00ns 16tWPST Write postamble 0.40.60.40.6tCK 15tWPRE Write preamble 0.250.25tCK tIS Input Setup time (address and control)0.9 1.2ns 19tIH Input Hold time (address and control)0.9 1.2ns 19tRPST Read postamble 0.40.60.40.6tCK tRPRE Read preamble0.9 1.10.9 1.1tCK tQPST /QFC postamble during reads0.40.60.40.6tCK tQPRE /QFC preamble during reads0.9 1.10.91.1tCK tQCK /QFC output access time from CLK//CLK, for write 44ns tQOH/QFC output hold time for writes1.2521.252ns-10Unit NotestCK CLK cycle timeSymbol AC Characteristics Parameter-75128M Double Data Rate Synchronous DRAMAC TIMING REQUIREMENTS(Continues)(Ta=0 ~ 70o C, Vdd = VddQ = 2.5V +0.2V, Vss = VssQ = 0V, unless otherwise noted)Min.Max Min.Max tRAS Row Active time 45120,00050120,000ns tRC Row Cycle time(operation)6570ns tRFC Auto Ref. to Active/Auto Ref. command period 7580ns tRCD Row to Column Delay 2020ns tRP Row Precharge time 2020ns tRRD Act to Act Delay time 1515ns tWR Write Recovery time1515ns tDAL Auto Precharge write recovery + precharge time 3535ns tWTRInternal Write to Read Command Delay11tCK tXSNR Exit Self Ref. to non-Read command 7580ns tXSRD Exit Self Ref. to -Read command 200200tCK tXPNR Exit Power down to command 11tCK tXPRD Exit Power down to -Read command 11tCK 18tREFIAverage Periodic Refresh interval15.615.6µs17-10Unit NotesSymbol AC Characteristics Parameter-75Output Load ConditionDQOutput Timing Measurement Reference PointV REFV REFDQSV OUTV REF30pF50ΩV TT =V REFZo=50Ω128M Double Data Rate Synchronous DRAM Notes1. All voltages referenced to Vss.2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for thespecified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in therange between VIL(AC) and VIH(AC).4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does notring back above (below) the DC input LOW (HIGH) level.5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +2% of the DC value.6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to beset equal to VREF, and must track variations in the DC level of VREF.7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC levelof the same.9. Enables on-chip refresh and address counters.10. IDD specifications are tested after the device is properly initialized.11. This parameter is sampled. VddQ = 2.5V+0.2V, Vdd = 2.5V + 0.2V , f = 100 MHz, Ta = 25o C, VOUT(DC) =VddQ/2, VOUT(PEAK TO PEAK) = 25mV. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level).12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input reference level for signals other than CLK//CLK, is VREF.13. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,CKE< 0.3VddQ is recognized as LOW.14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or beforethis CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,depending on tDQSS.17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.19. For command/address and CK & /CK slew rate > 1.0V/ns.。
火力发电厂热力设备和管道保温材料技术条件与检验方法
火力发电厂热力设备和管道保温材料技术条件与检验方法SDJ 68—85中华人民共和国水利电力部关于颁发《火力发电厂热力设备和管道保温材料技术条件与检验方法》SDJ 68—85的通知(85)水电基字第10号为适应电力建设施工技术的发展，我部委托电力建设研究所对1981年编制的《火力发电厂热力设备和管道保温材料技术条件与检验方法》进行了修订，修订后名称不变，编号为SDJ 68—85，仍配合《电力建设施工及验收技术规范(锅炉机组篇)》第九章使用，现颁发执行。
希各单位在执行过程中注意总结经验，若发现问题，请随时告电力建设研究所。
一九八五年十月第一章总则第1.0.1条本技术条件与检验方法是为统一火力发电厂热力设备和管道保温材料的技术条件与检验方法而编制的，是《电力建设施工及验收技术规范(锅炉机组篇)》关于保温材料方面的补充规定。
第1.0.2条本技术条件与检验方法对火力发电厂使用的保温材料统一分类如下： 1.硬质材料制品它是指一般的固体材料(包括掺有少量纤维材料)加工成型的制品，如板、半圆瓦、弧形块、砖等。
2.矿纤材料制品它是指采用有弹性的矿质纤维材料加工成型的制品。
它又分为两大类：(1)矿纤硬质制品：用树脂粘结的板、管套、弧形块、毡、垫及缝合垫等。
(2)矿纤软质制品：无树脂粘结的毡、垫、缝合垫等。
3.松散材料它是指粒状及纤维状材料，如膨胀蛭石、膨胀珍珠岩、矿渣棉、玻璃棉、石棉纤维及硅酸铝耐火纤维等。
注：(1)毡是指厚度小于或等于50mm的制品。
(2)垫是指厚度大于50mm的制品。
(3)缝合垫是指用镀锌铁丝网单面、双面缝合，或用玻璃丝布贴面缝合成型的制品。
第1.0.3条未经鉴定的新型保温材料，本技术条件与检验方法中未作规定，可参照有关规定办理。
第1.0.4条用水泥作凝结剂时，应采用不低于525号硅酸盐水泥。
若采用其他水泥时，应按本技术条件进行试验鉴定。
第二章保温材料技术条件第一节膨胀蛭石及其制品第2.1.1条膨胀蛭石的技术条件见表2.1.1。
广东电网公司220～500kV元件保护验收规范资料
目次前言 (II)1 适用范围 (1)2 引用标准 (1)3现场验收前应具备的条件 (1)4 验收要求 (2)5 500kV变压器保护现场验收内容 (2)6 50kV母差保护现场验收内容 (5)7 220kV变压器保护现场验收内容 (6)8 220kV母差及失灵保护现场验收内容 (11)9 220kV母联（分段）保护现场验收内容 (14)附录 A 500kV变压器保护验收文档（规范性附录） (17)附录B 500kV母差保护验收文档（规范性附录） (41)附录 C 220kV变压器保护验收文档（规范性附录） (52)附录 D 220kV母差及失灵保护验收文档（规范性附录） (71)附录 E 220kV母联（分段）保护验收文档（规范性附录） (86)Ⅰ前言为了加强广东电网公司220～500kV元件保护验收工作，规范继电保护设备及二次回路现场验收，保证220～500kV元件保护验收质量，确保新投入运行的继电保护设备及二次回路符合广东电网公司相关技术规范，满足电网安全运行要求，特制定本规范。
本规范附录均为规范性附录。
本规范由广东电网公司生产技术部提出、归口及解释。
本规范主要起草人：鲁德锋、张泽良、段新辉、刘玮、吴国沛、王莉、毛为民、张驰、邹庆年、江文东、刘浩明、黄奕俊、贺继红、邓小玉、梁煜、叶石丰、成霞、梁东明、欧明秀、纪金水、洪毅文、徐春新、陈莉莉、刘锦兰、罗劲松、徐子利、张言权、张胜宝、吴海涛。
Ⅱ广东电网公司220～500kV元件保护验收规范1 适用范围1.1本规范规定了广东电网公司220～500kV元件保护现场验收的验收项目、验收内容和验收标准等。
1.2本规范适用于广东电网公司所辖变电站新建、扩建和改造工程的500kV变压器保护、500kV母差保护、220kV变压器保护、220kV母差及失灵保护、220kV母联（分段）保护的现场验收。
2 引用标准下列文件中的条款通过本规范的引用而成为本规范的条款。
电气化铁道专用单相交流27.5kV电缆附件技术规范
equipment other than liquid filled transformers
3. 术语及定义
冷缩式终端 将预扩张、内有支撑物的弹性体终端套在经过处理后的电缆末端，抽出支撑物，收缩压 紧在电缆上而形成的电缆终端。 冷缩式中间接头 将预扩张、内有支撑物的弹性体接头部件现场套在经过处理后的电缆连接处，抽出支撑
5. 技术要求
5.1 通用技术要求 5.1.1 电缆终端和中间接头须采用冷缩式结构，可分离连接器须采用内锥型可插拔式。 5.1.2 电缆附件的主体部分须采用进口优质硅橡胶材料整体模制而成，不应采用乙丙橡 胶。其橡胶部件及安装材料应符合本标准附录 A 的要求。 5.1.3 冷缩电缆附件的扩张率应大于 200%，以保证安装其在电缆上时足够的界面压力和 电气性能。 5.1.4 冷缩式电缆附件采用塑料芯绳的支撑方式，为保证芯绳的强度和易于抽取安装， 芯绳需采用搭扣式方式编制，每圈芯绳之间有均匀的焊接点。冷缩芯绳能从一侧被完整 抽出，不采用抽管式。 5.1.5 在正常的室温环境温度储存条件下, 中间接头和终端最少可以储存 3 年。 5.1.6 电缆终端接地线和中间头过桥线截面积应按与之相适应的电缆金属屏蔽层和铠装 层截面积相一致的原则选取。铠装接地与屏蔽接地应分开处理。接地线须采用双层结构 的铜编织线，长度不小于 1m。 5.1.7 接地线连接必须采用原装进口恒力弹簧固定连接， 自然状态下的恒力弹簧应大于 5 层，以保证长久接触良好，不会产生涡流和电位悬浮。 5.1.8 附件的主要材料采用低烟、无卤阻燃材料，材料性能符合本规范附录 B 的要求。
FR205G资料
FAST RECOVERY GLASS PASSIVATED RECTIFIERVOLTAGE RANGE 50 to 1000 Volts FR201G THRU FR207GCURRENT 2.0 AmpereFEATURESDO-15•Fast switching speed for high efficiency •Glass passivated chip junction •Low reverse leakage •High forward surge current capacity • High temperature soldering guaranteed:260 /10 seconds, 0.375” (9.5mm) lead lengthMECHANICAL DATA•Case: transfer molded plastic •Epoxy: UL94V – 0 rate flame retardant •Polarity: Color band denotes cathode end •Lead: Plated axial lead, solderable per MIL-STD-202E method 208C •Mounting position: any • Weight: 0.014 ounce, 0.39 gramMAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS•Ratings at 25O C ambient temperature unless otherwise specified •Single Phase, half wave, 60Hz, resistive or inductive load • For capacitive load derate current by 20% SYMBOLS FR 201G FR 202G FR 203G FR 204G FR 205G FR 206G FR 207GUNIT Maximum Repetitive Peak Reverse Voltage V RRM 50 100 200 400 600 800 1000 VoltsMaximum RMS Voltage V RMS 35 70 140 280 420 560 700 VoltsMaximum DC Blocking Voltage V DC 50 100 200 400 600 800 1000 VoltsMaximum Average Forward Rectified Current, 0.375” (9.5mm) lead length At T C = 55O C I (AV) 2.0 AmpsPeak Forward Surge Current8.3mS single half sine wave superimposed onrated load (JEDEC method)I FSM 70 Amps Maximum Instantaneous Forward Voltage @ 2.0AV F 1.3 Volts 5.0 Maximum DC Reverse Current at Rated T A = 25 OCDC Blocking Voltage per element T A = 125 O CI R 500 µA Maximum Reverse Recovery TimeTest conditions I F = 0.5A, I R = 1.0A, I RR = 0.25At rr 150 250 500 nS Typical Junction Capacitance(Measured at 1.0MHz and applied reverse voltage of 4.0V)C J 20 pF Typical Thermal Resistance (Note 1)R θJA 40 O C/W Operating Junction Temperature RangeT J (-65 to +175) O C Storage Temperature Range T STG (-65 to +175) O CNotes:1. Thermal resistance from junction to ambient with 0.375” (9.5mm) lead length, PCB mountedRATINGS AND CHARACTERISTIC CURVES FR201G THRU FR201G。
10520;中文规格书,Datasheet资料
© 2012 DESCO INDUSTRIES, INC.
Employee Owned
DESCO INDUSTRIES INC. Technical Bulletin TB-7042
Statguard® Static Dissipative Floor Finish Application Instructions & MSDS
General Guidelines
Made in the United States of America
Statguard® eliminates triboelectric generated charges above 100V before costly damage can occur from personnel who approach static sensitive parts and products. Statguard® also drains static charges from personnel who forget to reattach their wrist straps minimizing the damage that could occur from handling. Even when using conductive tiles, a substantial triboelectric charge is generated. When Statguard® is applied over conductive tiles, the enhanced floor tile eliminates charge generation due to walking across the floor. Generally accepted industrial stripping and floor finish application procedures are to be followed as outlined on pages 2 and 3 in this technical bulletin. Figure 1. Statguard® Static Dissipative Floor Finish NOTE: Statguard® Static Dissipative Floor Care products do not have a set life span. The chemicals are not known to degrade over time when stored at the proper temperature conditions as stated in the Material Safety Data Sheet. We also recommend that these products be stored in their original containers and be sealed when not in use. GROUNDING Conventional grounding practices like electrically connecting Statguard® Static Dissipative Floor Finish to earth ground is required for applications of static dissipative floor finish that are less than 50 square feet. For applications that are greater than 50 square feet, the capacitance of Statguard® Floor Finish is MANY, MANY times greater than the capacitance of the human body model. The difference in capacitance is so great that the Statguard® treated floor acts as a theoretical reservoir or natural ground. The capacitance and surface resistance of the Statguard® treated floor will decay a 5000v charge to zero in .05 sec. per FTMS 101B, Method 4046. Statguard® has substantially less than the maximum static decay time of 0.1 seconds. Per ESD Handbook ESD TR20.20 section 5.3.4.2 “Floor finishes and topical antistats, on the other hand. function by two separate mechanisms. First. they reduce the surface’s tendency 10 generate a stalic charge. Second, they provide a path for the dissipation of charge. The charge may dissipate over the surface of the finish or it may dissipate to ground if the floor finish is grounded.” To remove charge form personnel ESD footwear should be used in conjunction with ESD flooring. ESD footwear should be worn on both feet.