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AMD与intel CPU型号大全

AMD与intel CPU型号大全

AMD与intel CPU型号大全AMD与intel CPU型号大全CPU 厂商会给属于同一系列的CPU 产品定一个系列型号,而系列型号是用于区分CPU 性能的重要标示。

英特尔公司的主要CPU 系列型号有:PentiumPentium ProPentium IIPentium IIIPentium 4Pentium 4EEPentium-mCeleronCeleron IICeleron IIICeleron IVCeleron DXeon 等等而AMD 公司的主要CPU 系列型号有:K5K6K6-2DuronAthlon XPSempronAthlon 64Opteron 等等3、接口类型我们知道,CPU 需要通过某个接口与主板连接,才能进行工作。

CPU 经过这么多年的发展,采用的接口方式有引脚式、卡式、触点式、针脚式等。

而目前CPU 的接口,都是针脚式接口,对应到主板上,就有相应的插槽类型。

CPU 接口类型不同,在插孔数、体积、形状上都有变化,所以不能互相混用接插。

1) Socket 775Socket 775 又称为Socket T,是目前应用于Intel LGA775 封装的CPU 所对应的接口,目前采用此种接口的有LGA775 封装的Pentium 4、Pentium 4 EE、Celeron D 等CPU。

与以前的Socket 478 接口CPU 不同,Socket 775 接口CPU 的底部没有传统的针脚,而代之以775 个触点,即并非针脚式而是触点式。

通过与对应的Socket 775 插槽内的775 根触针接触,来传输信号。

Socket 775 接口,不仅能够有效提升处理器的信号强度、提升处理器频率,同时也可以提高处理器生产的良品率,降低生产成本。

随着Socket 478 的逐渐淡出,Socket 775 将成为今后所有Intel 桌面CPU 的标准接口。

2) Socket 754Socket 754 是2003年9月AMD 64 位桌面平台最初发布时的CPU 接口,目前采用此接口的,有低端的Athlon 64 和高端的Sempron,具有754 根CPU 针脚。

大数据的五大核心技术

大数据的五大核心技术

大数据的五大核心技术21世纪,世界已经进入数据大爆炸的时代,大数据时代已经来临。

从商业公司内部的各种管理和运营数据,到个人移动终端与消费电子产品的社会化数据,再到互联网产生的海量信息数据等,每天世界上产生的信息量正在飞速增长。

2009年数据信息量达到8 000亿GB,而到2011年达到1.8 ZB。

图灵奖获得者Jim Gray提出的“新摩尔定律”:“每18个月全球新增信息量是计算机有史以来全部信息量的总和”,已经得到验证。

大数据的“大”不仅仅体现在数据的海量性,还在于其数据类型的复杂性。

随着报表、账单、影像、办公文档等在商业公司中得到普遍使用,互联网上视频、音乐、网络游戏不断发展,越来越多的非结构化数据进一步推动数字宇宙爆炸。

数据海量而复杂,这是对大数据的诠释。

与传统的数据相比,大数据具有规模性(Volume)、多样性(Variety)、高速性(Velocity)和低价值密度(Value)的4V特点。

规模性和高速性是数据处理一直以来研究和探讨的问题,多样性和价值密度低是当前数据处理发展中不断显现出来的问题,而且在可以预见的未来,随着智慧城市、智慧地球等各种新设想的不断成为现实,上面的4中问题将会变得更加凸显,而且是不得不面对的问题。

数据的产生经历了被动、主动和自动3个阶段。

大数据的迅猛发展是信息时代数字设备计算能力和部署数量指数增长的必然结果。

解决大数据研究中的问题,必须要从大数据的产生背景进行研究。

大数据的产生源于规模效应,这种规模效应给数据的存储、管理以及数据的分析带来了极大的挑战,数据管理方式上的变革正在酝酿和发生。

大数据的规模效应要求其存储、运算方案也应当从规模效应上进行考虑。

传统的单纯依靠单设备处理能力纵向发展的技术早已经不能满足大数据存储和处理需求。

以Google等为代表的一些大的数据处理公司通过横向的分布式文件存储、分布式数据处理和分布式的数据分析技术很好的解决了由于数据爆炸所产生的各种问题。

英特尔 DCI 用户指南说明书

英特尔 DCI 用户指南说明书

Debugging via Intel® DCI User´s GuideRelease 02.2023Debugging via Intel® DCI User´s GuideTRACE32 Online HelpTRACE32 DirectoryTRACE32 IndexTRACE32 Documents ......................................................................................................................Intel® DCI [Direct Connect Interface] ..........................................................................................Debugging via Intel® DCI User´s Guide (1)Introduction (4)4-wire DCI OOB4 DCI OOB Hardware6 DCI DbC7 Target System Requirements8 Related Documents8Start a TRACE32 Session using Intel® DCI (9)Prepare Your Target9 Connecting to an Intel® SoC using DCI OOB9 Connecting to an Intel® Client or Server System using DCI OOB10 Connecting to an Intel® SoC using DCI DbC11 Connecting to an Intel® Client or Server System using DCI DbC12Troubleshooting (13)DCI error: no response to connect pattern13 Could not stop the target13 Target Power Fail13Intel® DCI Specific Commands (14)DCI Commands to configure the Intel® DCI trace handler14 DCI.DESTination Set trace destination14 DCI.ON Enable trace handler14 DCI.OFF Disable trace handler15 SYStem.DCI Intel® DCI specific SYStem commands16 SYStem.DCI.Bridge Select DCI bridge16 SYStem.DCI.BssbClock Configure DCI OOB clock rate16 SYStem.DCI.CKDIrouting Routing of the CK and DI signals17 SYStem.DCI.DisCONnect Force DCI disconnect17 SYStem.DCI.DOrouting Routing of the DO signals18 SYStem.DCI.PortPower Configure VBUS19 SYStem.DCI.TimeOut Configure timeouts of internal operations20Intel® DCI Specific Functions (21)In This Section21 SYStem.DCI.Bridge()Currently selected DCI bridge21 SYStem.DCI.BssbClock()Currently selected DCI OOB clock21 SYStem.DCI.TIMEOUT()Timeouts of internal operations22Debugging via Intel® DCI User´s GuideVersion 10-Feb-2023 IntroductionThe Intel® Direct Connect Interface (DCI) allows debugging of Intel® targets using the USB3 port. The technology supports debugging via the USB Stack (DCI DbC) as well as a dedicated protocol using a USB3 connector only (DCI OOB).4-wire DCI OOBDCI OOB uses a special protocol on the USB3 pins. This makes the mode independent of the actual USB implementation on the target board. This allows debugging of cold boot scenarios, reset flows, and sleep states.A BThe figure above illustrates a typical setup. A Power Debug Module with a CombiProbe and a Whisker Cable DCI OOB (LA-4515) [A] is connected to the debug host running TRACE32 PowerView. On the target side the Whisker Cable DCI OOB connects to a USB port of the target system using a short USB cable [B].TRACE32 sends DCI commands encoded in the DCI OOB protocol to the target system. In the target system the commands are decoded by the OOB module and forwarded to the DCI module where they are translated to JT AG sequences. These JT AG sequences allow to access the internal T AP of the SoC/PCH as well as externally connected JT AG devices (e.g., the CPU of a client or server system).T race data can be exported through the DCI module and recorded by the CombiProbe.DCI OOB HardwareIn the following the available DCI OOB hardware is shown.Whisker Cable DCI OOB for CombiProbe Version 1Whisker Cable DCI OOB for CombiProbe Version 2A USB cable to target system D USB connector for target system B VBUS jumper E 34-pin expansion connector (proprietary)C Cable to CombiProbeA USB cable to target system D USB connector for target system B VBUS sliderE 34-pin expansion connector (proprietary)C Cable to CombiProbeABCEDABCDEDCI DbCDCI DbC allows debugging using the OS USB stack.The figure above illustrates a typical setup. TRACE32 only runs on the debug host. The target system connects to the debug host using a USB cable.TRACE32 sends DCI commands encoded in the USB protocol to the target system using libusb and the USB Stack of the operating system. In the target system the commands are decoded by the USBimplementation and forwarded to the DCI module where they are translated to JT AG sequences. These JT AG sequences allow to access the internal T AP of the SoC/PCH as well as externally connected JT AG devices (e.g., the CPU of a client or server system).T race data can be directly exported via USB and recorded by TRACE32 on the debug host. DCI DbC also provides a DMA capability for fast download of the system RAM. Support of these capabilities by TRACE32 depends on the used target system.For using DCI DbC, please observe the “System Requirements” (usbdebug_user.pdf).Target System RequirementsFor debugging using Intel® DCI your target system must fulfill the following:•The BIOS must enable DCI debugging or provide a user option to do so. Please contact your BIOS manufacturer to clarify if your BIOS conforms to the Intel® BIOS Writer's Guiderequirements for DCI support.•For using DCI OOB, the USB part of your target system must be electrically designed such that DCI OOB signaling is not blocked. This is of special importance for USB Type-C solutions.Details about these requirements can be found in the appropriate Intel® Platform Design Guide.Related Documents•“Intel® x86/x64 Debugger” (debugger_x86.pdf)•“Debugging via USB User´s Guide” (usbdebug_user.pdf)Start a TRACE32 Session using Intel ® DCIPrepare Your TargetIrrespective of which DCI variant is used, debugging via DCI needs to be activated in the BIOS of the target system first. Please contact your BIOS manufacturer for instructions.Connecting to an Intel ® SoC using DCI OOB1.Connect your TRACE32 hardware and start the TRACE32 software, as described in “Starting a TRACE32 PowerView Instance” (training_debugger_x86.pdf).2.For SoCs configure the CPU, e.g., by executing the following command:3.Establish the debug connection:On a successful connect, the TRACE32state line displays “running” or “cpu power down”:You are now ready to debug the x86 core using DCI OOB. For information on how to continue, please refer to:•“Training Basic SMP Debugging for Intel® x86/x64” (training_debugger_x86.pdf) or •“Intel® x86/x64 Debugger” (debugger_x86.pdf)SYStem.CPU APOLLOLAKESYStem.AttachConnecting to an Intel ® Client or Server System using DCI OOB1.Connect your TRACE32 hardware and start the TRACE32 software, as described in “Starting a TRACE32 PowerView Instance” (training_debugger_x86.pdf).2.For client or server systems configure CPU, PCH, and core number e.g.:The results are displayed in the AREA.view window:3.Establish the debug connection:On a successful connect, the TRACE32state line displays “running” or “cpu power down”:You are now ready to debug the x86 core using DCI OOB. For information on how to continue, please refer to:•“Training Basic SMP Debugging for Intel® x86/x64” (training_debugger_x86.pdf) or •“Intel® x86/x64 Debugger” (debugger_x86.pdf)SYStem.CONFIG PCH SUNRISEPOINT SYStem.DETECT CPU SYStem.DETECT CORESSYStem.AttachConnecting to an Intel ® SoC using DCI DbC1.Install the target USB driver and start a TRACE32 session for USB debugging as described in “Debugging via USB User´s Guide” (usbdebug_user.pdf).2.For SoCs configure the CPU, e.g., by executing the following command:3.Select the IntelUSB0 debug port and configure the USB parameters for the debug connection, e.g., by executing the following commands:In this example, “1.” is the number of the debug enabled interface, “0x8087” is the vendor ID of the target system and “0x0A73” is the product ID of the target system.These parameters can be determined interactively as described in “Select a USB Device via the GUI” (usbdebug_user.pdf). For details, please refer to B .4.For tracing via DbC, add the configuration for the trace interface, e.g.:5.For using DMA via DbC, add the configuration for the DMA interface, e.g.:6.Establish the debug connection:On a successful connect, the TRACE32 state line displays “running” or “cpu power down”:You are now ready to debug the x86 core using DCI DbC. For information on how to continue, please refer to:•“Training Basic SMP Debugging for Intel® x86/x64” (training_debugger_x86.pdf) or •“Intel® x86/x64 Debugger” (debugger_x86.pdf)SYStem.CPU APOLLOLAKESYStem.CONFIG DEBUGPORT IntelUSB0SYStem.CONFIG USB SETDEVice Debug 1. 0x8087 0x0A73SYStem.CONFIG USB SETDEVice Trace 2. 0x08087 0x0A73SYStem.CONFIG USB SETDEVice DMA 3. 0x08087 0x0A73SYStem.AttachConnecting to an Intel ® Client or Server System using DCI DbC1.Install the target USB driver and start a TRACE32 session for USB debugging as described in “Debugging via USB User´s Guide” (usbdebug_user.pdf).2.Configure the PCH your board is using, e.g., by executing the following command:3.Configure the USB parameters for the debug connection, e.g., by executing the following commands:In this example, “1.” is the number of the debug enabled interface, “0x8087” is the vendor ID of the target system and “0x0A73” is the product ID of the target system.These parameters can be determined interactively as described in “Select a USB Device via the GUI” (usbdebug_user.pdf). For details, please refer to B .4.Run the following commands to detect CPU and core number automatically:The results are displayed in the AREA.view window:5.Establish the debug connection:On a successful connect, the TRACE32 state line displays “running” or “cpu power down”:You are now ready to debug the x86 core using DCI DbC. For information on how to continue, please refer to:•“Training Basic SMP Debugging for Intel® x86/x64” (training_debugger_x86.pdf) or •“Intel® x86/x64 Debugger” (debugger_x86.pdf)SYStem.CONFIG PCH SUNRISEPOINTSYStem.CONFIG DEBUGPORT IntelUSB0SYStem.CONFIG USB SETDEVice Debug 1. 0x8087 0x0A6ESYStem.DETECT CPU SYStem.DETECT CORESSYStem.AttachTroubleshootingThe following describes some possible error scenarios, along with suggestions how to resolve them: DCI error: no response to connect patternTRACE32 did not receive any response from the target.•Make sure the USB cable is connected to a DCI enabled USB port.•Make sure DCI is enabled in the BIOS of the target system.•Configure the DO-Routing manually. For details, see SYStem.DCI.DOrouting.•In case you are using a USB Type-C connector, try flipping the plug.•Consider removing common mode chokes in the USB path.Could not stop the targetTRACE32 could not halt the processor, but the DCI connection is working.•Make sure debugging is enabled in the BIOS of the target system.Target Power FailUsing DCI TRACE32 cannot detect whether the target system is powered. Thus all connection losses are interpreted as power fails. In case you are encountering target power fails, but your target system ispowered:•Try a lower DCI OOB clock. For details, see SYStem.DCI.BssbClock.•Consider removing common mode chokes in the USB path.Intel® DCI Specific CommandsDCI Commands to configure the Intel® DCI trace handlerThe Intel® DCI trace handler is a hardware module of the Intel® DCI implementation on the target system.This module is responsible for forwarding trace data coming from the Intel® T race Hub to a DCI transport.The DCI command group allows expert control of this hardware module. If using the Intel® T race Hub commands this configuration is done automatically (see ITH commands).See also■ DCI.DESTination ■ DCI.OFF ■ DCI.ON ■ SYStem.DCIDCI.DESTination Set trace destination Format:DCI.DESTination [OOB | DBC]Configures to which destination the trace data is routed.OOB (default)Stream the trace data to the Intel® DCI OOB interface.DBC Stream the trace data to the Intel® DCI DbC interface (USB).See also■ DCIDCI.ON Enable trace handler Format:DCI.ONEnables the trace handler.See also■ DCIDCI.OFF Disable trace handler Format:DCI.OFFDisables the trace handler.See also■ DCISYStem.DCI Intel® DCI specific SYStem commandsUsing the SYStem.DCI command group, you can configure target properties as well as the DCI OOB hardware.See also■ SYStem.DCI.Bridge ■ SYStem.DCI.BssbClock ■ SYStem.DCI.CKDIrouting ■ SYStem.DCI.DisCONnect ■ SYStem.DCI.DOrouting ■ SYStem.DCI.PortPower ■ SYStem.DCI.TimeOut ■ SYStem.state■ DCI❏ SYStem.DCI.Bridge() ❏ SYStem.DCI.BssbClock()▲ ’Intel® DCI Specific Functions’ in ’Debugging via Intel® DCI User´s Guide’SYStem.DCI.BridgeSelect DCI bridgeConfigures TRACE32 for the specific DCI bridge implementation used in your system. For known Intel ® SoCs and PCHs this setting is done automatically based on CPU/PCH settings.See also ■ SYStem.DCI❏ SYStem.DCI.Bridge()SYStem.DCI.BssbClockConfigure DCI OOB clock rateConfigures the operating frequency used by the TRACE32 DCI OOB hardware. The maximum frequency is 100 MHz. Format:SYStem.DCI.Bridge <bridge_name>Format:SYStem.DCI.BssbClock <frequency> [<slow_frequency>]<frequency>Frequency during normal operation. Default: 100MHz.<slow_frequency>Frequency used during connect and during low power phases. The default is based on the selected platform.Example: Set frequency to 50 MHz.SYStem.DCI.BssbClock 50.MHzSee also■ SYStem.DCI ❏ SYStem.DCI.BssbClock()SYStem.DCI.CKDIrouting Routing of the CK and DI signals Format:SYStem.DCI.CKDIrouting [STRAIGHTthrough | CROSSover] Configures how the CK and DI signals are mapped to the super speed rx signals on the USB 3 connector of the target. This configuration option is available for 4-wire DCI OOB only. The configuration must be set before trying to connect.STRAIGHTthrough The signals CK and DI are routed in compliance with the Intel DCIspecification. Set if the rx signals are connected one-to-one from the chipto the USB port.CROSSover The signals CK and DI are routed contrary to the Intel DCI specification.Set if the rx signals are connected cross-over from the chip to the USBport.See also■ SYStem.DCISYStem.DCI.DisCONnect Force DCI disconnect Format:SYStem.DCI.DisCONnectT erminates the low-level DCI connection.Normally TRACE32 will manage the connect and disconnect of the DCI connection used for the debug session automatically. However, in some cases explicit termination of the DCI connection is required, e.g., when TRACE32 is used together with the T32 Remote API.NOTE:SYStem.DCI.DisCONnect will not care about the overall state of your debugsession before disconnecting.T o avoid problems, execute SYStem.Down on all TRACE32 instances beforeexecuting this command.See also■ SYStem.DCISYStem.DCI.DOrouting Routing of the DO signals Format:SYStem.DCI.DOrouting [AUTO | STRAIGHTthrough | CROSSover] Configures how the DO signal pair is mapped to the super speed tx signals on the USB 3 connector of the target. This configuration option is available for 4-wire DCI OOB only. The configuration must be set before trying to connect.AUTO (default)TRACE32 tries to detect the routing automatically.STRAIGHTthrough The signals DO+ and DO- are routed in compliance with the Intel DCIspecification. Set if the tx signals are connected one-to-one from the chipto the USB port.CROSSover The signals DO+ and DO- are routed opposed to the Intel DCIspecification. Set if the tx signals are connected cross-over from the chipto the USB port.See also■ SYStem.DCISYStem.DCI.PortPower Configure VBUS Format:SYStem.DCI.PortPower <mode><mode>:OFFDISchargeSDPCDPDCPAUTODCPBC12DCPDIVSome TRACE32 DCI OOB hardware can drive the VBUS pin of the USB port from the debugger and emulate a USB charging port.Preconditions:•Base module is PowerDebug USB3.0 or PowerDebug Pro.•“Whisker Cable DCI OOB for CombiProbe Version 2”, page 6.•The yellow slider on the CombiProbe Whisker must be set to on.The following modes are available:OFF (default)Do not drive VBUS.DIScharge Discharge VBUS.SDP Standard Downstream Port according to the USB2.0 specification.CDP Charging Downstream Port according to the USB 2.0 BC1.2specification.DCPauto Dedicated Charging PortIn this mode the used DCP scheme is automatically detected.DCPBC12Dedicated Charging Port according to USB 2.0 BC1.2 specification.DCPDIV Dedicated Charging Port - Divider ModeD+ and D- of the USB port are driven to 2V and 2.7V, respectively.See also■ SYStem.DCISYStem.DCI.TimeOut Configure timeouts of internal operations Format:SYStem.DCI.TimeOut <operation> <time><operation>:SETtingsJTAGPMChandshakeConfigure the timeout for certain internal operations. Do not change unless instructed to do so by the Lauterbach support.The current value can be obtained using the SYStem.DCI.TimeOut() function.See also■ SYStem.DCI ❏ SYStem.DCI.TIMEOUT()Intel ® DCI Specific Functions In This SectionSee also■ SYStem.DCI ❏ SYStem.DCI.Bridge() ❏ SYStem.DCI.BssbClock() ❏ SYStem.DCI.TIMEOUT() SYStem.DCI.Bridge()Currently selected DCI bridge [build 68208 - DVD 09/2016]Returns the name of the currently selected DCI bridge. The bridge is selected with the SYStem.DCI.Bridge command.Return Value Type : String .Example :SYStem.DCI.BssbClock()Currently selected DCI OOB clock [build 68208 - DVD 09/2016]Returns the value of the current DCI OOB clock rate. The clock rate is configured with the SYStem.DCI.BssbClock command.Parameter Type : String .Return Value Type : Decimal value .Syntax:SYStem.DCI.Bridge() PRINT SYStem.DCI.Bridge()Syntax:SYStem.DCI.BssbClock(<clock_name>) <clock_name>:ACTIVE | DEFault | SLOW ACTIVEThe currently active DCI OOB clock. DEFaultThe value of the DCI OOB clock used during normal operation.SLOW The value of the DCI OOB clock used during connect and low powerphases.Example:PRINT SYStem.DCI.BssbClock(ACTIVE)SYStem.DCI.TIMEOUT()Timeouts of internal operations[build 79617 - DVD 02/2017] Syntax:SYStem.DCI.TIMEOUT(<operation>)<operation>:JTAG | SETtings | PMChandshakeReturns the current timeout of an internal operation. The timeout can be configured using theSYStem.CONFIG DCI.TimeOut command.Parameter Type: String.Return Value Type: Time value.。

Lustre 2.0 用户指南说明书

Lustre 2.0 用户指南说明书

Lustre™2.0Release Notes Part No. 821-2077-10July 2010, Revision 01PleaseRecycleCopyright ©2010,Oracle and/or its affiliates.All rights reserved.This software and related documentation are provided under a license agreement containing restrictions on use and disclosure and are protected by intellectual property laws.Except as expressly permitted in your license agreement or allowed by law,you may not use,copy,reproduce,translate,broadcast,modify,license,transmit,distribute,exhibit,perform,publish,or display any part,in any form,or by any means.Reverse engineering,disassembly,or decompilation of this software,unless required by law for interoperability,is prohibited.The information contained herein is subject to change without notice and is not warranted to be error-free.If you find any errors,please report them to us in writing.If this is software or related software documentation that is delivered to the ernment or anyone licensing it on behalf of the ernment,the following notice is applicable:ERNMENT RIGHTS Programs,software,databases,and related documentation and technical data delivered to ernment customers are "commercial computer software"or "commercial technical data"pursuant to the applicable Federal Acquisition Regulation and agency-specific supplemental regulations.As such,the use,duplication,disclosure,modification,and adaptation shall be subject to the restrictions and license terms set forth in the applicable Government contract,and,to the extent applicable by the terms of the Government contract,the additional rights set forth in FAR 52.227-19,Commercial Computer Software License (December 2007).Oracle USA,Inc.,500Oracle Parkway,Redwood City,CA 94065.This software or hardware is developed for general use in a variety of information management applications.It is not developed or intended for use in any inherently dangerous applications,including applications which may create a risk of personal injury.If you use this software or hardware in dangerous applications,then you shall be responsible to take all appropriate fail-safe,backup,redundancy,and other measures to ensure the safe use.Oracle Corporation and its affiliates disclaim any liability for any damages caused by use of this software or hardware in dangerous applications.Oracle is a registered trademark of Oracle Corporation and/or its affiliates.Oracle and Java are registered trademarks of Oracle and/or its affiliates.Other names may be trademarks of their respective owners.AMD,Opteron,the AMD logo,and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices.Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation.All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International,Inc.UNIX is a registered trademark licensed through X/Open Company,Ltd.This software or hardware and documentation may provide access to or information on content,products,and services from third parties.Oracle Corporation and its affiliates are not responsible for and expressly disclaim all warranties of any kind with respect to third-party content,products,and services.Oracle Corporation and its affiliates will not be responsible for any loss,costs,or damages incurred due to your access to or use of third-party content,products,or services.1Lustre 2.0Release NotesThe Lustre 2.0Release Notes describe the testing environments,new features and enhancements,major fixes and known issues for Lustre 2.0.Tested EnvironmentsLustre 2.0has been tested against the following Linux platforms,architectures 1and interconnects.Downloadable Lustre packages (RPMs)are available for the Linux platforms listed below.1.We encourage the use of 64-bit platforms.Linux Platform **Lustre does not support security-enhanced (SE) Linux (including clients and servers).Architecture Interconnect ServerOEL 5.4RHEL 5.4x86_64Client OEL 5.4RHEL 5SLES 10,11Scientific Linux 5[New]Fedora 12(2.6.31)[New]x86_64ia64(RHEL)ppc64(SLES)i686Server and ClientTCP/IPOFEDNew FeaturesLustre2.0introduces the following new features and enhancements.Lustre2ArchitectureLustre2.0introduces a new architecture for the metadata server(MDS)and clients.This architecture,known as Lustre2,establishes a stable foundation for platformportability and major performance optimizations in future Lustre releases.ChangelogsChangelogs record events that change the file system namespace or file metadata.Events such as file creation,deletion,renaming,attribute changes,etc.are recordedwith the target and parent file identifiers(FIDs),the name of the target,and atimestamp.These records can be used for a variety of purposes:■Record recent changes to feed into an archiving system.■Use changelog entries to exactly replicate changes in a file system mirror.■Set up"watch scripts"that take action on certain events or directories.Changelog record are persistent(on disk)until explicitly cleared by the user.The areguaranteed to accurately reflect on-disk changes in the event of a server failure.■Maintain a rough audit trail(file/directory changes with timestamps,but no user information).2Lustre 2.0 Release Notes•July 2010Commit on ShareThe Commit on Share(COS)feature prevents missing clients from causing the evictions of other clients when Lustre is in recovery mode.If some clients miss the recovery window,the remaining clients are not evicted.When an MDS starts up and enters recovery mode after a failover or service restart, clients begin to reconnect and replay their uncommitted transactions.If one or more clients miss the recovery window,this may cause other clients to abort their transactions or be evicted.The transactions of evicted clients cannot be applied and are aborted.This causes a cascade effect as transactions dependent on the aborted ones fail and so on.COS addresses this problem by eliminating dependent transactions.With no dependent,uncommitted transactions to apply,the clients replay their requests independently without the risk of being evicted.COS is controlled with the MDT’s commit_on_sharing parameter,which can be set to1(enabled)or0(disabled).In Lustre2.0.0,COS is disabled,by default.To enable COS,set commit_on_sharing to1on the MDS node:# lctl set_param mdt.<mdt-name>.commit_on_sharing=1To disable COS,set commit_on_sharing to0on the MDS node:# lctl set_param mdt.<mdt-name>.commit_on_sharing=0To store the commit_on_sharing parameter on disk,use mkfs.lustre or tunefs.lustre with--param mit_on_sharing=0/1.Lustre_rsyncThe lustre_rsync feature provides namespace and data replication to an external (remote)backup system without having to scan the file system for inode changes and modification times.Lustre metadata changelogs are used to record file system changes and determine which directory and file operations to execute on the replicated system.Lustre_rsync avoids full file system scans,which can be time-consuming on very large file systems.Lustre_rsync can be restarted from where it left off,so the replicated file system is fully synchronized when operation completes. Lustre_rsync may be bi-directional for distinct directories.The replicated system may be another Lustre system or any other file system.The replica is an exact copy of the namespace of the original file system at a specific time. However,the replicated file system is not a snapshot of the source file system;its contents may differ from the original file system's contents.On the replicated file system,each file contains the data present when the file transfer occurred.Lustre 2.0 Release Notes3Size-on-MDS(Preview)Note–In Lustre2.0,size-on-MDS(SOM)is available as a preview feature.SOM isstill under development,so it should not be enabled on a2.0production system.The size-on-MDS feature caches file object attributes(file size,number of blocks,ctime and mtime)on the MDS;these attributes were originally stored on the OSTs.Storing the SOM cache on the MDS allows clients to issue just one RPC per file to theMDS and avoid sending multiple RPCs to the OSTs to find the file object attributeskept on those OSTs.The SOM enhancement significantly improves the performanceof the directory listing command(ls-l).Size-on-MDS can be enabled when the file system is created,using mkfs.lustre orset later when the file system is running,using lctl.The SOM parameter is$FSNAME.mdt.som=$MODE,where$FSNAME is the file system name("lustre"bydefault)and$MODE is"enabled"or"disabled".Note–Once SOM is enabled on the MDS,clients can only mount the file system ifthe som_preview mount option is specified.The som_preview option must begiven on the client,not the MDS.To create a file system with SOM enabled,run:$ mkfs.lustre --mdt --param=mdt.som=enabledTo enable/disable SOM on an existing file system,run:$ lctl conf_param $FSNAME.mdt.som=$MODESOM mode is applied after the file system is shut down,not on the fly.For more information on SOM,see BZ22864.Landings to Lustre Master for2.0For a list of all bugs that were resolved and landed to Lustre Master(HEAD)and tono earlier Lustre branches,see Bugs Landed on HEAD.For a list of all bugs fixed forthis release,see the2.0changelog.4Lustre 2.0 Release Notes•July 2010Known Issues and WorkaroundsThis section describes known issues with Lustre2.0,which will be resolved in future releases.■BZ16893(Enabling ext4by default)Enabling ext4allows LUNs larger than8TB to be used in the Lustre file system.When ext4is enabled,by default,in a system at scale,servers become overloaded (cause unknown).This results in clients timing out and attempting to reconnect, an action which the server does not accept.Eventually,the server evicts the client due to a lock timeout.Workaround:Do not enable ext4in Lustre2.0.0.■BZ16919(Asynchronous journal commit functionality)Lustre asynchronous journal commit adds support for Lustre clients to submit write requests to an OST,but not require the server to do the I/O synchronously.Instead,the client keeps a copy of the data in cache until it receives a commit notification from the OST and rewrites the data if the OST crashes.This allows a single client to submit a large number of writes without having to commit the journal transaction.This enhancement was completed after the Lustre2.0code freeze.Workaround:If asynchronous journal commits are needed,use Lustre1.8.0or later(the latest1.8version is recommended).■BZ16774(Avoid replaying unused locks during recovery)During recovery,Lustre clients can overwhelm the servers by replayingthousands of unused locks.This bug was fixed after the Lustre2.0code freeze.It will be available in a later2.0.x release.Workaround:If this bug fix is needed,use Lustre1.8.2or later.■BZ22040(Parallel_scale_nfsv4test times out after running13000seconds) Using flock on an NFSv4export of a Lustre file system can cause applications to hang.The root issue(tracked in BZ14080)will be fixed after Lustre2.0.0isreleased.Workaround:We recommend not using flock on NFSv4until BZ14080is fixed.Lustre 2.0 Release Notes5Additional DocumentationThe Lustre2.0Operations Manual is a comprehensive resource that describes how toinstall,configure,and tune Lustre2.0.The manual also contains troubleshooting andutilities information,and tips to improve Lustre operations and performance.For thelatest version of the Lustre2.0manual,see:/manual/LustreManual20_HTML/index.htmlThe Lustre2.0Changelog describes networks and kernels that were tested with thisLustre version and provides a comprehensive list of fixed bugs.For the latest versionof the Lustre2.0changelog,see:/index.php/Change_Log_2.06Lustre 2.0 Release Notes•July 2010。

华硕B85M-G主板说明书C8146

华硕B85M-G主板说明书C8146
全國聯保............................................................................................................................... iii 安全性須知.................................................................................................................................. viii
B85M-G
用戶手冊
Motherboard
C8146
第一版(V1) 2013 年 5 月
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Latitude 5490 快速入门指南.pdf_1700880557.4193065说明书

Latitude 5490 快速入门指南.pdf_1700880557.4193065说明书

1Connect the power adapter andpress the power buttonSambungkan adaptor daya dan tekan tombol dayaConecte el adaptador de alimentación y presione el botón de encendidoليغشتلا رز ىلع طغضلاو رايتلا ئياهم ليصوتب مقProduct support and manualsDukungan dan panduan produkManuales y soporte del productoةلدلأاو جتنملا معد/support/support/manuals/support/windowsContact DellHubungi Dell | Comuníquese con DellDell ةكرشب لصتا/contactdellRegulatory and safetyPeraturan dan keselamatan | Información reglamentariay de seguridad | ةيميظنتلا تامولعملاو ناملأا/regulatory_complianceRegulatory modelModel peraturan | Modelo reglamentarioيميظنتلا زارطلاP72GRegulatory typeTipe peraturan | Tipo reglamentarioيميظنتلا عونلاP72G002Computer modelModel komputer | Modelo de computadoraرتويبمكلا زاهج زارطLatitude-54902017-11 What’s NewApa yang Baru | Novedadesةديدجلا تازيملا• Supports Dual (7th Gen Intel Core) and Quad (8th Gen Intel Core)processors• Supports up to 2400 MHz DDR4 memory with 8th Gen Intel Coreprocessors• Mendukung prosesor Dual (Intel Core Generasi Ke-7) dan Quad(Intel Core Generasi Ke-8)• Mendukung hingga 2400 MHz memori DDR4 dengan prosesorIntel Core Generasi Ke-8• Compatibilidad con procesadores dobles (Intel Core de 7.a generación)y procesadores cuádruples (Intel Core de 8.a generación)• Compatibilidad con memoria DDR4 de hasta 2400 MHz con procesadoresIntel Core de 8.a generaciónليجلا نم Intel Core( ةاونلا ىعابرو )عباسلا ليجلا نم Intel Core( ةاونلا يئانث تاجلاعملا معد)نماثلانماثلا ليجلا نم Intel Core تاجلاعم عم زترهاجيم 2400 ىلإ لصت ةعرسب DDR4 ةركاذ معد© 2017 Dell Inc. or its subsidiaries.© 2017 Intel Corporation.FeaturesFitur-fitur | Funciones |تازيملا1. Puerto de red2. Cámara3. Indicador luminoso de estado de lacámara4. Ranura para tarjeta microSIM(opcional)5. Puerto HDMI6. Puerto USB 3.1 Gen 17. Puerto del conector de alimentación8. Emisor de infrarrojos (opcional)9. Cámara infrarroja (IR) (opcional)10. Cámara (opcional)11. Indicador luminoso de estado de lacámara (opcional)12. Micrófonos de arreglo doble13. Indicador LED de botón deencendido/estado de alimentación14. Ranura para cierre de seguridadNoble15. Puerto VGA16. Puerto USB 3.1 de primera generacióncon PowerShare17. Puerto para auriculares y micrófono18. Lectora táctil de huellas dactilares(opcional)19. Indicador luminoso de estado decarga de la batería20. Lectora de tarjetas sin contacto(opcional)21. Altavoces22. Superficie táctil23. Lector de tarjetas inteligentes(opcional)24. Puntero (opcional)25. el lector de tarjetas SD26. Puerto USB 3.1 Gen 127. DisplayPort por USB Tipo C28. Indicador luminoso de estado delmicrófono29. Etiqueta de servicio1. Port jaringan2. Kamera3. Lampu status kamera4. Slot kartu SIM mikro (opsional)5. Port HDMI6. Port USB 3.1 Gen 17. Port konektor daya8. Pemancar inframerah (IR) (opsional)9. Kamera inframerah (opsional)10. Kamera (opsional)11. Lampu status kamera (opsional)12. Rangkaian Mikrofon Ganda13. Tombol daya/LED status daya14. Slot kunci Nobel Wedge15. Port VGA16. Port USB 3.1 Tdengan PowerShare17. Port Headset/Microphone18. Pembaca sidik jari sentuhan(opsional)19. Lampu status pengisian baterai20. Pembaca kartu nirkontak (opsional)21. Speaker22. Panel sentuh23. Pembaca kartu pintar (opsional)24. Pointstick (optional)25. pembaca kartu SD26. Port USB 3.1 Gen 127. DisplayPort di atas USB Tipe-C28. Lampu status mikrofon29. Label Tag Servis16. USB 3.1 Gen 1 port with PowerShare17. Headset/Microphone port18. Touch Fingerprint reader (optional)19. Battery charge status light20. Contactless card reader (optional)21. Speakers22. Touchpad23. Smart card reader (optional)24. Pointstick (optional)25. SD card reader26. USB 3.1 Gen 1 port27. DisplayPort over USB Type-C28. Microphone status light29. Service Tag label1.ةكبشلا ذفنم2.اريماكلا3.اريماكلا ةلاح حابصم4.)ةيرايتخا( micro-SIM ةقاطب ةحتف5.HDMI ذفنم6.لولأا ليجلا نم USB 3.1 ذفنم7.رايتلا لصوم ذفنم8.)IR( ءارمحلا تحت ةعشلأا ثب زاهج)يرايتخا(9.ءارمحلا تحت ةعشلأاب ةلماعلا اريماكلا)يرايتخا( )IR(10.)ةيرايتخا( اريماكلا11.)يرايتخا( اريماكلا ةلاح حابصم12.ةيئانثلا فيفصلا تانوفوركيم13.ةقاطلا ةلاحل LED حابصم/ةقاطلا رز14.Nobel Wedge لفق ةحتف15.VGA ذفنم16.دوزم لولأا ليجلا نم USB 3.1 ذفنمPowerShare ةزيمب17.نوفوركيملا/سأرلا ةعامس ذفنم18.لمعي يذلا عبصلإا ةمصب ئراق)يرايتخا( سمللاب19.ةيراطبلا نحش ةلاح حابصم20.)يرايتخا( يكلسلالا ةقاطبلا ئراق21.توصلا تاربكم22.سمللا ةحول23.)يرايتخا( ةيكذلا ةقاطبلا ئراق24.)يرايتخا( ريشأتلا اصع25.SD ةقاطب ئراق26.لولأا ليجلا نم USB 3.1 ذفنم27.نم USB ربع DisplayPort ذفنمC عونلا28.نوفوركيملا ةلاح حابصم29.ةمدخلا زمر قصلم。

intel cpu型号大全

intel cpu型号大全

intel cpu型号大全2009年12月24日星期四 15:12intel cpu型号大全按照处理器支持的平台来分,Intel处理器可分为台式机处理器、笔记本电脑处理器以及工作站/服务器处理器三大类;下面我们将根据这一分类为大家详细介绍不同处理器名称的含义与规格。

由于Intel产品线跨度很长,不少过往产品已经完全或基本被市场淘汰(比如奔腾III和赛扬II),为了方便起见,我们的介绍也主要围绕P4推出后Intel发布的处理器产品展开。

台式机处理器Pentium 4(P4)第一款P4处理器是Intel在2000年11月21日发布的P4 1.5GHz处理器,从那以后到现在近四年的时间里,P4处理器随着规格的不断变化已经发展成了具有近10种不同规格的处理器家族。

在这里面,“P4 XXGHz”是最简单的P4处理器型号。

这其中,早期的P4处理器采用了Willamette核心和Socket 423封装,具256KB二级缓存以及400MHz前端总线。

之后由于接口类型的改变,又出现了采用illamette核心和Socket478封装的 P4产品。

而目前我们所说的“P4”一般是指采用了Northwood核心、具有400MHz前端总线以及512KB二级缓存、基于Socket 478封装的P4处理器。

虽然规格上不一样,不过这些处理器的名称都采用了“P4 XXGHz”的命名方式,比如P4 1.5GHz、P4 1.8GHz、P4 2.4GHz。

Pentium 4 A(P4 A)有了P4作为型号基准,那么P4 A就不难理解了。

在基于Willamette核心的P4处理器推出后不久,Intel为了提升处理器性能,发布了采用Northwood 核心、具有 400MHz前端总线以及512KB二级缓存的新一代P4。

由于这两种处理器在部分频率上发生了重叠,为了便于消费者辨识,Intel就在出现重叠的、基于Northwood核心的P4处理器后面增加一个大写字母“A”以示区别,于是就诞生了P4 1.8A GHz、P4 2.0A GHz这样的处理器产品。

[IT168评测]九大主流横向扩展文件系统存储对比评测_IT168文库

[IT168评测]九大主流横向扩展文件系统存储对比评测_IT168文库

【IT168 评测】对于IT主管来说,为大数据构建一个同时具有高可扩展性和成本效益的存储基础架构是非常关键的,也是必要的。

日前,Garter对目前市场主流的九大存储供应商所推出的9款横向扩展文件系统产品进行了对比评测分析,并指出了各自的有点和需改进的地方,以供用户在采购时进行对比参考,以下为报告主要内容(注:本译文部分有删减): 海量非结构化数据的存储和分析日趋重要,已经上升到战略高度,这使得在IT基础设施规划中,横向扩展存储架构将成为最突出的问题。

横向扩展存储产品往往能够实现接近线性的缩放,并通过并发来提供高性能。

大多数横向扩展存储供应商倾向于采用X86标准化硬件,从而降低硬件的采购成本,并在软件层嵌入存储信息。

横向扩展存储供应商的主要目标市场一般都是学术机构或特定行业的 HPC环境,例如基因组测序、金融建模、三维动画、气象预报和地震分析等。

因此,产品的主要关注点在于其可扩展性、原始计算能力和聚合带宽,数据保护、安全和效率则是次要考虑因素。

但是,企业对于容量空间、存储效率以及非结构化数据保护方面的需求越来越强烈,迫使供应商提供更好的安全性、可管理性、数据保护以及ISV互操作性来满足客户的需求。

虽然大多数产品用作通用存储阵列的情况还很少,但向这方面发展的趋势将会越来越明显。

IT组织必须要制定严格的规划流程来全面评估产品的关键能力以选择合适横向扩展存储供应商。

厂商需要针对特定使用情况继续优化其产品,尽管在本研究报告中,这些领先供应商兼顾到了其产品在企业环境中使用可能出现的各种情况。

但是,横向扩展存储的意识和全局命名空间在企业IT环境中并不常见,所以培训支出应该是预算分配的重要组成部分。

本研究的目的在于比较三种常见的用例——商业HPC、大的主目录以及备份和归档,并在9个关键能力方面进行考量。

非结构化数据的增长趋势明显已经超过了结构化数据。

企业和服务提供商所要求的高可扩展性和弹性存储基础设施必须在合理的成本之内,才能解决大数据的挑战,并构建云计算基础。

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