圆片级封装的新颖对准技术
先进封装案例
先进封装案例随着科技的快速发展，集成电路（IC）的集成度和性能要求越来越高，传统的封装技术已经无法满足这些需求。
因此，先进封装技术应运而生，并成为当前集成电路领域的研究热点。
本文将介绍一些先进的封装案例，包括芯片堆叠技术、2.5D/3D集成、扇出型封装、晶圆级封装、集成无源器件、异构集成、高频电子、先进热管理、可靠性验证和先进材料应用。
一、芯片堆叠技术芯片堆叠技术是一种将多个芯片垂直堆叠在一起，实现三维集成的技术。
这种技术可以提高集成度、减小体积、降低成本，同时还可以提高信号传输速度和降低功耗。
例如，苹果公司的iPhone X采用了芯片堆叠技术，将多个芯片垂直堆叠在一起，实现了高性能的摄像头和处理器。
二、2.5D/3D集成2.5D/3D集成是一种将多个芯片通过硅中介层或直接在晶圆上集成在一起的技术。
这种技术可以实现更高密度的集成，提高芯片间的互连速度和降低功耗。
例如，AMD的Ryzen处理器采用了2.5D集成技术，将多个芯片集成在一起，实现了高性能的处理器。
三、扇出型封装扇出型封装是一种将芯片从传统的封装形式中解放出来的技术。
这种技术可以实现更高的集成度和更小的体积，同时还可以提高散热性能和降低成本。
例如，台积电的7纳米工艺采用了扇出型封装技术，实现了高性能的处理器和存储器。
四、晶圆级封装晶圆级封装是一种将多个芯片直接在晶圆上集成在一起的技术。
这种技术可以实现更高的集成度和更小的体积，同时还可以提高生产效率和降低成本。
例如，华为的Mate 20采用了晶圆级封装技术，实现了高性能的摄像头和处理器。
五、集成无源器件集成无源器件是指在芯片上集成的无源元件，如电阻、电容和电感等。
这种技术可以减小电路板的体积和重量，提高电路的性能和可靠性。
例如，德州仪器的MAX10系列微控制器采用了集成无源器件技术，实现了高性能的数字信号处理和控制器。
六、异构集成异构集成是指将不同类型的芯片或组件集成在一起的技术。
这种技术可以实现更高的性能和更小的体积，同时还可以提高生产效率和降低成本。
圆片级封装介绍(wafer level packaging)
Table of ContentsINFORMATION (1)1 CONTACT2 INTRODUCTION (3)2.1Overview (3)2.2History (3)3 CHOOSING A BUMPING PROCESS (5)3.1Standard Flip Chip – Bump on I/O (5)3.1.1Standard Flip Chip-Bump on I/O Process Summary (6)3.1.2I/O requirements for the SFC-Bump on I/O process (7)3.2Standard Flip Chip--Repassivation (8)3.2.1SFC-Repassivation Process Summary (9)3.3Standard Flip Chip--Redistribution (10)3.3.1SFC-Redistribution Process Summary (10)3.4Spheron TM WLCSP (12)3.4.1Spheron WLP™ Redistribution Process Flow (12)3.5Ultra CSP® (14)3.5.1Ultra CSP Process Summary (14)3.6Elite UBM™, Elite FC™, and Elite CSP™ – Electroless Ni/Au (17)3.6.1Elite UBM™ – Process Flow (17)3.6.2Elite FC™ – Process Flow (18)3.6.3Elite CSP™ – Process Flow (19)3.7Available Solder Alloys (21)3.7.1Basic Physical Properties of Solder Paste Alloys (21)3.7.2Basic Physical Properties of Pre-Formed Solder Ball Alloys (21)3.8Other Services (22)3.8.1Laser Mark (22)3.8.2“In Process” Backgrind (22)3.8.3“Post Process” Backgrind (22)3.8.4Electronic Wafer Yield Maps (23)3.8.5Post Bump Electrical Testing (23)3.8.6Dicing and Packaging (23)4 DESIGN RULES AND GUIDELINES (24)4.1Overview (24)4.2Incoming Wafer Requirements (24)4.2.1Types of Wafers (24)4.2.2SEMI Material Requirements (24)4.2.3Wafer Scribe Requirements (24)4.2.4Wafer Backside Requirements (24)4.2.5Acceptable Wafer Size (24)4.2.6Wafer Edge Exclusion Requirements (25)4.2.7Incoming Wafer Thickness (25)4.3Device Requirements (25)4.3.1Die Size (25)4.3.2Number of Sites Bumped Per Die (25)4.3.3Die Layout (25)4.3.4Unique Die on Wafer (25)4.3.5Types of Passivation (26)4.3.6Types of Final Metal (26)4.3.7Probing (26)4.3.8Ink Dots (26)4.3.9Fuse Links (27)4.3.10Nitride Passivation Openings Not Bumped (27)4.3.11Street Width (27)4.3.12Special Elite UBM, Elite FC, and Elite CSP Device Requirements (27)4.3.13Passivation Opening Sidewalls (28)4.4Alignment Feature Requirements (28)4.5What Information Does FlipChip Need For New Mask Designs? (29)CONSIDERATIONS (30)5 DESIGN5.1Pitch, UBM Size, and Bump Height Relationships (30)5.2Packaging Relationships (31)5.2.1SFC, Repassivation, and Redistribution Package Stand-Off Height (31)5.2.2UltraCSP, Spheron WLP, and EliteCSP Package Dimensions (31)5.2.3WLP Package Stand-Off Heights (32)5.3Printed-Circuit Board Layout (33)5.3.1WL-CSP Stencil and Board Design Parameters (34)5.4Reliability Testing (34)PROPERTIES (35)6 MATERIAL6.1Benzocyclobutene (BCB) (35)6.2Spheron WLP Polymer (36)6.3Solder Alloy Material Properties (37)6.4UBM Metal Properties (37)6.5SFC-Redistribution Trace Electrical Properties (38)6.6Ultra CSP Redistribution Trace Electrical Properties (38)7 GLOSSARY (39)1Contact InformationTo start your relationship with FlipChip, contact the appropriate Sales Representative. Each is an expert at learning the particular needs of your device. In addition, your FlipChip Sales Representative can discuss all aspects of pricing, logistics, cycle time, and answer any other question you may have.Worldwide Sales RepresentativesFred Hickman IIIVice President -- Sales and MarketingFlipChip International, LLCPhoenix, AZ, USA 85034Phone: 602-431-4749E-mail: fred.hickman@AsiaJay HayesSr. Director of Strategic AccountsFlipChip International, LLCMonument, CO, USAPhone: 719-481-6444E-mail: jay.hayes@California and Northwest U.S.A.Jim GrahamRegional Account ManagerFlipChip International, LLCSanta Clara, CA, USAPhone: 408-395-4765Cell: 408-761-0808E-mail: jim.graham@Southwestern U.S.A., Eastern U.S.A., Canada andGeneral Technical InquiresBret TrimmerSr. Account ManagerFlipChip International, LLCPhoenix, AZ, USAPhone: 602-431-4760Cell: 480-643-9034E-mail: bret.trimmer@Central U.S.A.Bruce BowersVice President -- Business Development FlipChip International, LLCPhoenix, AZ, USAPhone: 602-431-6634E-mail: bruce.bowers@EuropeDave McCombDirector of European Business and Sales FlipChip International, LLCHawick, Scotland, UKPhone: +44 1450 373 919E-mail: david.mccomb@EuropeDavid ClarkEuropean Sales EngineerFlipChip International, LLCIpswich, Suffolk, UKPhone: +44 7875 307 633 E-mail: david.ckark@2 Introduction2.1 OverviewThank you for your interest in FlipChip International, LLC for your wafer bumping needs. This guide will take you through the process of deciding which bumping flow is right for you. In addition, the guide will give you the basics of each process flow, incoming wafer requirements, device requirements, material properties, and a glossary, so you may have a better understanding of the bumping process.2.2 HistoryFlipChip International, LLC started out in 1996 as Flip Chip Technologies (FCT), a joint venture between Delco Electronics Systems and Kulicke & Soffa Industries (K&S). Delco brought the patented Flex-On-Cap (or FoC) flip chip process and over 30 years of experience from the automotive industry. K&S added its knowledge and leadership position as the world's largest supplier of semiconductor assembly equipment. By any measure, the company was a huge success. The company’s Flex-on-Cap (FoC) standard flip chip bumping technology quickly became the industry standard for flip chip bumping.In 1998, FCT developed and patented the Ultra CSP® Wafer Level Chip Scale Package (WL-CSP), which quickly became the industry standard for WL-CSP. FlipChip began an aggressive licensing program to bring its unique bumping technology to a broader worldwide market. Today, the semiconductor industry’s packaging heavyweights, including Amkor Technology, Advanced Semiconductor Engineering (ASE), Siliconware (SPIL), and STATS ChipPAK license and use FlipChip’s bumping technology.In 2001, K&S acquired Delco’s remaininginterest in FCT and we became the Flip ChipDivision of Kulicke & Soffa. In 2004,RoseStreet Labs, LLC, a private research anddevelopment company based in Phoenix,completed the acquisition of the assets of theFlip Chip Division from Kulicke & Soffa, throughits newly formed subsidiary -- FlipChipInternational, LLC. In early 2005, FCI acquiredIC Services, which became the Die SalesDivision of FCI (or FCI-DSD). The Die SalesDivision continues its long tradition of providingwafer thinning, dicing, Automated OpticalInspection (AOI), Waffle Pack, and Tape & Reelservices.In 2005 FlipChip acquired a license to produce Electroless Ni/Au from the Fraunhofer/IZM Institute of Berlin. The initial target applications of E-less Ni/Au are high temperature power devices and low cost RFID applications. The new process was in commercial production in 2006.In 2006, FlipChip announced that it had entered into a joint venture with Millennium Microtech to form FlipChip Millennium Shanghai (FCMS). FCMS opened in March of 2007 and provides “Turn-Key” wafer bumping and die packaging services, focusing on the Asian market.In 2007, FlipChip entered into strategic partnerships with several domestic testing houses to provide Electrical Testing as part of Turn-Key wafer processing.In addition to bumping services, FlipChip has an aggressive program to develop and generate intellectual property for future implementation at FlipChip and for our licensee’s. Our commitment to leadership and quality in wafer bumping solutions continues, ensuring that FlipChip remains the leader in developing, and bringing to market, the latest bumping technology.The main bumping facility for FlipChip is located in the World Headquarters building in Phoenix, Arizona, USA. We have a state of the art, 16,000-ft2 (4700 m2) class 1000 clean room. FlipChip is ISO9001:2000 and ISO14001 certified.FCI World Headquarters –- Phoenix, AZ Die Sales Division -– Tempe, AZFCMS Bumping Facility -- Shanghai, China RoseStreet Labs Facility -- Phoenix, AZ3 Choosing a Bumping ProcessHere we look at the different bumping services offered by FlipChip. To make it easy, we have broken our services into the different processes. Each one is perfect for a different bumping situation, from the simplest to the most complex. Look these over and decide which process will meet your needs. If you still can’t decide, give us a call! We’ll be glad let you know which process will work best for you. We are experts at matching up a standard process flow to your device. Keep in mind that we are a development driven engineering organization. For unusual devices, we can often design a custom process flow that will completely meet your needs.3.1 Standard Flip Chip – Bump on I/OOur Standard Flip Chip (SFC) process, formerly known as the Flex-on-Cap (or FoC) process, was created in the mid-1960’s by Delco for use in the automotive industry. Today, the process has 40 years and over a million bumped wafers behind it. This is the process to use when you need to place small bumps (less than 135µm in height) directly on the die I/O. Pitch capabilities in this process are 150µm or greater for a full array I/O design and 120µm or greater for a peripheral I/O design. Typically, the number of bumps per die ranges from 4 to 6000. The SFC process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal restraints of an electroplating process, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, these die will require the use of underfill during packaging.To take advantage of this process flow, the device must meet some minimum I/O pad requirements (described below in section 3.1.2). If the device does not meet these minimum I/O pad requirements, take a look at section 3.2, which describes the SFC Repassivation flow. If you are looking for bump heights greater than 135µm, take a look at section 3.4, which covers the UltraCSP flow – the industry standard Wafer Level Package (WLP) process flow.3.1.1 Standard Flip Chip-Bump on I/O Process SummaryThe SFC-Bump on I/O process requires the fewest process steps of any flow that FlipChip offers. Below is an outline of the flow:UBM3.1.2 I/O requirements for the SFC-Bump on I/O processSince the SFC-Bump on I/O process forms a bump directly on the device I/O, certain criteria must be followed to ensure a proper bump structure. The basic rule is what we call “The Golden Rule of Flip Chip”, which is:•The UBM must overlap the I/O passivation opening by at least 7µm and the I/O final metal pad must extend at least 5µm past the end of the UBM.Figure 1 shows the “Golden Rule” requirements for the UBM in relation to the passivation opening and the I/O metal bond pad. This rule requirement accomplishes several reliability requirements. The overlap of the UBM to the passivation opening provides a seal to the underlying I/O aluminum bond pad. The overlap of the UBM inside the I/O metal bond pad eliminates stresses that can cause silicon cratering.Figure 1. The Golden Rule of Flip ChipThe allowable size of the UBM is directly related to I/O Pitch. The bump height is strongly influenced by UBM size. Please see the section 5.1 “Pitch, UBM Size, and Bump Height Relationships” as a guide as to what size your UBM will be.If your device does not meet the requirements of the Golden Rule, your device may be a candidate for the SFC-Repassivation process, which is described in the next section.3.2 Standard Flip Chip--RepassivationThe SFC-Repassivation process is similar to the SFC-Bump on I/O process, but it is designed for die that do not meet all of the I/O final metal pad and passivation opening requirements of SFC-Bump on I/O. In this process, a layer of Benzocyclobutene (or BCB) repassivation is deposited on the die before bumping. The BCB passivation corrects for the issue of the I/O passivation opening being too large for a standard flip chip bump. It also corrects for the issue of the I/O final metal pad being too small for a standard flip chip bump. The BCB layer planarizes the device surface and gives the bump structure additional strength and robustness.As with SFC-Bump on I/O, SFC-Repassivation is designed for small bumps (less than 135µm) placed directly on the die I/O. Pitch capabilities in this process are 150µm or greater for a full array I/O design and 140µm or greater for a peripheral I/O design. The number of bumps per die typically ranges from 4 to 600. The SFC-Repassivation process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal restraints of an electroplating bath, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, die bumped with the SFC-Repassivation process will require the use of underfill during packaging.If your device contains bumps that will not be placed directly on the I/O, take a look at the next section (3.3), which describes the SFC-Redistribution flow. If you are looking for bump heights greater than 140µm, take a look at section 3.4, which covers the UltraCSP flow – the industry standard Wafer Level Chip Scale Package (WL-CSP) process flow.3.2.1 SFC-Repassivation Process SummaryThe SFC-Repassivation process requires relatively few process steps to complete the flow. Below is an outline of the process flow (none of the drawings are to scale):Deposit and pattern a layer of BCB passivation.Deposit three layer (Al/NiV/Cu) Under Bump Metalization (or UBM) stack.Pattern UBM pads.Deposit pre-mixed solder paste.Reflow solder.- PIQ3.3 Standard Flip Chip--RedistributionOn some die, the I/O are not located where you need to have the bumps. This is especially true when you take an existing die that is wire bonded and would like to convert it to flip chip. The SFC-Redistribution Line (or RDL) process adds “redistribution metallization” (often called “runners’ or “traces”) that let you re-route the signal path from the die peripheral I/O to the new desired bump locations. This process is usually seen as a transitional solution between a die that is designed for wire bonding and a die that is designed for flip chip. Redistribution is designed to produce bumps of less than 135µm in height, although the typical bump height is 100µm. Pitch capabilities in this process are 70µm or greater. Standard Redistribution line widths are 38µm with 38µm space between lines. For fine pitch designs, FlipChip will go down to 25µm lines and 12µm space between lines. Since the process is not limited to the bi-metal restraints of an electroplating bath, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, these die will require the use of underfill during packaging.3.3.1 SFC-Redistribution Process SummaryThe SFC-Redistribution process requires more process steps than the SFC-Bump on I/O or the SFC-Repassivation flows. Below is an outline of the SFC-Redistribution process flow (none of the drawings are to scale):Deposit and pattern first layer of BCB passivation (BCB1).Deposit four layer (Al/NiV/Cu/Ti) UBM stack.I/O Final Metal Bond padEtch UBM stack to form redistribution runners and bump pads.Deposit, pattern, and cross-link second layer of BCB passivation (BCB2).Deposit solder paste (Proprietary Process).Reflow solder.Cu UBM3.4 Spheron TM WLCSPFlipChip offers a new type of Wafer Level Chip Scale Packaging (WLCSP) that utilizes a unique dielectric material, which offers improved capacitance decoupling and reliability. In addition to the advanced polymer, Spheron WLP TM incorporates a new metal structure, which offers improved strength and electrical performance. Benefits of Spheron WLP include: improved electrical performance, reduced capacitive coupling between UBM/Solder and the underlying IC circuitry, improved solder joint reliability, significant improvement in TC performance due to die planarization/polymer film characteristics, and elimination of incoming wafer topology issues. In addition, the planarized polymer film ensures proper UBM step coverage, even over non-planarized devices. Spheron is compatible with nitrides and oxides.As with Ultra CSP, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed for final bump heights of 200µm to 400µm. In this process, the bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 – 100. Die bumped with Spheron WLP typically do not require underfill. Spheron WLCSP, as well as all FlipChip packages, is classified as JEDEC Level 1 compliant.3.4.1 Spheron WLP™ Redistribution Process FlowThe Spheron WLP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. An example of the redistributed process is shown (none of the drawings are to scale).I/O Final Metal Bond Wafer Silicon Device PassivationCoat first dielectric layer (Spheron1), expose, develop, and cure.Sputter metal redistribution layer. Pattern and etch to form redistribution runners.Coat second dielectric layer (Spheron2), expose, develop, and cross-link.Deposit and pattern three layer UBM (Al/NiV/Cu).Attach pre-formed solder ball.Reflow Solder3.5 Ultra CSP®Ultra CSP® is our patented Wafer Level Chip Scale Package (or WLCSP) process. Since its introduction in 1998, Ultra CSP has become the industry standard for WLCSP. Bump heights for the process range from 200µm to 450µm. In this process, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed. The bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 – 100. Die bumped with Ultra CSP do not require underfill until the bump array reaches the 6x6 to 7x7 size. Then underfill may be needed. The lack of underfill makes it easy to migrate TSOP or QFP to Ultra CSP. Ultra CSP, as well as all FlipChip packages, is classified as JEDEC Level 1 compliant.3.5.1 Ultra CSP Process SummaryThe UltraCSP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. Both processes are summarized below (none of the drawings are to scale).3.5.1.1 Ultra CSP Bump on I/O -- Process FlowDeposit and pattern a layer of BCB passivation.Deposit three layer (Al/NiV/Cu) Under Bump Metalization (or UBM) stack.Pattern UBM pads.Attach pre-formed solder ballReflow solder.3.5.1.2 UltraCSP Redistributed -- Process FlowDeposit and pattern first layer of BCB passivation (BCB1).Deposit three layer (Al/NiV/Cu) UBM stack.I/O Final Metal Bond padPattern UBM Pads and Runners.Deposit, pattern, and cross-link second layer of BCB passivation (BCB2).Attach Pre-formed Solder Ball.Reflow solder.3.6 Elite UBM™, Elite FC™, and Elite CSP™ – Electroless Ni/AuIn 2005 FlipChip acquired a license to produce Electroless Ni/Au (E-less Ni/Au) from the Fraunhofer/IZM Institute of Berlin. E-less Ni/Au is available in three configurations: EliteUBM, EliteFC, and EliteCSP. EliteUBM is simply a Ni/Au pad ranging in height from 5µm to 30µm. Typical applications for EliteUBM are low cost RFID tags. Elite packages, as well as all FlipChip packages, are classified as JEDEC Level 1 compliant.EliteFC is a Flip Chip size bump that uses the low cost E-less Ni/Au UBM. Typical bump heights are 70µm - 160µm. EliteFC can often be used as a lower cost alternative to traditional Standard Flip Chip.EliteCSP is a Wafer Level-Chip Scale Package (WL-CSP) that uses the E-less UMB structure. As with Ultra CSP, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed for final bump heights of 200µm to 400µm. Typical applications for EliteCSP are high power / high temperature devices.Devices that are to be bumped using any of the Elite processes need to have some special requirements met. These requirements are described in Section 4.3.12.3.6.1 Elite UBM™ – Process FlowClean Aluminum/Cu Final Metal Pad.ZincApply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincCoat UBM with a thin layer of Gold (oxidation protection).3.6.2 Elite FC™ – Process FlowDevice PassivationClean Aluminum/Cu Final Metal Pad.ZincApply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincCoat UBM with a thin layer of Gold (oxidation protection).Deposit pre-mixed solder paste.Reflow Solder3.6.3 Elite CSP ™ – Process FlowClean Aluminum/Cu Final Metal Pad.Apply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincDevice Passivation ZincCoat UBM with a thin layer of Gold (oxidation protection).Attach pre-formed solder ball.Reflow Solder3.7 Available Solder AlloysFlipChip offers several different solder alloys to mach your needs. By using pre-mixed solder paste and pre-formed solder balls, alloy composition is very tightly controlled. This means that your solder balls have predictable and reliable reflow characteristics.3.7.1 Basic Physical Properties of Solder Paste AlloysThe SFC-Ball on I/O, SFC-Repassivation, and SFC-Redistribution processes use pre-mixed solder paste to form the final solder bumps. The table below gives the basic properties of the paste alloys (for complete physical properties of solder alloys, see section 6.3).Table 1. Physical Proprieties of Paste AlloysAlloy / Property Sn/Ag/Cu Lead Free (SAC 351) 63Sn37Pb Standard EutecticAlloy Composition Sn 95.5%Ag 3.5%Cu 1.0%Sn 63%Pb 37%Melting 217°C Eutectic 183°C EutecticReflow Temperature 235°C to 255°C 215°C to 225°CAlpha Emissions(counts/cm2/hr)<0.002 N/A3.7.2 Basic Physical Properties of Pre-Formed Solder Ball AlloysThe Ultra CSP, Spheron, and Polymer Collar WLP processes use pre-formed solder balls. Thestandard solder ball sizes are 0.25mm (250µm), 0.3mm (300µm), 0.35mm (350µm), 0.4mm(400µm), and 0.5mm (500µm). The basic physical properties of the pre-formed solder balls arelisted on the table below (for complete physical properties of solder alloys, see section 6.3).Table 2. Physical Proprieties of Pre-Formed Solder Ball AlloysAlloy / Property Sn/Ag/Cu LeadFree (SAC 266) Enhanced Lead FreeSn/Ag/Cu (SAC 105)Eutectic63Sn37PbHigh Lead95Pb5SnAlloy Composition Sn 96.8%Ag 2.6%Cu 0.6%Sn 98.5%Ag 1.0%Cu 0.5%DopantSn 63%Pb 37%Sn 5%Pb 95%Melting Point 218°C – 220°C 218°C – 220°C 183°CEutectic 308°C - 314°CReflow Temperature 235°C to 255°C 235°C to 255°C 215°C to225°C 325°C to 335°CAlpha Emissions (counts/cm2/hr) <0.002 <0.002 N/AN/A3.8 Other Services3.8.1 Laser MarkFor die identification and traceability, FlipChip gives you theoption of using a Laser to mark the backside of each die.FlipChip can mark any alphanumeric character down to aminimum character size of 0.20 mm square with a characterdepth of approximately 4 - 6µm. Simple graphics includingcircles, squares, triangles, etc. can be used for the optionalpin 1 indicator. We can even mark simplified graphicsconsisting of basic shapes including circles, squares,triangles, etc. for company logos. FlipChip has thecapability to mark accurately any die to a minimum diedimension of 0.8 mm. If you need custom designs, giveFlipChip a call. We can custom match a laser program foryour needs.3.8.2 “In Process” BackgrindMany times, wafers need to be thinned to meet final packaging requirements. For Ultra CSP, Spheron WLP, EliteCSP, and Polymer Collar WLP, FlipChip has the ability to backgrind wafers, during processing, just before the solder balls are applied. Wafers are course ground with a wheel of 320 – 360 grit and polished ground with a wheel of 2000 grit. Below are our backgrinding/processing capabilities. (For thickness requirements on incoming wafers, please see section 4.2.7 “Incoming Wafer Thickness.”) Please contact FlipChip if you have thinner backgrinding requirements.Table 3. Wafer Thickness After “In Process WL-CSP” BackgrindingWafer Size 6 inch (150mm) 8 inch (200mm)Minimum Wafer Thickness After Backgrind 14 mil(356µm)14 mil (456µm)3.8.3 “Post Process” BackgrindFor Standard Flip Chip (SFC), Repassivated Standard Flip Chip (RP-SFC) and Redistributed Standard Flip Chip (RP-SFC), FlipChip has the ability to backgrind wafers, after the bumping process is completed Wafers are course ground with a wheel of 320 – 360 grit and polished ground with a wheel of 2000 grit. Below are our backgrinding/processing capabilities. Please contact FlipChip if you have thinner backgrinding requirements.Table 4. Wafer Thickness After “Post Process SFC” BackgrindingWafer Size 6 inch (150mm) 8 inch (200mm)Minimum Wafer Thickness After Backgrind 12 mil(305µm)12 mil (305µm)3.8.4 Electronic Wafer Yield MapsWafer yield mapping data is either presented on paper (shipped with the wafers) or by electronic wafer maps (transmitted over secure FTP sites). FlipChip uses Simplified INF (SINF), the industry standard file format, for all electronic wafer maps. FTP sites can be easily and quickly set up for secure data transfer. Contact FlipChip for details.3.8.5 Post Bump Electrical TestingAfter bumping, FlipChip can have the dice electrically tested on a variety of test platforms including:•Advantest•Agilent / HP•Credence•Eagle•Credence•Nextest•LTX•TeradyneContact FlipChip for a complete description of electrical testing capabilities.3.8.6 Dicing and PackagingIf desired, FlipChip will have your finished wafers diced, to your specifications. After dicing, visual inspection, either by sampling or 100% will be performed. The die will then be packaged in tape-and-reel or waffle pack configurations. For complete dicing and packaging descriptions and capabilities, contact FlipChip.4 Design Rules and Guidelines4.1 OverviewFlipChip has developed a set of design rules and guidelines to ensure that your wafers will be processed successfully. These rules allow for FlipChip to use standardized process flows using industry standard process equipment. FlipChip has extensive data that shows the reliability of devices processed under these design rules. The rules presented below represent a generalization of the actual FlipChip Design Specifications, which are subject to revisions and may not apply to all devices. If you have wafers that do not meet these guidelines or if you have any questions, give FlipChip a call. Since we are a development driven engineering organization, we can often create a custom solution to for even the most unusual bumping situation. We will always work with you to ensure your total satisfaction.4.2 Incoming Wafer Requirements4.2.1 Types of WafersFlipChip can process Silicon (all types) and Silicon/Germanium wafers. Contact FlipChip if you have other types of wafers (Quartz, Sapphire, etc.), we will discuss our capabilities on non-standard wafer types. FlipChip cannot currently process GaAs wafers.4.2.2 SEMI Material RequirementsAll wafers must meet current SEMI material requirements. These specifications cover major areas such as: wafer diameter (dimension and tolerance), polish, edge profile, notches, and major and minor flat sizes, locations, and orientations. It is highly recommend that 8-inch (200 mm) wafers have a notch rather than a flat.4.2.3 Wafer Scribe RequirementsIt is highly recommended that each wafer have a unique scribe number. Typically, the device lot number and the wafer number (within the lot) are scribed on each wafer.4.2.4 Wafer Backside RequirementsFor proper processing, the backside must be smooth, without ridges, bumps, or protrusions. The backsides of incoming wafers ideally should be exposed Silicon or Silicon/Germanium. Some types of backside coatings are acceptable. Call FlipChip if your wafers are backside coated.4.2.5 Acceptable Wafer SizeFlipChip accepts wafers of the following sizes: 6 inch (150mm), and 8 inch (200mm). If you have other wafer sizes, contact FlipChip and we will discuss our capabilities on non-standard wafer sizes.。
mems晶圆级封装
mems晶圆级封装mems晶圆级封装是一种先进的封装技术，用于封装微电子机械系统（Micro-Electro-Mechanical Systems，MEMS）的晶圆级封装。
MEMS晶圆级封装具有体积小、重量轻、功耗低、集成度高等特点，被广泛应用于微机电传感器、微机电执行器和微机电系统等领域。
MEMS晶圆级封装的主要目的是将MEMS器件封装在晶圆级别上，以提高封装密度和可靠性。
传统的MEMS封装往往需要将MEMS 器件单独封装起来，然后再与电路板连接。
而MEMS晶圆级封装则将MEMS器件直接封装在晶圆上，可以在晶圆级别上进行测试、封装和组装，从而大大提高了封装效率和产品质量。
MEMS晶圆级封装的关键技术包括封装工艺、封装材料和封装结构。
封装工艺是指将MEMS器件与晶圆进行精密的对位、粘接和封装等工艺。
封装材料则需要具备良好的粘接性、密封性和耐腐蚀性，以保护MEMS器件免受外界环境的影响。
封装结构则需要根据MEMS器件的特点和应用需求设计，以实现最佳的性能和可靠性。
MEMS晶圆级封装的优势主要体现在以下几个方面：MEMS晶圆级封装可以实现高集成度。
由于MEMS器件直接封装在晶圆上，可以实现多个MEMS器件在同一晶圆上的集成，从而大大提高了封装密度和系统集成度。
这对于一些对尺寸和重量要求较高的应用非常有利。
MEMS晶圆级封装可以提高封装效率。
由于MEMS器件在晶圆级别上进行封装，可以通过自动化的生产线进行大规模的生产，大大提高了封装效率和生产能力。
这对于工业化生产和大规模应用非常重要。
MEMS晶圆级封装可以提高产品质量和可靠性。
由于MEMS器件在晶圆级别上进行测试、封装和组装，可以及时发现和修复封装过程中的问题，从而提高了产品质量和可靠性。
这对于一些对产品质量和可靠性要求较高的应用非常关键。
MEMS晶圆级封装还可以降低成本。
由于MEMS晶圆级封装可以实现高集成度和高封装效率，可以大幅降低封装成本。
这对于一些对成本要求较高的应用非常有利。
晶圆级封装（Fan
晶圆级封装（Fan便携式及手持电子设备的小型化，激发了传统BGA和CSP封装往更小尺寸的发展趋势。
芯片级封装（Chip Scale Package，CSP），是芯片面积与封装面积之比接近1:1的一种封装形式，而晶圆级封装（Wafer Level Package，WLP)，可以认为是一种经过改进和提高的CSP，广泛应用于智能手机、可穿戴设备等领域的集成电路，如功率放大器、电源模块、射频滤波器、存储器及逻辑电路等。
晶圆级封装，以晶圆片为加工对象，在晶圆片上同时对多个芯片进行全部的封装及测试，最后再切割成单个器件，使用时直接贴装到基板或印刷电路板上。
由于晶圆级封装的封装尺寸与基板或印制电路板上安装面积相同，所以WLP通常被认为是集成电路封装的最终形式，10mm2的芯片，如采用典型的QFP扁平封装占据约900mm2的安装面积，载带自动焊封装（Tape Automated Bonding，TAB是将芯片组装在金属化柔性高分子聚合物载带上的封装技术）、板上芯片封装（Chip On Board，COB是将晶圆直接安装到印制电路板，然后用键合丝实现互联，再用有机材料涂覆到晶圆上完成后期封装）分别占据550mm2、300mm2，而WLP只需约100mm2的安装面积，这就表明WLP可以使整机模块尺寸更小、重量更轻、集成度更高，同时成本也更低。
WLP主要用于具有以下功能的集成电路：o低引脚数（≤200）o焊球间距范围为0.50mm、0.40mm、0.35mm和0.30mmo小尺寸芯片（≤5mm*5mm）o低成本、低端o大批量使用晶圆级封装后的体积与集成电路的裸芯片基本一致，并且整合了芯片的前端和后端工艺，封装成本也随着晶圆尺寸（圆片级封装的成本与每个圆片上的芯片数量密切相关，晶圆尺寸的增加，每个晶圆就可以生产更多的IC，芯片数越多，晶圆级封装的成本也就越低）的增加或IC封装尺寸的降低而减少晶圆级封装以晶圆形式的批量生产工艺进行制造，加工效率高，与其它封装类型相比，尺寸也较小，很好的满足便携式电子设备尺寸不断减小的需求；在传输性能上，有效增加了数据传输的频宽并减少了信号损耗，提升了数据传输的速度和稳定性；在散热性能上，由于WLP没有像传统封装的塑封料或陶瓷包封，所以散热能力效果更优；另外，晶圆级封装的芯片设计和封装设计可以统一考虑、同时进行，这将大大提高设计效率，从芯片制造、封装再到产品发往用户的整个过程中，周期也会大幅缩减晶圆级封装（Fan-in WLP）工艺技术从封装技术特点上看，晶圆级封装主要分为Fan-in和Fan-out两种形式。
封装扇出型晶圆级封装
封装扇出型晶圆级封装
封装扇出型晶圆级封装是一种新型的封装技术，它是将多个芯片封装在同一晶圆上，通过扇出线连接到外部引脚，从而实现高密度、高性能的集成电路封装。
这种封装技术在现代电子产品中得到了广泛应用，特别是在移动设备、计算机、通信设备等领域。
封装扇出型晶圆级封装的优点在于其高度集成、高性能、低功耗、小尺寸等特点。
它可以将多个芯片封装在同一晶圆上，从而实现高度集成，减少了电路板的数量和尺寸，提高了系统的可靠性和稳定性。
同时，扇出型晶圆级封装还可以通过优化电路设计和布局，实现低功耗和高性能的要求，从而满足现代电子产品对高性能和低功耗的需求。
封装扇出型晶圆级封装的制造过程也非常复杂，需要先进行芯片的制造和测试，然后将芯片粘贴在晶圆上，并通过微影技术进行线路的制造和连接。
最后，通过切割和封装等工艺，将晶圆切割成单个芯片，并封装成最终的产品。
这种制造过程需要高度的技术和设备支持，因此，封装扇出型晶圆级封装的成本也比较高。
封装扇出型晶圆级封装是一种非常先进的封装技术，它可以实现高度集成、高性能、低功耗、小尺寸等特点，满足现代电子产品对高性能和低功耗的需求。
虽然其制造成本较高，但随着技术的不断进步和成本的降低，封装扇出型晶圆级封装将会得到更广泛的应用。
先进封装技术完整版
先进封装技术目录：1.BGA技术2.CSP封装技术1倒装焊技术1晶圆级封装技术(WLP) 13D封装技术1SiP1柔性电子2.CSP封装技术WB －CSP 剖面示意图和外形图CSP•什么是CSP?─CSP--Chip Scale (Size) Package ─封装外壳的尺寸不超过裸芯片尺寸1.2倍(JEDEC 等共同制定的标准)─按互连方式，CSP 可分为WB 和FC 两种─缺乏标准化─引脚间距: 1.0, 0.75, 0.5mm 1.有效减小封装厚度和面积，利于提高组装密度2.有效降低电容、电感的寄生效应，大幅提高电性能3. 可利用原有的表面安装设备和材料4.散热性能优良特点:•结构特征─在IC的引出焊区的基础上,将引脚再分布(redistribution)─结构主要包括IC芯片, 互连层,保护层及焊球(凸点)刚性基板CSP引线框架式CSP焊区阵列式CSP2. CSP封装技术– 微小模塑封型CSP•微小模塑封型CSP①结构①结构②工艺再布线工艺流程•几种CSP互连的比较•CSP技术的应用情况•CSP发展仍需解决的问题：– 产品标准化问题– 二次布线技术– 封装材料– 组装CSP产品的印制电路板问题– 成本控制3. 倒装焊技术4. 晶圆级封装(Wafer level packaging)4.晶圆级封装•定义在通常制作IC芯片的Al焊区完成后，继续完成CSP的封装制作，称之为晶圆级CSP（WLCSP),又称作晶圆级封装。
它是一种以BGA技术为基础，是一种经过改进和提高的CSP，综合了BGA、CSP的技术优势。
•WLP 的主要技术种类•工艺5. 3D封装技术5. 3D封装技术• 3D封装的基本概念3D封装技术又称立体封装技术。
与传统封装技术相比，在原有基础上向Z方向即向空间发展的微电子封装高密度化。
• 3D封装技术的特点：– 更有效的利用基板，提高硅效率– 通过更短的互联获得更高的电性能– 有效降低系统成本•3D封装的主要类型：─ 芯片堆叠封装（Die stacking)以芯片叠层为特色，在单一封装衬底上叠加上两层或者多层芯片Samsung公司 6－Die 叠层封装芯片–封装体堆叠（Package stacking)在其内部经过完整测试的封装被堆叠到另一个经过完整测试的封装上部–晶圆级堆叠(Wafer-level stacking)3-D晶圆堆叠是通过对具有特殊功能的完整晶圆的生产达到的，这些晶圆垂直互连。
晶圆级芯片封装
晶圆级芯片封装晶圆级芯片封装是指将芯片直接封装在晶圆上，以实现更高的集成度和更小的体积。
在制造过程中，晶圆级芯片封装是非常重要的一步。
本文将从以下几个方面对晶圆级芯片封装进行详细介绍。
一、晶圆级芯片封装的概念和意义1.1 晶圆级芯片封装的定义晶圆级芯片封装是指将裸露的芯片直接封装在晶圆上，以实现更高的集成度和更小的体积。
它是半导体制造过程中非常重要的一步。
1.2 晶圆级芯片封装的意义晶圆级芯片封装可以提高半导体器件的集成度和性能，并且可以减小器件体积，降低生产成本。
此外，在大规模集成电路领域，晶圆级芯片封装也可以提高生产效率。
二、晶圆级芯片封装工艺流程2.1 芯片选切在制造过程中，先要从整个硅块中选择出符合要求的区域，并对其进行切割。
这个过程称为芯片选切。
2.2 芯片清洗选切好的芯片需要进行清洗，以去除表面的杂质和污垢。
这个过程可以使用化学溶液或超声波等方法。
2.3 芯片涂胶在芯片表面涂上一层粘合剂，以便将其固定在晶圆上。
这个过程称为芯片涂胶。
2.4 晶圆准备在晶圆上涂上一层粘合剂，以便将芯片固定在晶圆上。
此外，还需要对晶圆进行清洗和烘干等处理。
2.5 排列芯片将芯片放置在晶圆上，并按照一定的排列方式进行布局。
此外，还需要进行对齐和精细调整等操作。
2.6 封装焊接将芯片与晶圆焊接起来，并用封装材料将其密封起来。
这个过程可以使用焊接机器或激光焊接等方法。
三、晶圆级芯片封装的优势和不足3.1 优势（1）提高集成度：通过直接将芯片封装在晶圆上，可以实现更高的集成度。
（2）减小体积：晶圆级芯片封装可以减小器件的体积，从而提高产品的便携性和可靠性。
（3）降低成本：晶圆级芯片封装可以降低生产成本，提高生产效率。
3.2 不足（1）技术难度高：晶圆级芯片封装需要高精度的设备和技术，制造难度较大。
（2）适用范围有限：由于其制造难度较大，晶圆级芯片封装只适用于一些特定的领域和应用场景。
四、晶圆级芯片封装的应用4.1 大规模集成电路在大规模集成电路领域，晶圆级芯片封装可以提高生产效率，并且可以实现更高的集成度和更小的体积。
第13章-先进封装技术
图 CBGA结构图
4.载带球栅阵列（TBGA）
也称为阵列载带自动键合（Array Tape Automated Bonding,ATAB），是一种相对新 颖的BGA封装。
TBGA优点：
比其它BGA封装轻、小； 电性能优良； 装配的PCB上，封装效率高。
13.2 CSP技术
刚性基板封装
3、引线框架式CSP封装（Custom Lead Frame）
由日本Fujitsu公司开发的此类CSP封装基本 结构如下页图所示。它分为Tape-LOC和MFLOC 两种形式，将芯片安装在引线框架上， 引线框架作为外引脚，因此不需要制作焊料 凸点，可实现芯片与外部的互连。它通常分 为Tape-LOC和MF-LOC 两种形式。
世界上首款BGA封装的主板芯片组i850
1.塑料球栅阵列（PBGA）工艺流程
PBGA（Plastic Ball Grid Array） PBGA的载体用材料：FR-4环氧树脂，与PCB用材
料相同； 芯片通过引线键合技术连接到载体上表面； 采用塑封进行载体塑模； 采用阵列式低共熔点37Pb/63Sn焊料（约在183℃
引线框架式CSP
4、圆片级CSP封装（Wafer-Level Package）
封装见下页图。它是在圆片前道工序完成后，直接 对圆片利用半导体工艺进行后续组件封装，利用划 片槽构造周边互连，再切割分离成单个器件。
WLP主要包括两项关键技术即再分布技术和凸焊点 制作技术。
它有以下特点：
①相当于裸片大小的小型组件（在最后工序切割分片）； ②以圆片为单位的加工成本（圆片成本率同步成本）； ③加工精度高（由于圆片的平坦性、精度的稳定性）。
BGA定义：
实现先进晶圆级封装技术的五大要素
实现先进晶圆级封装技术的五大要素追溯芯片封装历史，将单个单元从整个晶圆中切割下来再进行后续封装测试的方式一直以来都是半导体芯片制造的“规定范式”。
然而，随着芯片制造成本的飞速提升以及消费市场对于芯片性能的不断追求，人们开始意识到革新先进封装技术的必要性。
对传统封装方式的改革创新，促成了晶圆级封装技术（Wafer Level Package，WLP）的“应运而生”。
晶圆级封装技术可定义为：直接在晶圆上进行大部分或全部的封装、测试程序，然后再进行安装焊球并切割，产出一颗颗的IC 成品单元（如下图所示）。
(图片来源：长电科技)晶圆级封装技术与打线型（Wire-Bond）和倒装型（Flip-Chip）封装技术相比，能省去打金属线、外延引脚（如QFP）、基板或引线框等工序，所以具备封装尺寸小、电气性能好的优势。
封装行业的领跑者们大多基于晶圆模式来批量生产先进晶圆级封装产品，不但可利用现有的晶圆级制造设备来完成主体封装制程的操作，而且让封装结构、芯片布局的设计并行成为现实，进而显著缩短了设计和生产周期，降低了整体项目成本。
先进晶圆级封装的主要优势包括：1.缩短设计和生产周期，降低整体项目成本；2.在晶圆级实现高密度I/O 互联，缩小线距；3.优化电、热特性，尤其适用于射频/微波、高速信号传输、超低功耗等应用；4.封装尺寸更小、用料更少，与轻薄、短小、价优的智能手机、可穿戴类产品达到完美契合；5.实现多功能整合，如系统级封装（System in Package，SiP）、集成无源件（Integrated Passive Devices，IPD）等。
需要强调的一点是，与打线型封装技术不同，用晶圆级封装技术来实现腔内信号布线（Internal Signal Routing）有多个选项：晶圆级凸块（Wafer Bumping）技术、再分布层（Re-Distribution Layer）技术、硅介层（Silicon Interposer）技术、硅穿孔（Through Silicon Via）技术等。
晶圆级封装技术
封装加工效率很高，它以圆片形式的批量生产工艺进行制造； 具有倒装芯片的优点，即轻、薄、短、小； 圆片级封装生产设备费用低，可利用圆片的制造设备，无须投资另建
新的封装生产线； 圆片级封装的芯片设计和封装设计可以统一考虑、并同时进行，这将
提高设计效率，减少设计费用； 圆片级封装从芯片制造、封装到产品发往用户的整个过程中，大大减
不同的WLP 结构
第三种WLP 结构如图(c)所示，是在图（b)结构的基础 上，添加了UBM 层。由于添加了这种UBM 层，相应 增加了制造成本。这种UBM 能稍微提高热力学性能。
图（d）所示的第四种WLP 结构，采用了铜柱结构， 首先电镀铜柱，接着用环氧树脂密封。
扩散式WLP（fan-out WLP）
所示为典型的晶圆凸点制作 的工艺流程。 首先在晶圆上完成UBM 层 的制作。然后沉积厚胶并曝 光，为电镀焊料形成模板。 电镀之后，将光刻胶去除并 刻蚀掉暴露出来的UBM 层。 最后一部工艺是再流，形成 焊料球。
电镀技术可以实现很窄的凸点节 距并维持高产率。并且该项技术 应用范围也很广，可以制作不同 尺寸、节距和几何形状的凸点， 电镀技术已经越来越广泛地在晶 圆凸点制作中被采用，成为最具 实用价值的方案。
晶圆级封装（WLP）
晶圆级封装简介 晶圆级封装基本工艺 晶圆级封装的研究进展和发展趋势
晶圆级封装（Wafer Level Package,WLP)是以BGA技术为基 础，是一种经过改进和提高的CSP技术。有人又将WLP称为圆片 级—芯片尺寸封装（WLP-CSP）。圆片级封装技术以圆片为加 工对象，在圆片上同时对众多芯片进行封装、老化、测试，最后 切割成单个器件，可以直接贴装到基板或印刷电路板上。它可以 使封装尺寸减小至IC 芯片的尺寸，生产成本大幅度下降。
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圆片级封 装 的新 颖对 准技 术
Ｃ．ｒｂｋｒ ＴＧｌ ｓｅ ， ．ｉ ｎｒ Ｍ．ｉ ｈｅ２ 高仰 月译 Ｂ ｕａｅ ． ｉ ｎｔ ＰＬｎ ｅ２ Ｔｓ ｌ ； ， ｎ ： ｄ ， ｃ ｒ
（ ． Ｖ Ｇ ｏ ｐＵＳＩｃ，７ １ ．ｎｖ ｒｉ ｉ ，ｕｔ ３ ０Ｐ ｏ ｎｘ Ａ ８ ０ ４ＵＳ １ Ｅ ｒｕ ， ． ０ ＥＵ ｉ ｓｙＤｒ ｅＳ ｉ ０ ｈ ｅ ｉ， Ｚ ５ ３ ， Ａ； ｎ ３ ｅ ｔ ｖ ｅ
ａｉ ｍｅ ｔ ｎ ｏ ｄｎ ， ｓｗｅｌ ｓ ｈ ｉ ｍｏ ｕａ ｔ ｒ ｕ ｌ ｎｅ ｒｔ ｎｉｔ ｉｈｖ ｌｍｅｐ ｏ ｕ ｔ ｎ ｌ ｅ ｌ ｎ ｇ ｎ ｄｂ ｎ ｉｇ ａ ｌ ａ ｅｒ ｄ ｌｒ ｆ ｌ ｉｔｇ ａｉ ｎｏｈ【 ｏｕ ｒ ｄ ｃｉ ｎ ｓ ａ ｔ ｉ ｏ ｆ ｙ ｏ ｇ ｏ ｉ
２Ｅ ． ＶＧｒｕ ，ｔ ｌ ｒ ｎＡ一 ７ ０Ｓ ｈ ｅｄｎ ， ｓｒａ ｏ ｐＳ ． ｏ ｉ ， ４ ８ ｃ ａ ｒ ｉｇＡｕ ｔｉ） Ｆ ａ
摘 要 ： 于 ３ 互 连 、 片级 封 装 （ Ｐ） 先 进 的 ＭＥ 对 Ｄ 圆 ＷＬ 和 ＭＳ器件 的 圆 片键 合 ， 密 对 准是 一 项 关 精
ｌ ｅ ｐ ｃ ａ ｅ （ Ｐ ａｄａ ｖ ｎｅ ＭＳｄｖｃ ｓ Ｕ ｌ ｅＭＥ ， ｉ ｒｑ ｅ ｔ ｖ ｌｅｄ ｕ ｌ ｅ ｌ ａｋ ｇ ｓ ＷＬ ） ｎ ｄ ａ ｃｄＭＥ ｅ ｉ ． ｎｉ ＭＳ ｗｈｃ ｆ ｕ ｎｌ ｉ ｏｖ ｏ ｂｅ ｖ ｅ ｋ ｈ ｅ ｙｎ
ｓｄ ｒ ｃ ｓ ｉ ｇ Ｉ ａ ｄ ＣＭ ＯＳ ｍａ ｕ ａ ｔｒｎ ｉ ａ ｅ ｈ ｏ ｄ ｉ ｔｒａ ｅ ｉ ． ａ ｅ ｔ ａ ｅ ｉ ｅ ｐ ｏ ｅ ｓｎ ， Ｃ ｎ ｎ ｆ ｃｕ ｉ ｇ ｓｔ ｔ ｄ ｉ ｔ ｅ ｂ ｎ ｅ ｆ ｃ ｅ ｆ ｃ ｏ ｆｃ ． ｕ ｎ ｎ ． Ｔ ｉ ｐ ｐ ｒｗｉ ｅ ｏ ｔ ｎ ｔ ｅｐ ｎ ｉ ａ ｔｐ ｆ ｈ ａ ｅ ｔ ａ ｅ ａｉ ｍ ｅ ｔ ｅｈ ｄ ａ ｄ ｏ ｅ ｌｔ ｓ ｈ ｓ ａ ｅ ｌ ｒ ｐ ｒ ｏ ｒ ｃ ｐ ｌ ｅ ｓ ｅ ｆ ｃ ｆｃ ｌ ｌ ｈ ｉ ｓ ｏ ｔ ｏ ｎ ｇ ｎ ｔ ｏ ， ｎ ｎ ｔ ａｅ ｔ ｍ ｈ ｒ ｓ ｌ ｅ ｏ ｉｇ ｏ ｅ ｍｉｒ ｎ ｏ ｅ ｔｒａ ｉ ｍｅ ｔ ｃ ｕ ａ ｙ ｔ ａ ｒ ｏ ｔ ｅｙ ｏ ｔ ｉｅ ｔ ｐ ｃａ ｌ ｅ ｅ ｕ ｔ ｒ ｐ ｒ ｎ ｎ ｃ ｏ ｒ ｔ ｌ ｓ ｔ ｂ ｅ ｎ ｇ ｎ ｃ ｒ ｃ ｔ ｅ ｒ ｕ ｉ ｌ ｂ ａｎ ｄ ｗｉ ａ ｓ ｅ ｉ ｌ ｄ — ａ ｈ ａ ｎ ｈ ｙ ｖ ｌ ｐ ｄ ａｉ ｎ ｅ ｔ ｓ ｓ ｍ ｈ ｔｕ ｅ ｈ ｓ ｍｅｈ ｄ Ｔ ｅ ｐ ｎ ｉ ａ ｑ ｉ ｍｅ ｔ ｄ ｓｇ ｓ ｆ ｒ ｗａｅ ｏ ｗａ ｅ ｅｏ ｅ ｌ ｍ ｎ ｙ ｔ ｇ ｅ ｔ ａ ｓ ｓ ｔ ｉ ｔ ｏ ． ｈ ｒ ｃｐ ｌｅ ｕ ｐ ｎ ｅ ｉ ｆ ｒ ｔ ｆｒ ｉ ｎ ｏ
ｗｉ ｅ ｄ ｓ ｕ ｓ ｄ ｌ ｂ ｉｃ ｓ ｅ ． １ Ｋｅ ｗｏ ｄ ： Ｄ ｎ ｅ ｃ ｎ ｅ ｔ Ａｌ ｍｅ ｔ Ｂｏ ｄ ｎ ； ＥＭ Ｓ Ｐ ｃ ａ ｉ ｇ Ｓ ａ ｋ ｎ ｙ ｒ ｓ ３ Ｉ ｔｒ ｏ ｃ； ｉ ｎ ｇ ｎ ； ｎ ｉｇ Ｍ ； ａ ｋ ｇ ｎ ； ｔｃ ｉ ｇ
Ｎｏ ｅ ｉ ｎｍ ｅ ｔＴｅ ｈ ｌ ｇ ｅ ｒ Ｗ ａ ｅ ｖ ｌＰａ ｋａ Ｆｏ ｆ ｒ Ｌｅ ｅ ｃ ｇ ｎｇ
Ｃ． ｕ ａ ｅ Ｔ Ｇｌ ｓ ｅ２Ｐ．ｉｄ ｅ Ｍ ． ｓｈｅ ２ Ｂｒ ｂ ｋ ｒ ． ｉ ｎ ｒ， Ｌ ｎ ｎ ￣， Ｔｉｃ ｌｒ ， ｎ
键技 术 ， 同的 ＭＥ ， 常 包含 双 面加 工 处理 ， ｌ 和 Ｃ 不 ＭＳ 常 而 Ｃ ＭＯＳ制 造 业 则只 利 用单 面加 工 处理 步
骤， 因此 ， 圆片 到 圆 片的对 准 必 须使 用设 置在 键 合 界 面 （ 就 是 面对 面 ） 也 中的对 准 标记
论 述 了 面对 面对 ； 法 的主 要 步骤 ， 隹方 最新 结 果报 导 ， 一种 特 殊 开 发 的 对 ； 用 隹系统 获得 了
Ａｂ ｔ ａ ｔ ｒ ｃ ｓ ｎ ａ ｉｎ ｄ ｗａ ｅ ｏ ｄ ｎ ｓ ａ ｋ ｙ ｅ ａ ｌ ｇ ｔｃ ｎ ｌ ｇ ｏ Ｄ ｎ ｅ ｃ ｎ ｅ ｔ， ｆ ｒ ｓｒ ｃ ：Ｐ ｅ ｉｉ ｌ ｅ ｆ ｒ ｂ ｎ ｉ ｇ ｉ ｅ ｎ ｂ ｉ ｅ ｈ ｏ ｏ ｙ ｆ ｒ ３ Ｉ ｔｒ ｏ ｎ ｃ ｓ ｗａ ｅ ｏ ｇ ｎ
１ ｍ 的对 准精 度 。设 备 主要 是 为 圆片对 圆片 的对 准和 键合 而设计 。 ｌ Ｊ 关键 词： Ｄ 互连 ； 准 ； 合 ； ＭＳ ３ 对 键 ＭＥ ；封 装 ；多层叠 加 中 图分 类号 ： Ｎ３ ５９ Ｔ ０． ４ 文献 标 识码 ： 文 章编 号 ：０ ４４ ０ （０ ６ ０ —０ ００ Ａ １０ —５ ７ ２ ０ ） ７０ ２ —４
（． Ｖ Ｇ ｏ ｐＵＳＩｃ，７ １ ．ｎｖ ｒｔ ｒ ｅ ｕｔ ３ ０Ｐ ｏｎｘ Ａ ５ ３ ， Ａ； １Ｅ ｒｕ ， ． ０ ＥＵ ｉｅ ｉ Ｄ ｖ ， ｉ ０ ｈ ｅｉ， Ｚ８０ ４ＵＳ ｎ ３ ｓｙ ｉ Ｓ ｅ
２ Ｖ ｏ ｐ Ｓ ． ｏｉ ， 一 ７ ０ Ｓ ｈ ｅ ｉｇＡ ｓ ｉ） Ｇｒｕ ， Ｆ ｒ ｎ Ａ ４ ８ ｃ ａ ｒ ｎ ， ｕ ｔ ａ Ｅ ｔｌ ａ ｄ ｒ