基于FPGA的LCD1602动态显示

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lcdplay is
port(clk,reset,lcdopen:in std_logic;
lcd_on,lcd_en,lcd_rw:out std_logic;
LCD_Data:out std_logic_vector(8 downto 0)
);
end lcdplay;
architecture zw of lcdplay is
signal clk1hz:std_logic;
--signal cnt2:std_logic_vector(4 downto 0);
type statetype is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23);
signal pstate,nstate:statetype;
begin
lcd_on<=lcdopen;
process(clk)
variable cnt1:integer range 0 to 4999999;
begin
if rising_edge(clk) then
if cnt1=4999999 then
cnt1:=0;
else
cnt1:=cnt1+1;
end if;
if cnt1<2500000 then
clk1hz<='1';
else
clk1hz<='0';
end if;
lcd_en<=clk1hz;
end if;
end process;
--process(clk1hz)
-- begin
-- if Reset='0'then
-- cnt2<="00000";
--- elsif rising_edge(clk1hz) then
-- if cnt2<"10000" then
-- cnt2<=cnt2+1;
-- else
-- cnt2<="00000";
--end if;
--end process;
process(pstate,reset)
begin
--lcd_en<=clk1hz;
if reset='1' then
nstate<=s0;
LCD_Data<="000000001";
else
case pstate is
when s0=>
lcd_rw<='0';
nstate<=s1;
LCD_Data<="000111000";--/*设置8位格式,2行,5*7*/ ,顺序2,3的要求
when s1=>
nstate<=s2;
LCD_Data<="000001100"; --/*整体显示,关光标,光标闪烁/ ，顺序4的要求
when s2=>
--lcd_rw<='0';
nstate<=s3;
LCD_Data<="000000001";--清屏，顺序5的要求
when s3=>
--lcd_rw<='0';
nstate<=s4;
LCD_Data<="000000110"; --/*显示移动格式，看最后两位，10表示光标右移，顺序6的要求
when s4=>
--lcd_rw<='0';
nstate<=s5;
LCD_Data<="010000100";--设定显示的位置在01H+80H，即显示屏第一行第01H个位置，顺序7的要求
when s5=>
nstate<=s6;
LCD_Data<="101011010";--Z
when s6=>
--lcd_rw<='1';
nstate<=s7;
LCD_Data<="101101000";--上一步基础上地址加一，显示字符h when s7=>
--lcd_rw<='1';
nstate<=s8;
LCD_Data<="101100001";--a
when s8=>
nstate<=s9;
LCD_Data<="101101110";--n
when s9=>
nstate<=s10;
LCD_Data<="101100111";--g
when s10=>
nstate<=s11;
LCD_Data<="101110111";--w
when s11=>
nstate<=s12;
LCD_Data<="101100101";--e
when s12=>
nstate<=s13;
LCD_Data<="101101001";--i
when s13=>
lcd_rw<='0';
LCD_Data<="011000011";
nstate<=s14;
when s14=>
nstate<=s15;
LCD_Data<="100110010";--2
when s15=>
nstate<=s16;
LCD_Data<="100110000";--0
when s16=>
nstate<=s17;
LCD_Data<="100110001";--1
when s17=>
nstate<=s18;
LCD_Data<="100110001";--1
when s18=>
nstate<=s19;
LCD_Data<="100110001";--1
when s19=>
nstate<=s20;
LCD_Data<="100110001";--1
when s20=>
nstate<=s21;
LCD_Data<="100110001";--1
when s21=>
nstate<=s22;
LCD_Data<="100110010";--2
when s22=>
nstate<=s23;
LCD_Data<="100110000";--0
when s23=>
nstate<=s0;
LCD_Data<="100111000";--0 end case;
end if;
end process;
process(clk1hz,nstate)
begin
if clk1hz'event and clk1hz='1' then
pstate<=nstate;
end if;
end process;
end zw;。