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怎么看数据手册

怎么看数据⼿册1 数据⼿册要点 (1)1.1 操作时序 (1)1.2 典型应⽤电路 (2)2.3 AD0804操作时序图 (3)2.3.1 AD0804启动转换⼯作时序 (3)2.3.2 读取AD数据时序图 (4)2.4 AD0804例程说明 (5)1 数据⼿册要点1.1 操作时序图1 MAX531的操作时序图2图1中的⽹格状部分（图2）为⽆效数据，对芯⽚的操作不起作⽤。

从图1可以看出，数据必须在时钟脉冲SCLK之前维持t DS时间，然后在SCLK 上升沿到来时，经SCLK保持t DH时间段，才能送⼊MAX531。

1.2 典型应⽤电路图3数据⼿册：特性说明。

DA ：转换位数、转换速率、位数、串⼝并⼝。

2.3 AD0804操作时序图Latch ：锁存2.3.1 AD0804启动转换⼯作时序图2-7如上图时序图所⽰：START CONVERSION “开始转换”，当给CS ____低脉冲时，AD 开始转换。

在CS ____为低电平期间，给WR ______⼀个低脉冲，tW(WR ______)L （100ns ）为WR ______低脉冲所维持的最短时间，如果WR ______维持的时间低于tW(WR ______)L ，则AD 接收不到WR ______信号。

如选⽤12MHZ 单⽚机，⼀个指令周期为1µs （=1000ns ）,单⽚机向AD 写信号WR ——的tW(WR ______)L 的时间为1000ns ，即使单⽚机给低电平之后⽴刻给⾼电平，这时也已经过去了1000ns ，对单⽚机的操作影响甚⼩。

CPLD 为门电路，内部操作速度较快，⼀般为3-7ns, tW(WR ______)L 维持的时间会对CPLD 的操作产⽣影响。

FPGA 操作时间也⽐100ns ⼩的多，故⽽在操作FPGA 或CPLD 时要考虑tW(WR ______)L 。

在WR ______变为⾼电平之后，在期间，实际内部转换特性曲线（ACTUAL INTERNAL STATUS OF THE CONVERTER ）“NOT BUSY ”状态，AD 未开始转换。

怎么看数据手册上的封装pdf

新入电子行业之怎么看datasheet上的封装尺寸作者：瑞生（微信：253057617）新入电子行业，做电路板就需要画封装，封装？实际上就是元器件在电路板上的样子，比如下面电路板，那个上下左右各12个引脚的地方（U1），就是用来焊接封装名称为LQFP48的芯片的。

它旁边的那个两个引脚的(C10),就是用来焊接一个0603封装的电容的。

这下你就知道什么是封装了吧？如上图各种封装，如果你画的差上几个毫米，那元器件就焊不上去了，所以我们要知道这些元器件的引脚是多粗、引脚和引脚的间距是多大等。

而这些数据，都在芯片的数据手册datasheet上。

封装尺寸图一般都在数据手册的最后面，你可以打开一个找找先。

如下图所示是一个SOIC-8封装的芯片封装尺寸图：图中，左上半部分是芯片的外观尺寸，把各个尺寸用字母ABC等标出来，然后就可以看右上半部分的表格，查看尺寸了。

图中下半部分就是厂家给出的封装建议尺寸，我们可以直接照着它给出的尺寸画封装。

封装的英文名称为Footprint，元器件的尺寸有两种单位，一种是毫米mm，一种是mil。

几乎所有的封装，都用两种单位来表示，如上图下半部分厂家给出的尺寸所示，横线上面的是mm，下面的是英尺inch，1英尺等于1000mil。

我们在软件中画尺寸的时候，可以用mm，也可以用mil，一般我们使用mm。

我们把上图中的表格放大看一下，如下图：图中，MILLIMETERS就是毫米，INCHES就是英尺，MIN是最小值，MAX是最大值，之所有最大最小值，是因为生产工艺肯定会有公差的存在。

如果厂家没有给出建议的封装尺寸图，我们就需要看上这个图画，我们取最大值和最小值之间的一个数就可以，一般取平均值。

芯片数据手册查询

芯片数据手册查询芯片数据手册是对特定芯片的详细技术规格和性能进行介绍的文档。

它通常包含了芯片的电气特性、引脚定义、功能描述、工作原理、时钟频率、电源电压和电流、温度范围、封装形式等技术信息。

芯片数据手册对于工程师、设计师、程序员和系统集成商来说都是非常重要的参考文献，它们通过手册可以了解芯片的各项性能指标，从而设计出更加高效、可靠的电路和系统。

在查询芯片数据手册时，我们需要考虑以下几个方面：1. 芯片型号和制造商：首先要确定要查询的芯片的型号和制造商，一般来说芯片的型号已经在芯片上标注，而制造商的信息通常在芯片的封装上或产品标签上可以找到。

有了这些基本信息，我们就可以在芯片制造商的官方网站上找到相关的数据手册。

2. 搜索引擎：如果找不到芯片的官方网站或没有账号登录权限，可以通过搜索引擎来找到其他网站或论坛上分享的芯片数据手册。

在搜索引擎中输入芯片型号和关键字"datasheet"可以获得更精确的搜索结果。

3. 可靠性和专业性：在查询芯片数据手册时，要特别注意选择可靠的来源。

官方网站和知名的电子元器件分销商是最常用的可靠来源。

在一些论坛或社区上分享的芯片手册可能会有差错或不准确的信息，因此需要对这些信息进行鉴别和验证。

在获得芯片数据手册后，我们可以根据实际需求查询其中的相关信息。

以下是一些常见的查询内容：1. 芯片功能和特性：手册中一般会有详细的功能描述和特性介绍，包括各个引脚的功能和电气特性。

我们可以查阅这些信息了解芯片的功能和性能。

2. 电气特性：芯片的电气特性包括输入电压范围、输出电压范围、工作电流等。

这些信息对于设计电路和保证系统正常工作非常重要。

3. 最大时钟频率和工作温度范围：芯片的最大时钟频率决定了它的性能上限，而工作温度范围则决定了它的工作环境适应能力。

这些信息对于系统设计和部署非常重要。

4. 引脚分配和封装形式：芯片的引脚分配和封装形式对于PCB设计和组装非常关键。

如何阅读规格书

How to Read a Datasheetconcisely tell you everything you need to know about the device, a common 555 timer chip (the duct-tape of the electronics hobbyist). Most datasheets for ICs follow the same general layout.You don’t have to understand everything in a datasheet. There’s a lot of information that might not be of any use to you. The annotations that follow try to point out parts of the datasheet that you should pay particular attention to.Where do you find datasheets? Nowadays you can find almost any datasheet on the internet, often in PDF (Acrobat) form. For example, the LM555 datasheet from National Semiconductor is on their website at .LM555TimerGeneral DescriptionThe LM555is a highly stable device for generating accuratetime delays or oscillation.Additional terminals are provided for triggering or resetting if desired.In the time delay mode of operation,the time is precisely controlled by one external re-sistor and capacitor.For astable operation as an oscillator,the free running frequency and duty cycle are accuratelycontrolled with two external resistors and one capacitor.Thecircuit may be triggered and reset on falling waveforms,and the output circuit can source or sink up to 200mA or driveTTL circuits.Features n Direct n Timing n Operates n Adjustable n Output n Output n Temperature n Normally n Available Applicationsn Precision n Pulse n Sequential DS007851-1LM555Timerespecially if Preliminary or Advance. Check the date!总会有一个日期。

怎样阅读datasheet

面对英文的长篇的芯片datasheet，有时感到无从插手，小结一下谨以自勉并分享。

1.General Description讲解基本功能，精炼而丰富，值得细细阅读。

（必要）2.Features讲解了使用条件、封装等，有一些有用信息，也要看一看。

这两部分认真看完，就对芯片基本功能较为了解。

3.Applications讲解用途，太粗略了，看不看得吧。

4.Pin Configuration与Pin Description讲解管脚定义和连接方法，画PCB，焊接芯片，调试电路都要用到。

（必要）5.Typical Operating Circuit结合Applications Information一起看，主要讲电路设计，有时间细看一下，对于电路设计和电路调试都很有用。

（必要）6.ABSOLUTE MAXIMUM RATINGS讲解绝对电气特性，也就是极限工作条件，也要细看，以防损毁芯片。

（必要）7.ELECTRICAL CHARACTERISTICS讲解电气特性，包括静态特性和动态特性，信息量巨大，最好用什么看什么，看一项就把它看明白，切忌囫囵吞枣。

（必要，要有针对性的看）8.Typical Operating Characteristics通过图表的方式讲解芯片性能，虽直观，但是内容一般比较广泛且深奥，看明白了也不一定能用得上，我也只是大致看看，电路调试时有时看看波形是否与图表中的一致，但都是象征性的了解了解，这部分尚需深入学习。

9.Detailed Description讲解一些芯片更细节的东西，也有一些有用内容，有时间就看看。

10.Package Information讲解封装特性，PCB设计常用。

其中有几部分对于较浅层次的电路设计电路调试是最为有用的，已经标注了“（必要）”。

datasheet多读几遍，对学习电路设计挺有帮助，引用斌哥一句话结尾：把一种电路仔细看的明明白白，要比一知半解知道多种电路有用得多！PS：阅读过程中把datasheet中不认识的英文单词记下来，慢慢积累下来，阅读速度就上来啦。

怎样读芯片数据手册

前言：在网上看到《How to Read a Datasheet》这篇文章，觉得不错，对我这种电子菜鸟很有帮助，就把它翻译了一下，希望能对大家有点用处。

我的E文水平有限，在《金山词霸》的帮助下翻译了此文，所以肯定存在很多问题，如果你发现什么问题，请一定指出，在此先谢谢大大家。

Email:case1234@Fire2006-9-7How to Read a DatasheetPrepared for the WIMS outreach program5/6/02, D. GroverIn order to use a PIC microcontroller, a flip-flop, a photodetector, or practically any electronic device, you need to consult a datasheet. This is the document that the manufacturer provides telling you• the typical device performance• minimum and maximum requirements and characteristics• what you can do to the device without harming it• suggested uses and hintsManufacturers want you, the designer, to have a successful experience with their device. They are trying to be helpful. They don’t always succeed. The datasheet on the following pages is a relatively good datasheet. It tries to concisely tell you everything you need to know about the device, a common 555 timer chip (the duct-tape of the electronics hobbyist). Most datasheets for ICs follow the same general layout.You don’t have to understand everything in a datasheet. There’s a lot of information that might not be of any use to you. The annotations that follow try to point out parts of the datasheet that you should pay particular attention to.Where do you find datasheets? Nowadays you can find almost any datasheet on the internet, often in PDF (Acrobat) form. For example, the LM555 datasheet from National Semiconductor is on their website at .What is the LM555? The LM555 is a timer chip that uses external resistors and capacitors to generate either a single pulse of a certain duration, or a continuous sequence of pulses with a variety of pulse widths possible. Because it is a very general purpose collection of functional blocks such as comparators, a flip-flop, internal voltage divider, high power output stage, and so on, a number of different timing-related functions are possible. Entire books have been written about the 555, though it is often used when another IC would work better. (See for example the CD4538 timer chip.)怎样读数据手册写给WIMS推广计划5/6/02, D. Grover为了使用PIC微控制器、触发器、光电检测器或者其它任何电子器件，你需要参考datasheet。

如何彻底读懂并理解MOSFET的Datasheet

APPENDIX AEstimating MOSFET Parameters from the Data Sheet(Equivalent Capacitances, Gate Charge, Gate Threshold Voltage,Miller Plateau Voltage, Internal Gate Resistance, Maximum Dv/Dt)In this example, the equivalent C GS , C GD , and C DS capacitances, total gate charge, the gate threshold voltage and Miller plateau voltage, approximate internal gate resistance, and dv/dt limits of an IRFP450MOSFET will be calculated. A representative diagram of the device in a ground referenced gate drive application is pictured below.V The following application information are given to carry out the necessary calculations:V DS,OFF =380V the nominal drain-to-source off state voltage of the device.I D =5A the maximum drain current at full load.T J =100°C the operating junction temperature.V DRV =13V the amplitude of the gate drive waveform.R GATE =5Ωthe external gate resistance.R LO =R HI =5Ωthe output resistances of the gate driver circuit.A1.CapacitancesThe data sheet of the IRFP450 gives the following capacitance values:Using these values as a starting point, the average capacitances for the actual application can be estimated as:Equations:Numerical Example:offDS,spec DS,spec OSS,ave OSS,off DS,spec DS,spec RSS,ave RSS,V V C 2C V V C 2C ⋅⋅=⋅⋅=369pF 380V25V720pF 2C 174pF 380V 25V340pF 2C ave OSS,ave RSS,=⋅⋅==⋅⋅=The physical capacitor values can be obtained from the basic relationships:aveRSS,ave OSS,DS RSS ISS GS ave RSS,GD C C C C C C C C −=−==195pF174pF 369pF C 2260pF 340pF 2600pF C 174pFC DS GS GD =−==−==Notice that C GS is calculated from the original data sheet values. Within one equation, it is important to use capacitor values which are measured under the same test conditions. Also keep in mind that C GS is constant, it is not voltage dependent. On the other hand, C GD and C DS capacitors are strongly non-linear and voltage dependent. Their highest value is at or near 0V and rapidly decreasing as the voltage increases across the gate-to-drain and drain-to-source terminals respectively.A2.Gate chargeThe worst case gate charge numbers for a particular gate drive amplitude, drain current level, and drainoff state voltage are given in the IRFP450 data sheet.Correcting for a different gate drive amplitude is simple using the typical Total Gate Charge curve as illustrated on the left.Starting from the 13V gate-to-source voltage on the left hand side, find the corresponding drain-to-source voltage curve (interpolate if not given exactly), then read the total gate charge value on the horizontal axes.If a more accurate value is required, the different gate charge components must be determined individually. The gate-to-source charge can be estimated from the curve on the left, only the correct Miller plateau level must be known. The Miller charge can be calculated from the C RSS,AVE value obtained in A1. Finally, the over drive charge component – raising the gate-to-source voltage from the Miller plateau to the final amplitude – should be estimated from the graph on the left again.13V122nCA3.Gate threshold and Miller plateau voltagesAs it was already shown in A2, and will be demonstrated later, several MOSFET switching characteristic are influenced by the actual value of the gate threshold and Miller plateau voltages. In order to calculate the Miller plateau voltage, one possibility would be to use the gate-to-source threshold voltage (V TH ) and transconductance (g fs ) of the MOSFET as listed in the data sheet.Unfortunately, the threshold is not very well defined and the listed g fs is a small signal quantity. A more accurate method to obtain the actual V TH and Miller plateau voltages is to use the Typical Transfer Characteristics curves of the data sheet.From the same temperature curve, pick two easy to read points and note the corresponding drain currents and gate-to-source voltages. Select the drain current values to correspond to vertical grid lines of the graph, that way the currents can be read accurately. Then follow the intersections to the horizontal axes and read the gate-to-source voltages.Starting with the drain currents will result in higher accuracy because the gate-to-source voltage is on a linear scale as opposed to the logarithmic scale in drain current. It is easier to estimate Vgs1 and Vgs2on the linear scale therefore the potential errors are much smaller.For this example, using the 150°C curve:5.67VV 20A I 4.13V V 3A I GS2D2GS1D1====The gate threshold and Miller Plateau voltages can be calculated as:()()()KI V V V V I K I I I V I V V V V K I V V K I LOADTHMiller GS,2TH GS1D1D1D2D1GS2D2GS1TH 2TH GS2D22TH GS1D1+=−=−⋅−⋅=−⋅=−⋅=() 4.413V 3.1695A3.157V V 3.1693.157V4.13V 3AK 3.157V3A 20A 3A5.67V 20A 4.13V V Miller GS,2TH =+==−==−⋅−⋅=I D1I D2V GS1V GS2Typical Transfer CharacteristicsThese values correspond to 150°C junction temperature, because the 150°C curve from the Typical Transfer Characteristics was used. Due to the substantial temperature coefficient of the threshold voltage, the results have to be corrected for the 100°C operating junction temperature in this application.The gate threshold voltage and the Miller plateau voltage level must be adjusted by:()TCC 150T ∆V J ADJ ⋅°−=()0.35VC V 0.007C 150C 100∆V ADJ +=÷øöçèæ°−⋅°−°=A4.Internal gate resistanceAnother interesting parameter is the internal gate mesh resistance (R G,I ), which is not defined in the data sheet. This resistance is an equivalent value of a distributed resistor network connecting the gates of the individual MOSFET transistor cells in the device. Consequently, the gate signal distribution within a device looks and behaves very similar to a transmission line. This results in different switching times of the individual MOSFET cells within a device depending on the cells distance from the bound pad of the gate connection.The most reliable method to determine R G,I is to measure it with an impedance bridge. The measurement is identical to the ESR measurement of capacitors which is routinely carried out in the lab. For this measurement the source and drain terminals of the MOSFET are shorted together. The impedance analyzer should be set to R S -C S or if it is available R S -C S -L S equivalent circuit to yield the component values of the equivalent gate resistor, R G,I , the MOSFET’s input capacitance, C ISS and the series parasitic inductance of the device, all connected in series.For this example, the equivalent component values of an IRFP450 were measured by an HP4194impedance analyzer. The internal gate resistance of the device was determined as R G,I =1.6Ω. The equivalent inductance was measured at 12.9nH and the input capacitance was 5.85nF.A5.dv/dt limitMOSFET transistors are susceptible to dv/dt induced turn-on only when their drain-to-source voltage rises rapidly. Fundamentally, the turn-on is caused by the current flowing through the gate-drain capacitor of the device and generating a positive gate-to-source voltage. When the amplitude of this voltage exceeds the gate-to-source turn-on threshold of the device, the MOSFET starts to turn-on. There are three different scenarios to consider.First, look at the capacitive divider formed by the C GD and C GS capacitors. Based on these capacitor values the gate-to-source voltage can be calculated as:GD GS GDDS GS C C C V V +⋅=If V GS <V TH , the MOSFET stays off. The maximum drain-to-source voltage to ensure this can be estimated by:GDGDGSTH MAX DS,C C C V V +⋅≈This mechanism provides full protection against dv/dt induced turn-on in low voltage applications,independent of the internal gate resistor and the external drive impedances.For higher voltage applications, it is desirable to determine the natural dv/dt limit of the MOSFET. This characteristic corresponds to the maximum dv/dt the device can withstand without turning on in an ideal situation where the external drive impedance is zero. This is signified by the shorted gate-source connection in the schematic diagram on the right.The turn-on is initiated by the voltage dropacross R G,I due to the charge current of C GD .Accordingly, the natural dv/dt limit can be calculated by:GDI G,TH LIMIT -N C R V dt dv⋅=This number is significant in evaluating the suitability of a device for a specific application where the turn-off dv/dt is forced by other components in the circuit. These applications include synchronous rectifiers, resonant mode and soft-switching power converters.The third calculation describes the resulting dv/dt limit of the drain-to-source voltage waveform based on the parasitic components of the MOSFET device and the characteristics of the gate drive circuit.To avoid turn-on, the gate-to-source voltage must stay below the turn-on threshold voltage:()GDLO GATE I G,TH LIMIT C R R R V dt dv⋅++=It is important to emphasize again that the threshold voltage of the MOSFET transistor changes significantly with temperature. Therefore, the effect of high junction temperature must be taken into effect. For the particular example using the IRFP450 type transistor at 100°C operating junction temperature the calculations yield the following limitations:Case 1. No dv/dt induced turn-on takes place below the drain-to-source voltage of:()GD GD GSADJ TH MAX DS,C C C ∆V V V +⋅+=()26.82V 340pF 2600pF0.35V 3.157V V MAX DS,=⋅+=Case 2. The natural dv/dt limit of the IRFP450 is:GDI G,ADJ THLIMIT -N C R ∆V V dt dv⋅+=µskV6.4340pF 1.6Ω0.35V 3.157V dt dv LIMIT -N =⋅+=Case 3. The in-circuit dv/dt limit including the effect of the driver’s output impedance is:()GD LO GATE I G,ADJ TH LIMIT C R R R ∆V V dt dv ⋅+++=()µsV889340pF 5Ω5Ω1.6Ω0.35V 3.157V dt dv LIMIT =⋅+++=Calculating Driver Bypass Capacitor ValueMOSFET drivers must be operated from a low impedance voltage source to achieve high switching speed and reliable operation. To provide this virtual voltage source, the bias line of the drivers must be locally bypassed by very good quality, high frequency capacitors. In most applications this capacitance is realized by low impedance, high frequency, multilayer ceramic capacitors. Half of the success in bypassing can be ensured by the proper location of the bypass capacitors and the driver itself. Some of the most important rules of proper gate drive design are highlighted in the example below:• The driver should be close to the device it is driving. Significant distance can be tolerated between the PWM controller and the MOSFET driver with careful layout design. Even though there is no high current between the output of the PWM IC and the input of the driver, relatively wide printed circuit board traces can reduce the parasitic interconnection inductance, thus providing lower loop impedance and better noise immunity.• It is also important to separately bypass the individual noise sources, i.e. the power stage, the PWM controller and the driver both have their own respective bypass capacitors. The three shaded loop areas must be minimized.During turn-on the gate current flows through the bypass capacitor of the driver, while during turn-off the high frequency bypass capacitor of the power stage must provide a path to charge the C GD capacitor of the MOSFET.In this numerical example an IRFP350 MOSFET is driven by a Micrel MIC4423 driver. The driver’s quiescent current I Q,HI with a high input, is 2.5mA. When the input is low the quiescent current is negligible. The switching frequency is 100kHz and the maximum duty ratio of the PWM signal is 0.7.The gate is driven by a 12V signal, and the off state voltage of the device is approximately 300V.From these operating conditions the total gate charge can be estimated as 115nC. A 5% percent ripple voltage across the bypass capacitor is acceptable, and a 12V bias would allow 0.6V ripple voltage. The equation to calculate the minimum bypass capacitor value is:∆V Q f D I C G DRV MAX HI Q,BYPASS +⋅=221nF 0.6V 115nC 100kHz 0.72.5mA C BYPASS =+⋅=The effect of switching frequency on the bypass capacitorvalue is depicted in the figure on the right. At high frequency,the gate charge determines the minimum bypass capacitor,thus the curve approaches an asymptotic minimum value. At low operating frequencies the quiescent current of the driver commands the minimum capacitor size. Note that this ripple component depends on the duty ratio of the PWM signal.For this calculation, the worst case situation (D=0.7) was considered.V IN1010010000.20.30.40.5Switching Frequency [kHz]M i n i m u m B y p a s s C a p a c i t o r [µF ]Bootstrap Bypass Capacitor ExampleIn this example an IR2125 high voltage integrated gate driver is employed to drive an IRF1310N transistor in a 48V input buck converter. The corresponding schematic diagram is given below.VV BIAS V OUT V DRV Let’s assume the following application parameters:V IN,MAX =65V the maximum steady state input voltage.V DRV =12V the bias voltage for the high side driver and the gate drive amplitude.∆V BST =0.5V the steady state ripple voltage across C BST .∆V BST,MAX =3V the maximum voltage droop across C BST before the driver goes to under voltage lockout or the gate drive amplitude becomes insufficient.f DRV =100kHz the switching frequency.D MAX =0.9the maximum steady state duty ratio at minimum input voltage – the controller does not limit the maximum duty cycle in this example.t OFF,TR =400µs transient off-time – at sudden removal of the load, the MOSFET stays off for this time interval.t ON,TR =200µstransient on-time – at sudden increase of the load current, the controller keeps the MOSFET on for this time interval to build up the output inductor current.The circuit components are characterized by:Q G =85nC the total gate charge of the IRF1310 @ V DRV =12V and V DS =65V.R GS =5.1k Ωthe gate-to-source pull down resistor value.I R =10µA leakage current of D BST @ V IN,MAX and T J =80°C.V F =0.6V forward voltage drop of D BST @ 0.1A and T J =80°C.I LK =0.13mA leakage current of the level shifter @ V IN,MAX and T J =100°C.I QBS =1mAquiescent current of the floating driver.First, consider the steady state operation of the driver. Based on the ripple budget of 0.5V and the amount of charge consumed from the bootstrap capacitor, a minimum capacitance value can be established:BSTG DRVMAX GS F DRV QBS LK R BST,1∆V Q f D R V V I I I C +⋅÷÷øöççèæ−+++=Substituting the numerical values yields the minimum bootstrap capacitor value for steady state operation:231nF 0.5V85nC 100kHz 0.95.1k Ω0.6V 12V 1mA 0.13mA A 10µC BST,1=+⋅÷øöçèæ−+++=For the transient conditions calculate the capacitor values based on the maximum voltage droop. When the switch has to stay off for an extended period of time, the output inductor current decays to zero and the source of the main switch settles at the output voltage. The bootstrap diode is reverse biased and the bootstrap capacitor has to keep the floating driver alive. Moreover, at the end of the idle period, C BST still has to provide the gate charge to turn-on the MOSFET. Accordingly, the required capacitor value is:MAXBST,GTR OFF,GS F DRV QBS LK R BST,2∆V Q t R V V I I I C +⋅÷÷øöççèæ−+++=Using the actual application parameters:nF478V3nC85µs 400k Ω1.5V 6.0V 12mA 1mA 13.0µA 10C 2BST,=+⋅÷øöçèæ−+++=The last calculation is carried out to check whether the switch can be turned on continuously for the desired 200 microseconds transient on time. The long on period will be followed by a guaranteed off-time when the bootstrap capacitor can be replenished. The bootstrap capacitor must hold enough energy to support the quiescent and leakage currents only as indicated in the expression below:MAXBST,TRON,GS F DRV QBS LK R BST,3∆V t R V V I I I C ⋅÷÷øöççèæ−+++=With the given numerical values:nF 225V3µs200k Ω1.5V 6.0V 12mA 1mA 13.0µA 10C 3BST,=⋅÷øöçèæ−+++=To fulfill all three requirements, the highest capacitor value (C BST =470nF) should be selected.The high side driver IC must be bypassed not only by the bootstrap capacitor, but also by another ground referenced capacitor as indicated in the schematic diagram. C DRV provides the high peak charge current to replenish the energy taken from C BST during the preceding on-time of the main MOSFET. If C DRV >> C BST , the bootstrap capacitor can be recharged to the full V DRV level. Usually, C DRV is an order of magnitude larger capacitance than C BST . When selecting the value of the low side bypass capacitor,primarily the steady state operation should be considered. Accordingly,BST,1DRV C 10C ⋅≈, which requires C DRV = 2.2µF.APPENDIX DCoupling Capacitor and Transient Settling Time CalculationIn this example the coupling capacitor and gate-to-source resistor value of an AC coupled gate drive circuit will be calculated. The design goal is to provide a 3V negative bias for the MOSFET during its off time. The application circuit is shown below:V DRV V INThe following application information is given:dV IN /dt=200V/ms the maximum dv/dt of the input voltage during power up, limited by the combined effect of the inrush current limiting circuit and the input energy storage capacitor.C GD,0=1nF the maximum gate-to-drain capacitance of the MOSFET read from the data sheet at 0V drain-to-source voltage (worst case start-up condition).V TH =2.7V the gate-to-source turn-on threshold @ T A,MAX .V DRV =15V the supply voltage of the PWM controller, i.e. the gate driver’s bias voltage.f DRV =100kHz the switching frequency.D MAX =0.8maximum duty ratio, limited by the PWM controller to reset the transformer.V CL =3V the negative bias amplitude.∆V C =1.5V maximum allowable ripple of the coupling capacitor.Q G =80nC total gate charge of the MOSFET .τ=100µstransient time constant for the coupling capacitor voltage (V C ). This is the start-up time constant as well to establish the initial value of V C .The design starts by determining the maximum value of the gate pull down resistor. During power-up,R GS must be low enough to keep the MOSFET off. When the voltage rises across the drain-source terminal, the C GD capacitor is charged and a current proportional to dV IN /dt flows through R GS . The MOSFET stays off if the voltage drop across R GS remains below the gate threshold. Therefore, the maximum allowable R GS value is:dtdV C V R INGD,0THMAX GS,⋅=13.5k ΩsV2000001nF 2.7V R MAX GS,=⋅=The next step is to find the common solution for the required time constant and ripple voltage. The two equations are:D(D)V D V f ∆V f Q C R C C DRV DRV C DRVG C GSC τττ⋅+⋅−⋅⋅⋅⋅=⋅=where V C (D) is the coupling capacitor voltage as a function of the duty ratio. The second equation can be evaluated right away since all parameters are defined. In general, V C (D)=D ⋅V DRV if the clamp circuit is not used, and the expression has a local maximum at D=0.5, which gives the minimum coupling capacitor value. In this application, the coupling capacitor voltage is limited to 3V by the zener clamp.Thus for D>0.2, the coupling capacitor voltage is constant, and V C =3V. Consequently, the maximum value of the second equation is not at D=0.5, but rather at the maximum duty cycle, D MAX .Before calculating C C , another important limitation should be pointed out. In order to arrive at a meaningful positive capacitor value, the denominator of the second equation must be positive which sets a limit on the transient time constant. This limit is:()DRVC C DRV MIN f ∆V (D)V VD τ⋅−⋅=This function has a maximum value at D=0.5 if the clamp circuit is not used. With the clamp circuit,D=D MAX will define the fastest possible transient response of the coupling capacitor voltage.Substituting the application parameters and using the appropriate equation for the clamp case yields the following values:()DRVC CL DRV MAX MIN f ∆V V VD τ⋅−⋅=()µs64kHz100V 5.1V 3V 158.0MIN τ=⋅−⋅=()CL DRV MAX DRV C DRVG C V V D f ∆V f Q C ττ−⋅−⋅⋅⋅⋅=()nF148V 3V 158.0kHz 100µs 100V 5.1kHz100µs 100nC 80C C =−⋅−⋅⋅⋅⋅=CGS C R τ=Ω675nF148µs100R GS ==These results are acceptable because τMIN <τ and R GS,MAX >R GS , therefore all conditions are met. The worst case power dissipation of R GS is 173mW at the maximum duty ratio of 0.8. If this value is not acceptable, selecting a longer time constant will increase the pull down resistor value. At the same time the power dissipation and the coupling capacitor value will decrease.The last calculation is to compute the bypass capacitor value. Assuming a maximum of 1V ripple on the bias rail (∆V DRV =1V) the following minimum bypass capacitance value will result:MAXDRVGS DRV CLDRV DRV G DRV D f R ∆V V V ∆V Q C ⋅⋅⋅−+=222nF 0.8100kHz675Ω1V 3V15V 1V 80nC C DRV =⋅⋅⋅−+=APPENDIX EGate Drive Transformer Design ExampleThe gate drive transformers for a phase shifted full-bridge converter will be designed according to the schematic diagram below:V INIn this example, the PWM controller has four high current output drivers on-board. The gate drive transformer design is based on the following application information:f CLOCK =400kHz the clock frequency.f DRV =200kHz the operating frequency of the gate drive transformers.D MAX =0.5maximum duty ratio of the gate drive transformer.V DRV =15Vthe bias voltage of the controller, which is also used to power the output drivers.The first task is to choose the core size. A seasoned designer can pick the right core for the first try based on previous experience. But even then, like all magnetics problem solving, the gate drive transformer design might require a couple of iterations. For this application a Ferroxcube RM5/I core was selected with no airgap. The preferred choice of material is 3C94 because it has the highest permeability and lowest loss at 200kHz from the available selection.Ae=24.8mm 2effective cross section area of the core.Ve=574mm 3effective volume of the core.B SAT =0.35T saturation flux density of the ferrite material @ 100°C.A L =2µH/turns 2equivalent inductance per turns square.B PEAK =0.1T peak flux density in steady state operation. Remember, that during transient operation the transformer’s flux can walk due to uneven duty cycles. Usually, a 3:1 margin is desirable.∆B=0.2Tpeak-to-peak flux density in steady state operation.Check the core loss under these conditions from the data sheet.P V =200kW/m 3effective volumetric power dissipation of 3C94 @ B PEAK =0.1T and 200kHz.(it is more meaningful to convert to 0.2mW/mm 3.)eV CORE V P P ⋅=115mW 574mm mmmW0.2P 33CORE =⋅=The power dissipation of the RM5/I core is 115mW which is acceptable. Next, calculate the primary number of turns according to:DRVe MAX DRV Pf A ∆B D V N ⋅⋅⋅=7.56200kHz24.8mm 0.2T 0.515V N 2P =⋅⋅⋅=turns The next higher full turn is selected, N P =8 turns. Since voltage scaling is not required in this gate drive transformer, the two secondary windings have 8 turns as well. In order to minimize leakage inductance and AC winding resistance, each winding should occupy a single layer only. The following data is needed to execute the winding design:W W =4.7mm the winding width from the data sheet of the coil former.MLT=24.9mmthe average length of turn also from the coil former data sheet.Considering that at the termination N+1 wires are side by side, the corresponding wire diameter is:1N W d P W W +=20.5mils 0.52mm 94.7mmd W ===The closest smaller diameter wire size according to the American Wire Gauge table is #25 and its characteristic data is:d W =0.0199mils heavy built (double isolated) nominal diameter. (0.0199mils=0.506mm)ρW =32.37Ω/1000ft.normalized wire resistance. (32.37Ω/1000ft =0.1062m Ω/mm)The DC winding resistance is:WP DC W,ρMLT N R ⋅⋅=21.2m Ωmmm Ω0.106224.9mm 8R DC W,=⋅⋅=Next, check the AC resistance based on Dowell’s curves according to the following steps:DRVPEN f 7.6D =cm017.02000006.7D PEN ==PEN WD d 0.83Q ⋅=2.470.17mm 0.506mm 0.83Q =⋅=Entering Dowell’s graph at Q=2.5, the single layer curve gives an R AC /R DC =3 ratio, thus the AC resistance of the winding is R AC =3⋅21.2m Ω=63.6m Ω, which is quite acceptable.The last step is to calculate the magnetizing inductance and current values:2L M N A L ⋅=µH 1288turnsµH 2L 22M =⋅=DRVM MAXDRV M P M,f L D V 212∆I I ⋅⋅⋅==mA 146kHz200µH 1285.0V 1521I M,P =⋅⋅⋅=3D I I MAXP M,RMS M,⋅=60mA 30.5146mA I RMS M,=⋅=Based on the RMS value of the magnetizing current, the wire loss is:AC 2RMS M,W R I P ⋅=0.2mW63.6m Ω(60mA)P 2W =⋅=This result demonstrates that power dissipation in the winding is not an issue in the gate drive transformer. The high magnetizing inductance and low winding resistance are the most critical design parameters to achieve low droop in the gate drive waveform. Also notice that copper loss is based purely on AC resistance, because in an ideal, steady state operation there is no DC current in the windings.Finally, the winding arrangement of the transformer is shown below. The primary is near the center post,then the low side, and the high side windings. All windings are in a single layer. The low side winding is utilized as a natural shield against parasitic capacitive currents between signal ground and the floatingcircuitry.APPENDIX FA Step by Step Design Example of a Ground Referenced and aFloating High Side Gate Driver for an Active Clamp Flyback ConverterThe gate drive design process begins AFTER the power stage is designed and the power components are selected. The simplified final schematic diagram of the active clamp flyback converter is shown below.DCRload85OhmsThe relevant operating parameters are:V DS1,off=V DS2,off=285V the off state drain-to-source voltage of Q1 and Q2. Both transistors areswitching between ground (0V) and V IN+V CLAMP.I D1=2.7A the peak drain current of Q1 at turn-off.T J=100°C the operating junction temperature of the devices.L R=14uH the resonant inductor of the active clamp flyback power stage.The specified driver output impedances and gate drive parameters of the UCC3580-4 are:OUT1OUT2V DRV=15V V DRV=15VD MAX1=0.7D MAX2=0.95f DRV=250kHz f DRV=250kHzR HI1=20ΩR HI2=33ΩR LO1=10ΩR LO2=33ΩThe estimated MOSFET parameters according to the operating junction temperature and based on the methods demonstrated in the previous Appendix’s are:IRFP350IRF740Q G1=135nC Q G2=60nC C GD1=148pF C GD2=71pF C OSS1=391pF C OSS2=195pF R G1,I =1.2ΩR G2,I =1.63ΩV TH1=3.2V V TH2=3.5V V GS1,Miller =4.2V V GS2,Miller =4.8VNext, establish the dv/dt of the external resonant circuit and the dv/dt of the devices. At node A, the resonant inductor, L R , charges and discharges the effective node capacitance. The inductor current barely changes during the short switching action, therefore it can be looked at as a DC current source.The node capacitance and the resulting dv/dt of the power stage are:RD1RES OSS2OSS1R C I dt dvC C C ≈+=µskV4.6586pF 2.7A dt dv 586pF 195pF 391pF C RES R =≈=+=The turn-on dv/dt of the MOSFET and the dv/dt LIMIT to prevent dv/dt induced turn-on assumingR GATE =0Ω are:()GD HI I G,Miller GS,DRV ON C R R V V dt dv ⋅+−=()µs kV 3.4148pF20Ω1.2Ω 4.2V 15V dt dv ON Q1,=⋅+−=()µs kV 4.1571pF33Ω1.63Ω 4.8V15V dt dv ON Q2,=⋅+−=()GDLO I G,TH LIMIT C R R V dt dv⋅+=()µs kV 1.93148pF10Ω1.2Ω 3.2Vdt dv LIMIT Q1,=⋅+=()µs kV 1.421pF733Ω1.63Ω3.5Vdt dv LIMIT Q2,=⋅+=Since the resonant dv/dt is higher than the dv/dt LIMIT calculated for both Q1 and Q2 transistors, a turn-off speed-up circuit must be used in both drive circuits. The selected low side and high side gate drivecircuits are presented below:IRFP350(Low Side Drive)IRF740(High Side Drive)Now, the dv/dt LIMIT numbers must be re-calculated assuming that the drivers’ output impedance is shunted out. Also, pay attention to the 0.7V voltage drop across the pn junction of the Q OFF transistors.µs kV 14148pF 2.10.7V -3.2V dt dv LIMIT Q1,=⋅Ω=µs kV 241pF71.63Ω0.7V-3.5V dt dv LIMIT Q2,=⋅=。

如何看元器件的产品规格书？

如何看元器件的产品规格书？产品规格书也叫做产品DataSheet是电子研发工程师的经常要接触最多的文档之一，当RD 电子工程项目后启动以后，电子工程师针对该产品项目功能进行分解，设计相应的电路，复杂的还需要专门的MCU芯片，从一开始的选型到封装制作再到后期的硬件调试，有的还需要对一些IO接口时序图进行查看时，都需要用到DataSheet，其重要性毋庸置疑。

那么一份元器件数据手册包含的内容那么多，应该如何阅读呢？01概要/综述可能用一至两段的篇幅进行综述,告知器件的特点、建议的应用范围、对加工过程的简要总结(是如何制造的)以及工程师一眼就能瞥见的突出要点。

在元件具有其他的封装形式和工作温度范围时,这部分可能还会包括订购相关须知,但这些信息有时会单独编为一节，在选型的时是必须要仔细阅读的章节。

02规格总览在Data Sheet中的第二个重点，便是系统框图及等效逻辑电路图。

通常包括一张最大额定值表,例如,最大供电电压和最高工作温度、一张热学特性表以及最佳工作条件。

03直流或交流电源下的特性参数这里可以说是器件重要规格的一览表,也是设计主要的参考依据，这里会清楚的标明器件的工作电压范围、工作电流范围，这些参数是用来提醒，设计所要注意的一些细节，比如说：如果设计时所提供的工作电压过高，可能会导致器件损坏；如果电压不足，器件则可能不正常工作或是根本就不工作。

04特性测试图表这里会标示器件在某种特性变化时，所产生的一些相对关系，比如说在固定电压下，在不同的振荡频率工作时，所需要的电流量有何不同?或是芯片在不同温度下工作时，其电压与电流的输出入会有怎样的变化?这都是在特性测试的图表中可以找得到答案。

05典型应用范例告知元器件实际应用笔记，指明了相关电路设计是应当注意的相关信息,例如,器件的物理装配的方法,以及PCB LAY走线布线设计的注意事项,等等。

这一节可能也会给出一个设计示例,即一个使用已知元件工作的电路,它可以用作工程师的设计参考。

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How to Read a DatasheetPrepared for the WIMS outreach program5/6/02, D. GroverIn order to use a PIC microcontroller, a flip-flop, a photodetector, or practically any electronic device, you need to consult a datasheet. This is theto.Where do you find datasheets? Nowadays you can find almost any datasheet on the internet, often in PDF (Acrobat) form. For example, the LM555 datasheet from National Semiconductor is on their website at .LM555TimerGeneral DescriptionThe LM555is a highly stable device for generating accurate time delays or oscillation.Additional terminals are provided for triggering or resetting if desired.In the time delay mode of operation,the time is precisely controlled by one external re-sistor and capacitor.For astable operation as an oscillator,the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor.The circuit may be triggered and reset on falling waveforms,and the output circuit can source or sink up to 200mA or drive TTL circuits.Featuresn Direct n Timing n Operates n Adjustable n Output n Output n Temperature n Normally n Available Applicationsn Precision n Pulse n Sequential DS007851-1有时常规描述（GeneralDescription ）会给出一些其它地方没提到的特性或者用法。

特性（确认电气特性所在的条件以及特殊情况。

通常叫做等效原理图，该原理不是该芯片中必须的，但是该芯片将按照里面的来运作。

它能帮助解释在数据手册中未被描述的行为。

能把这个电路在面包板上搭出来吗？除非您知道那些并未给出参数的晶体管的参数。

总会有一个日期。

数据手册变动，尤其是预备版或者修正版，核对一下日期。

555MLDS007851-3Top ViewNumber Package Marking Media TransportLM555CM LM555CM RailsLM555CMX LM555CM 2.5k Units TapeLM555CMM Z551k Units TapeLM555CMMX Z55 3.5k Units TapeLM555CN LM555CN RailsOrdering Information ）下，可以找到带有完整零件编号的该器件的每个变种列表。

通常开始的几个字母是行业标准或者厂商标识, 接着的是常规标识（“555”）。

后缀通常给出封装类型（贴片安装型或直插型），温度范围（宽范围型，当然也会更贵），速度（快速型，更贵），以及其它各种如功耗，电压范围等等。

--相关器件，如它可替换的，可直接替换的，或者可以被其它替换的器件--提供编程或者配置该器件的信息（寄存器等）--与其它器件之间的连接（包括输入/输出特性）DS007851-4DS007851-19Output Voltage vs.Output Source CurrentDS007851-20Output Voltage vs.Sink CurrentDS007851-21Output Voltage vs.Output Sink CurrentDS007851-22Output Voltage vs.Sink CurrentDS007851-23LM555图表被用来描述那些不容易放在表格里的特性。

通常几个被变化--上文中，供电电流被测量当输入电压被改变时，并同时显示了三种温度下的值。

注意25C是近似室温（77F）的温度。

数据手册的第6页被省略。

The voltage across the capacitor then increases exponen-tially for a period of t=1.1R A C,at the end of which time the voltage equals2/3V CC.The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state.Figure2shows the waveforms gener-ated in this mode of operation.Since the charge and the threshold level of the comparator are both directly propor-tional to supply voltage,the timing internal is independent of supply.During the timing cycle when the output is high,the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least10µs before the end of the timing interval.However the circuit can be reset during this time by the application of a negative pulse to the reset terminal(pin4).The output will then remain in the low state until a trigger pulse is again applied.When the reset function is not in use,it is recommended that be connected to V CC to avoid any possibility of false trig-gering.Figure3is a nomograph for easy determination of R,C val-ues for various time delays.OPERATIONcircuit is connected as shown in Figure4(pins connected)it will trigger itself and free run as a multivibrator.external capacitor charges through R A+R Bthrough R B.Thus the duty cycle may beratio of these two resistors.this mode of operation,the capacitor charges and charges between1/3V CC and2/3V CC.As in the triggered mode,the charge and discharge times,and therefore the quency are independent of the supply voltage.DS007851-5FIGURE1.MonostableDS007851-6CC=5V Top Trace:Input5V/Div.TIME=0.1ms/DIV.Middle Trace:Output5V/Div.A=9.1kΩBottom Trace:Capacitor Voltage2V/Div.=0.01µFFIGURE2.Monostable WaveformsDS007851-7FIGURE3.Time DelayDS007851-8FIGURE4.AstableLM555并非所有的数据手册应用示例都写得这么充分，有时你仅得到一个不完整的原理图。

对于更复杂的器件，例如微控制器，不同的方面可能被放在不同的部分--例如，时钟电路在一处，而复位电路却在另一处。

阅读整个部分确保正确的使用器件以及提供了所有需要的元件。

独立的应用注意。

这个波形有助于电路调试。

8-11页被省略。

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