FPGA--数字时钟(verilog)

因为本人也是刚学习fpga的菜鸟，所以这个程序漏洞很多，仅供参考。

//分频子模块module fenpin (clk,rst_n,en_1s,en_1ms); //产生1s，1ms的分频input clk;input rst_n;output en_1s;output en_1ms;reg[31:0] jishu_1s;reg[15:0] jishu_1ms;parameter cnt_1s =49999999;parameter cnt_1ms =49999;always@(posedge clk or negedge rst_n)beginif(!rst_n)jishu_1s<=32'b0;else if(jishu_1s<cnt_1s)jishu_1s<=jishu_1s+1'b1;elsejishu_1s<=32'b0;endalways@(posedge clk or negedge rst_n)beginif(!rst_n)jishu_1ms<=16'b0;else if(jishu_1ms<cnt_1ms)jishu_1ms<=jishu_1ms+1'b1;elsejishu_1ms<=16'b0;endassign en_1s=(jishu_1s==cnt_1s)? 1'b1 : 1'b0; //1sassign en_1ms=(jishu_1ms==cnt_1ms)? 1'b1 : 1'b0; //1msendmodule//按键控制部分module anjian(clk,rst_n,key1,key2,key1_low,key2_low);input clk;input rst_n;input key1; // 分加input key2; // 分减output key1_low; //按键按下消抖后的标志位output key2_low;reg reg0_key; //key1消抖reg reg1_key;reg reg2_key; //key2消抖reg reg3_key;always @(posedge clk or negedge rst_n)beginif(!rst_n)beginreg0_key <= 1'b1;reg1_key <= 1'b1;endelsebeginreg0_key <= key1;reg1_key <= reg0_key; //根据非阻塞赋值的原理，reg1_key 存储的值是reg0_key 上一个时钟的值endend//脉冲边沿检测法,当寄存器key1 由1 变为0 时，key1_an 的值变为高，维持一个时钟周期wire key1_an;assign key1_an = reg1_key & ( ~reg0_key);always @(posedge clk or negedge rst_n)beginif(!rst_n)beginreg2_key <= 1'b1;reg3_key <= 1'b1;endelsebeginreg2_key <= key2;reg3_key <= reg2_key;endend//脉冲边沿检测法,当寄存器key2 由1 变为0 时，key2_an 的值变为高，维持一个时钟周期wire key2_an;assign key2_an = reg3_key & ( ~reg2_key);reg[19:0] cnt_key1; //计数寄存器always @ (posedge clk or negedge rst_n)beginif (!rst_n)cnt_key1 <= 20'd0; //异步复位else if(key1_an)cnt_key1 <=20'd0; //led1_an=1，按键确认按下，cnt_key1从0开始计数elsecnt_key1 <= cnt_key1 + 1'b1;endreg[19:0] cnt_key2; //计数寄存器always @ (posedge clk or negedge rst_n)beginif (!rst_n)cnt_key2 <= 20'd0;else if(key2_an)cnt_key2 <=20'd0;elsecnt_key2 <= cnt_key2 + 1'b1;end//以下为消抖程序reg reg_low;reg reg1_low;always @(posedge clk or negedge rst_n)beginif (!rst_n)beginreg_low <= 1'b1;endelse if(cnt_key1 == 20'hfffff) //时钟50mhz的话大约计时是20msbeginreg_low <= key1; //led_an=1，按键确认按下，cnt_key从0开始计数，这时候还有消抖动，计数20ms后抖动滤除了此时再锁存一下key1的值end //这时key1的值就稳定了endalways @(posedge clk or negedge rst_n)beginif (!rst_n)reg1_low <= 1'b1;elsereg1_low <= reg_low;endassign key1_low = reg1_low & ( ~reg_low); //当寄存器reg_low 由1 变为0 时，key_low 的值变为高，维持一个时钟周期reg reg2_low;reg reg3_low;always @(posedge clk or negedge rst_n)beginif (!rst_n)beginreg2_low <= 1'b1;endelse if(cnt_key2 == 20'hfffff)beginreg2_low <= key2;endendalways @(posedge clk or negedge rst_n)beginif (!rst_n)reg3_low <= 1'b1;elsereg3_low <= reg2_low;endassign key2_low = reg3_low & ( ~reg2_low);endmodule//时、分、秒module shijian(clk,rst_n,en_1s,key1_low,key2_low,shi,fen,miao);input clk;input rst_n;input en_1s;input key1_low;input key2_low;output[5:0] shi;output[5:0] fen;output[5:0] miao;reg [5:0] shi;reg [5:0] fen;reg [5:0] miao;always@(posedge clk or negedge rst_n) beginif(!rst_n)beginshi<=6'b0;fen<=6'b0;miao<=6'b0;endelse if(en_1s)beginmiao=miao+1'b1;if(miao==60)beginmiao=0;fen=fen+1'b1;if(fen==60)beginfen=0;shi=shi+1'b1;if(shi==24)shi=0;endendendelse if(key1_low)beginfen=fen+1'b1;if(fen==60)beginfen=0;shi=shi+1'b1;if(shi==24)shi=0;endendelse if(key2_low)beginfen=fen-1'b1;if(fen==0)beginshi=shi-1'b1;fen=59;endendelsebeginshi<=shi;fen<=fen;miao<=miao;endendendmodule//显示部分module xianshi(clk,rst_n,en_1ms,shi,fen,miao,led_bit,dataout); input clk;input rst_n;input en_1ms;input[5:0] shi;input[5:0] fen;input[5:0] miao;output[7:0] led_bit; //位选output[7:0] dataout; //段选//数码管显示0~9 对应段选输出parameter num0 = 8'b11000000,num1 = 8'b11111001,num2 = 8'b10100100,num3 = 8'b10110000,num4 = 8'b10011001,num5 = 8'b10010010,num6 = 8'b10000010,num7 = 8'b11111000,num8 = 8'b10000000,num9 = 8'b10010000;reg[3:0] shi1,shi2,fen1,fen2,miao1,miao2;reg[7:0] led_bit; //位选reg[7:0] dataout; //段选reg[2:0] state; //状态寄存器always@(posedge clk or negedge rst_n)if(!rst_n)beginled_bit<=8'b1;state<=3'b0;endelse if(en_1ms)beginstate<=state+1'b1;shi1=shi/10;shi2=shi%10;fen1=fen/10;fen2=fen%10;miao1=miao/10;miao2=miao%10;if(state==3'b000)beginled_bit=8'b11111110;case(miao2)0: dataout<=num0;1: dataout<=num1;2: dataout<=num2;3: dataout<=num3;4: dataout<=num4;5: dataout<=num5;6: dataout<=num6;7: dataout<=num7;8: dataout<=num8;9: dataout<=num9;default :dataout<=num0;endcaseendelse if(state==3'b001)beginled_bit=8'b11111101;case(miao1)0: dataout<=num0;1: dataout<=num1;2: dataout<=num2;3: dataout<=num3;4: dataout<=num4;5: dataout<=num5;default :dataout<=num0;endcaseendelse if(state==3'b010)beginled_bit=8'b11110111;case(fen2)0: dataout<=num0;1: dataout<=num1;2: dataout<=num2;3: dataout<=num3;4: dataout<=num4;5: dataout<=num5;6: dataout<=num6;7: dataout<=num7;8: dataout<=num8;9: dataout<=num9;default :dataout<=num0;endcaseendelse if(state==3'b011)beginled_bit=8'b11101111;case(fen1)0: dataout<=num0;1: dataout<=num1;2: dataout<=num2;3: dataout<=num3;4: dataout<=num4;5: dataout<=num5;endcaseendelse if(state==3'b100)beginled_bit=8'b10111111;case(shi2)0: dataout<=num0;1: dataout<=num1;2: dataout<=num2;3: dataout<=num3;4: dataout<=num4;default :dataout<=num0;endcaseendelse if(state==3'b101)beginled_bit=8'b01111111;case(shi1)0: dataout<=num0;1: dataout<=num1;2: dataout<=num2;endcaseendelse if(state==3'b110)beginled_bit=8'b11011011;dataout<=8'b10111111;endendelsebegindataout<=dataout;led_bit<=led_bit;endendmodule//顶层模块module Shizhong(clk,rst_n,key1,key2,led_bit,dataout); input clk;input rst_n;input key1;input key2;output[7:0] led_bit;output[7:0] dataout;wire en_1s;wire en_1ms;wire[5:0] shi;wire[5:0] fen;wire[5:0] miao;wire key1_low,key2_low;fenpin fenpin_int(.clk(clk),.rst_n(rst_n),.en_1s(en_1s),.en_1ms(en_1ms));anjian anjian_int(.clk(clk),.rst_n(rst_n),.key1(key1),.key2(key2),.key1_low(key1_low),.key2_low(key2_low));shijian shijian_int(.clk(clk),.rst_n(rst_n),.en_1s(en_1s),.key1_low(key1_low),.key2_low(key2_low),.shi(shi),.fen(fen),.miao(miao));xianshi xianshi_int(.clk(clk),.rst_n(rst_n),.en_1ms(en_1ms),.shi(shi),.fen(fen),.miao(miao),.led_bit(led_bit),.dataout(dataout));endmodule。