ADS Fundamentals - 2002_AC Simulations
8ABuilding the Top Level Design in Agilent Ptolemy

PropNADCtdma P1 Type=NoMultipath Pathloss=Yes Env=TypicalUrban Delay=0.0 Pwr=0.0 Seed=1234567 Test=Tap1
AntBase A2 Gain=6 _dB X=0 meter Y=0 meter Height=10 meter
Lab 8 - Building the Top Level Design in Agilent Ptolemy
ADS 2002 CommSys, April 2002
Slide 8 1
Co-simulation
Co-simulation is simulating an A/RF schematic design with a DSP schematic design
Port P2 Num=2
ADS 2002 CommSys, April 2002
Slide 8 10
Add the Demodulator and Sinks
RES R6 R=50 Ohm SpectrumAnaly zer Recv _Out_Spectrum Plot=Rectangular Start=17*Sy m_time Stop=Def aultTimeStop Window=none WindowConstant=0.0
ADS 2002 CommSys, April 2002
Slide 8 6
Place the DSP Sub-Network Into the Top Level Design
RES R1 R=50 Ohm DelayRF D1 Delay=17*Sym_time InterpolationMethod=none IncludeCarrierPhaseShift=Yes TimedSink Qref Plot=Rectangular Start=DefaultTimeStart Stop=DefaultTimeStop ControlSimulation=YES
关于仿真软件ads的书

关于仿真软件ads的书关于仿真软件ADS(Advanced Design System)的书籍,以下是一些可能的参考:1. "Advanced Design System (ADS) Tutorial Guide" by Keysight Technologies: 这是一本官方教程指南,详细介绍了ADS的各种功能和使用方法。
2. "Microwave Office and ADS Circuit Design and Simulation" by Joseph F. White: 这本书涵盖了ADS和其他微波电路设计与仿真软件的使用,包括滤波器、放大器、混频器等电路的设计和优化。
3. "RF and Microwave Circuit Design for Wireless Systems" by David Pozar: 虽然这本书不是专门针对ADS的,但它包含了大量关于射频和微波电路设计的内容,这些内容在使用ADS进行仿真时非常有用。
4. "IC Design for Reliability" by J. R. Davis: 这本书讨论了集成电路设计中的可靠性问题,并包含了一些使用ADS进行仿真和分析的例子。
5. "High-Frequency Techniques: An Introduction to RF and Microwave Engineering" by Frederic J. Gardiol: 这本书是射频和微波工程的入门教材,其中包括了一些使用ADS进行仿真和设计的实例。
以上书籍都可以在各大线上书店或者图书馆找到。
不过需要注意的是,由于ADS软件的更新换代,一些旧版书籍中的内容可能与最新版本的ADS 有所差异,因此在使用时需要结合软件的实际版本进行参考。
ADS教程第2章

ADS教程第2章实验二系统模拟基础概要这一章介绍了如何使用行为模型建立一个系统(例如我们要做的接收系统),这一步是设计系统的第一步,通过对系统级行为模型的模拟,来接近所需的系统性能。
先设定系统组件为所需的性能,然后逐步用独立的电路替换,并可以比较两者的性能差异。
目标●使用上一章的技巧和经验●使用行为模型(滤波器、放大器、混频器)建立一个RF接收器的系统项目,RF=1900MHz,IF=100MHz●使用一个RF源,带相位噪声的本振LO和一个噪声控制器●测试系统:S参数,频谱,噪声等等目录1.建立一个新的系统项目和原理图 (21)2.建立一个由行为模型构成的RF接收系统 (21)3.设置一个带频率转换的S参数模拟 (22)4.画出S21数据 (24)5.提高增益,再模拟,绘制出另一条曲线 (25)6.设置一个RF源和一个带相位噪声的本振LO (26)7.设置一个谐波噪声控制器 (27)8.设置谐波模拟 (29)9.模拟并画出响应:pnmx和V out (32)10.选学-SDD(象征性定义的元件)模拟 (33)步骤1.建立一个新的系统项目和原理图使用上一章学到的方法,建立一个新的项目取名rf_sys2. 建立一个由行为模型构成的RF接收系统a.Butterworth滤波器:在元件模型列表窗口中找到带通滤波器项目Filters-Bandpass。
插入一个Butterworth滤波器。
设定为:中心频率Fcenter=1.9GHz。
通带带宽BWpass=200MHz,截止为BWstop=1GHz。
b.放大器:在元件模型列表窗口中找到System-Amps&Mixers 项目,插入放大器Amplifier。
设定S21=dbpolar(10,180)。
c.Term:在port1插入一个端口。
端口Terms在元件模型列表窗口的Simulation-S_Param中找。
关于Butterworth滤波器请注意-Butterworth滤波器的行为模型是理想情况的,所以在通带内没有波纹。
Advanced Design System - 2002_DC Simulations and sub-circuit modeling

Tips for wiring!
• Use the wire or connect pins = wired • Point and click to snap to grid • Drag a wired component and it stays wired. • Wire color can be changed: Options > Layers
Swept Variable in controller
Sweep: allows you to sweep a parameter but it must be declared as a variable. Note the dialog entry automatically puts quotes on the controller (screen) entry.
VARS can be used with optimization, parameter sweeps, and other applications!
Next, symbols, names,...
ADS 2002 Fundamentals - April, 2002
Slide 3 - 7
TIP: Wiring and Moving components
Or use the command: Edit > Wire/Pin Label Attributes
For busses, see: examples/Tutorial/wire_bus_prj It is a documented example. Next, VARS...
ADS 2002 Fundamentals - April, 2002
Advanced Design System - 2002_System Design Fundamentals

Lower level: circuit.
Set up the simulation controller at the top level.
ADS 2002 Fundamentals - April, 2002
• Install directory (location of ADS program) - C or D drive on a PC $HPEESOF_DIR (UNIX variable) or %HPEESOF_DIR% (PC variable) • Home directory (location of your ADS design work) - C:\users\default on a PC $HOME (UNIX variable) or %HOME% (PC variable)
HB results: Fundamental tones, harmonics, difference and sum frequencies are plotted. However, because no conversion gain is accounted for in the SDD equation, the results have a lower magnitude than the behavioral model mixer. Also, Transient results compare within 1dB of HB using fs function.
Install
LICENSE Variable and File:
Filters DesignGuide,Transient Momentum and the DAC

NOTE: iVar1 always = 1 (index at first column). However, iVal1 always starts at 0 (same as ADS data).
The file must be in the DATA directory and must be in correct format. The circuit simulation manual has information on file formats such as DSCR..
Slide 6 - 13
Steps in the Design Process
• Design the RF sys behavioral model receiver • Test conversion gain, spectrum, etc. • Start amp_1900 design – subckt parasitics • Simulate amp DC conditions & bias network • Simulate amp AC response - verify gain • Test amp noise contributions – tune parameters • Simulate amp S-parameter response • Define amp matching topology and tune input • Optimize the amp in & out matching networks • Filter design – lumped 200MHz LPF • Filter design – microstrip 1900 MHz BPF • Transient and Momentum filter analysis • Amp spectrum, delivered power, Zin - HB • Test amp comp, distortion, two-tone, TOI • CE basics for spectrum and baseband • CE for amp_1900 with GSM source • Replace amp and filters in rf_sys receiver • Test conversion gain, NF, swept LO power • Final CDMA system test CE with fancy DDS • Co-simulation of behavioral system
射频实验内容要求

射频实验系统系列课题介绍一、射频实验系统的结构组成在无线通讯中,射频发射器担任着重要的角色。
无论是语言还是数字信号都要利用电磁波经空气传送到远端,而此过程都要使用射频前端发射器。
其主要电路结构如图1-1所示,它大致可分为9个部分。
1.中频放大器(IF AMP ):一般放大器电路,根据信号输入功率不同可分为小信号放大器、低噪声放大器和功率放大器三种。
2.中频滤波器(IF BPF ):滤波器的用途是抑制无用信号,而使有用信号顺利通过。
3.上变频混频器(MIXER ):混频器是利用混频管电阻(或电容)的非线性特性,将输入的外来信号频率S ω和本机振荡信号的频率L ω进行组合,产生一系列组合频率SL m n ωω±,再经滤波取出其中的和频S L ωω+(上变频器)或差频S L ωω-或L Sωω-(下变频器)。
4.射频滤波器(RF BPF )5.射频驱动放大器(RF AMP )6.射频功率放大器(PA )7.载波振荡器(LO )8.载波滤波器(LO BPF )9.发射天线(Antenna )射频前端接收器的基本电路结构如图2-1所示。
共分为天线(ANTENNA)、射频低噪声放大器(RF LAN)、下变频器(DOWN MIXER)、中频滤波器(IF BPF)和本地振荡器(LO)。
其工作原理是将发射端所发射的射频信号由天线接收后,经低噪声放大器后,再送入下变频器与本地振荡器混频后由中频滤波器将设计所要的频段信号滤出,最后再经过中频放大器将信号放大后,送到基频电路部分解调出所需要的信息信号。
二、ADS仿真软件Advanced Design System(ADS)是美国安捷伦(Agilent)公司所生产拥有的电子设计自动化软件;ADS功能十分强大,包含时域电路仿真(SPICE-like Simulation)、频域电路仿真(Harmonic Balance、Linear Analysis)、三维电磁仿真(EM Simulation)、通信系统仿真(Communication System Simulation)和数字信号处理仿真设计(DSP);支持射频和系统设计工程师开发所有类型的RF设计,从简单到复杂,从离散的射频/微波模块到用于通信和航天/国防的集成MMIC,是当今国内各大学和研究所使用最多的微波/射频电路和通信系统仿真软件软件。
ADS应用中的器件建模

Advanced Topics in Circuit Design (using ADS 2002) LAB 1: Modeling TechniquesOBJECTIVES• Use various devices in simulations• Extract parameters for a model• Use an SDD in an optimization• Use Model Binning• Use SDD’s to model an amplifier and nonlinear resistor• Use an FDD to model a doublerLab 1: Modeling Techniques1-2 Copyright Agilent Technologies 2002 TABLE OF CONTENTS1. Start ADS on your computer and copy the project (3)2. MODELS_prj...............................................................................................................3 2.1. DIODE Model. (3)2.1.1. BB535_Model.dsn.........................................................................................3 2.1.2. DIODE_Extraction_of_N.dsn. (6)2.2. BJT Model..........................................................................................................10 2.2.1. AT30500.dsn (10)2.2.2. AT30500_IC_VCE_Curves.dsn..................................................................12 2.2.3. AT30500_IC_and_IB_vs_VBE.dsn (13)2.2.4. AT30500_Extraction_of_IS_and_NF.dsn.................................................14 2.3. Model Binning. (16)2.3.1. Model_Binning_BJT_Example.dsn..........................................................16 2.3.2. Model_Binning_MOSFET_Example.dsn. (19)3. VENDOR_MODELS_prj ..........................................................................................23 3.1. AT36 Chip PHEMT.. (23)3.1.1. ATF36_CHIP_MODEL.dsn.........................................................................23 3.2. ATF36077 Packaged PHEMT (25)3.2.1. ATF36077_HB_Convergence.dsn .............................................................25 4. SDD_EXAMPLES_prj. (27)4.1.1. Amplifier_Model_DC.dsn..........................................................................27 4.1.2. Amplifier_Model_HB.dsn.. (30)4.1.3. Nonlinear_Resistor_DC.dsn......................................................................31 4.1.4. Nonlinear_Resistor_HB.dsn. (32)5. FDD_EXAMPLES_prj..............................................................................................33 5.1.1. FDD_DOUBLER_HB.dsn (33)6. References (37)Lab 1: Modeling TechniquesCopyright Agilent Technologies 2002 1-3PROCEDURE1. Start ADS on your computer and copy the project Project files used in this course should be copied to your computer as needed. The project files are located in the ADS Examples\Training\ADVCKT directory. You can use the ADS main window command: File > Copy Project, then select the Examples Directory and Browse to each project as you need it, as shown here: NOTE: The instructions for copying the project files will not be given again.2. MODELS_prj2.1. DIODE Model2.1.1. BB535_Model.dsn2.1.1.1. Copy and Open the project “MODELS_prj”, and then open thered text is just comment text.Lab 1: Modeling Techniques2.1.1.2. Here is our diode:2.1.1.3. Here are the equations that describe the DC forward andreverse characteristics of our diode junction:(forward biased: VD > 0)ID = IS * (e (q*VD / (N*k*T) ) – 1 )(reverse biased: VD < 0)ID = - ISwhere: k = 1.38 x 10-23 J/K (Boltzmann’s Constant)q = 1.602 x 10-19 C (charge on electron)T = 298.15 Kelvin (25 deg C)(you can also see this on page 19 of Massobrio andAntognetti, see references at end of lab)2.1.1.4. Note the value of N for our BB535 diode.N = 1.027831N is the forward emission coefficient of the diode.For ideal diodes, N = 1.0.1-4 Copyright Agilent Technologies 2002Lab 1: Modeling TechniquesCopyright Agilent Technologies 2002 1-52.1.1.5. Note the value of IS for our BB535 diode.IS = 0.919 fAIS is the saturation current of the diode.IS relates to both the forward and reverse characteristics ofthe diode, as seen above.2.1.1.6. Note the value of RS for our BB535 diode.RS = 0.094949 OhmsRS denotes a parasitic resistance in series with our diode.Our value of 0.094949 Ohms is almost negligible unless highcurrents are run through the diode.2.1.1.7. Note the value of LS for our BB535 diode.LS = 1.97 nHLS is a parasitic inductance in series with our diode.LS causes a change in the effective capacitance of our diode. This effective capacitance change will be an important effect in a later lab when we use this BB535 diode as a varactor(voltage tunable capacitor).2.1.1.8. Here is the equation for the diode’s reverse-bias junction capacitance(reverse biased : VD < 0)CJ = CJO / (1 – VD / VJ )M2.1.1.9. Note the values of CJO, VJ, and M for our diode.CJO = 28.7 pFVJ = 1.959931 VoltsM = 0.953817CJO is the zero-bias junction capacitance.VJ is the built-in junction voltage.M is the junction grading coefficient.2.1.1.10. Close the design “BB535_Model.dsn”.Lab 1: Modeling Techniques1-6 Copyright Agilent Technologies 20022.1.2. DIODE_Extraction_of_N.dsn2.1.2.1. Open the schematic “DIODE_Extraction_of_N.dsn”.2.1.2.2. In this schematic a voltage is applied across the diode and thecurrent running though the diode is measured. In this way, an I-V curve for the diode can be generated.A forward bias of 0 to +1.2 volts is applied across the diode, using the DC voltage source (SRC1). The bias is increasedslowly, in 2 mV steps, giving fine resolution for the I-V curve. This is a swept DC simulation, where the variable VD isswept. The Var equation (VAR1) is used to initialize VD for the sweep.A measurement equation (Meas1) is used to take the natural log ofthe diode current that is measured. This quantity,“ln_of_ID”, will be useful in the extraction of the diode emission coefficient, N.2.1.2.3. Run the simulation and view the results in theData Display. Note that the Data Display automatically opens when the simulation isfinished.Lab 1: Modeling TechniquesCopyright Agilent Technologies 2002 1-72.1.2.4. Look at the first page in the Data Display. It is titled, “I-VCurve”. This page should come up automatically.Here the current, “ID”, is graphed versus the swept biasvoltage, “VD”.2.1.2.5. Change to the second Data Display page, by using the Pagemenu and selecting the second page, “Extraction of N”.2.1.2.6.A plot is generated of ln(ID) versus VD.Two markers denote the estimated linear region of the curve. The slope ofthe line is extracted from these twomarkers via Data Display equations. N is related to the slope.Lab 1: Modeling Techniques1-8 Copyright Agilent Technologies 20022.1.2.7.Change to the third Data Display page, “Alternative Extraction of N”. Note that the “diff( )” function is used here to obtain the slope, or derivative, of the “ln_of_ID” curve. This is another method of estimating the linear region (the flat portion of the “Alternative_N” curve”) and extracting N. 2.1.2.8.Insert an equation (Eqn) and click the “Functions Help” button. Under the “MeasEqn Function Reference” topic, check out the “diff( )” function help page. The “diff( )” function can be used to take derivatives of any data. Close the Help page and click “Cancel”. 2.1.2.9.Create a new Data Display page by using the “New Page” command under the “Page” menu. Name this new page “page 4”.Lab 1: Modeling TechniquesCopyright Agilent Technologies 2002 1-92.1.2.10. In this new Data Display page, insert a listing column for “ln_of_ID”. Insert another listingcolumn for “ln_of_ID_slope”.Note that the derivative array “ln_of_ID_slope” has one lessentry, and that the independent variable values are between those of “ln_of_ID”.2.1.2.11. Change back to the “I-V Curves” Data Display page. Save yourData Display changes. Close the Data Display and Simulation Status Window. Close the design“DIODE_Extraction_of_N.dsn”.Lab 1: Modeling Techniques1-10 Copyright Agilent Technologies 20022.2. BJT Model2.2.1. AT30500.dsn2.2.1.1. Open the schematic “AT30500.dsn”.Note the bipolar transistor, BJT1. The “Model” field on this device points to the model card “BJTM1”. Every active semiconductor device in an ADS schematic must have an associated model card, just like SPICE.This schematic is an actual device model for the AT30500 chip from Agilent Semiconductor. It is available on the Agilent Semiconductor website at: 2.2.1.2. Turn on pin numbers and names. Start by going to the Options >Preferences menu:2.2.1.3. Select thePin/Tee taband checkboth the PinNumbers andPin Namesboxes. ClickOk.2.2.1.4. View the schematic symbol pageusing View > Create/EditSchematic Symbol. You mayneed to also “Zoom out by 2”.This symbol was created by copyingartwork from the ADS BJT symbol and attaching the 3 pins(Collector = 1, Base = 2, Emitter = 3) associated with our 3ports.View the schematic page again using View > Create/EditSchematic.You can also see the ADS BJT symbol artwork when youopen the following schematic (use Open Design and theBrowse button):D:\Ads2001\circuit\symbols\SYM_BJT_NPN.dsn2.2.1.5. Close the design “SYM_BJT_NPN.dsn” and the design“AT30500.dsn”.2.2.2. AT30500_IC_VCE_Curves.dsn2.2.2.1. Open the design “AT30500_IC_VCE_Curves.dsn”.2.2.2.2. This design shows a typical curve tracer. The inner sweep iscollector-emitter voltage, VCE, from 50 mV to 20V. The outersweep is base current, IB, from 5 uA to 35 uA.2.2.2.3. Run the simulation and view the Data Display results.2.2.2.4. A forward Early plot is shown that displays IC vs. VCEcurves.These typical BJT curves describe how the collector current(IC) varies with base current (IB) and collector-emittervoltage (VCE).One of the parameters that can be extracted from this curveset is VAF, the forward Early voltage.If you were to extend linear fits to these curves, down pastVCE = 0 V, down to negative VCE values, the fitted lineswould all meet at one point, (x,y) = (-VAF,0).In our AT30500 model, the VAF parameter is 105 Volts, whichis quite good. VAF’s better than 50 Volts are very desirable.A VAF of infinity would be ideal. This ideal transistor, with aVAF of infinity, would provide a constant collector current nomatter what the collector-emitter voltage is.2.2.2.5. Close the Data Display and Simulation Status Window. Closethe design “AT30500_IC_VCE_Curves.dsn”.2.2.3. AT30500_IC_and_IB_vs_VBE.dsn2.2.3.1. Open the design “AT30500_IC_and_IB_vs_VBE.dsn”.2.2.3.2. This schematic shows the next test one might run on a BJTdevice. This test varies base-emitter voltage (VBE) andmeasures base current (IB) and collector current (IC).This test holds VCE constant at 5 Volts, a typical operatingpoint.2.2.3.3. Run the simulation andview the results in theData Display.2.2.3.4. The Data Display has two pages. The first is titled “Beta”. Itshows how forward current gain (Beta or BF) varies withVBE. The maximum Beta is calculated, as well as, the VBE atwhich it occurs.2.2.3.5. The second Data Display page is titled “IC and IB”. The graphon this page shows how IB and IC vary with VBE. Themarkers are located at the maximum Beta point of VBE =0.736 V. IB and IC at this maximum Beta point are alsodisplayed.log(Beta) is the vertical distance between the IC and IBtraces on this semi-log plot:Beta = IC / IB è log(Beta) = log(IC) – log(IB)2.2.3.6. Close the Data Display. Do not save DDS changes. Close theSimulation Status Window. Close the design.2.2.4. AT30500_Extraction_of_IS_and_NF.dsn2.2.4.1. Open the design “AT30500_Extraction_of_IS_and_NF.dsn”.2.2.4.2. In this schematic, VBE is being swept. The equations inVAR1 set VBE equal to VCE, so that the base-collectorjunction has 0 Volts across it and does not activate.Under these conditions, we can extract the BJT modelparameters IS and NF.Please note the measurement equationsbeing used to calculate the naturallogarithms of the base and collectorcurrents.2.2.4.3. Simulate and view the results in the Data Display.2.2.4.4. The Data Display has two pages. The first page is titled“Extracting NF and IS”.On this page, the natural logarithms of IB and IC are plottedversus VBE. Two markers are again inserted onto the linearportion of the ln(IC) curve.The slope is calculated and NF is computed from it.NF = 1.030Compare this to the NF model parameter in the“AT30500.dsn” schematic.The y-intercept is calculated and IS is computed from it.IS = 7.8 x 10-17Compare this to the IS model parameter in the “AT30500.dsn”schematic.2.2.4.5. The second Data Display page shows an alternative methodof calculating the slope and extracting NF, using the “diff( )”function.2.2.4.6. Close the Data Display. Do not save DDS changes. Close theSimulation Status Window. Close the design“AT30500_Extraction_of_IS_and_NF.dsn”.2.3. Model Binning2.3.1. Model_Binning_BJT_Example.dsn2.3.1.1. Open the schematic “Model_Binning_BJT_Example.dsn”.2.3.1.2. Sometimes, a device can be drastically different dependingon the device size. This is especially true with empirical(curve-fit) models. This design shows how Model Binningcan change model cards based on device size (Area).2.3.1.3. There are 3 different BJT size ranges in this schematic, eachwith its own Gummel-Poon model. “Beta” is the ONLYparameter that varies in this particular case:SmallBJT: Beta = 150Valid for emitter area scale factors(Area) between 20 and 30.MediumBJT: Beta = 50Valid for emitter area scale factors(Area) between 30 and 40.LargeBJT: Beta = 25Valid for emitter area scale factors(Area) between 40 and 50.2.3.1.4. Notice that the “Model” field on the BJT points to“BinModel1”, the Model Binning component, instead of amodel card.2.3.1.5. Double-click on theModel Binningcomponent(BinModel1). Noticethe parameter thatwill vary is “Area”.This parameter mustbe defined on the BJTdevice itself. Closethe dialog box byusing “Cancel”.2.3.1.6. The minimum areasand maximum areasshown here determine which model card will be used for agiven device area.2.3.1.7. Check the DC simulation component in the schematic. Thissimulation will sweep VBE while current probes measureboth IB and IC. Notice that VCE = 3 Volts for this example.The equation, “Meas1”, defines Beta as forward current gain.2.3.1.8. Nested around the DC simulation is a Parameter Sweep,“Sweep1”. This Parameter Sweep will change the “size” or“area” of the transistor from 25 to 45 in steps of 10. Thisshould enable the use of all three size models.2.3.1.9. Change the Component Palette to “Devices - BJT”. Note thatthe upper left icon in the palette is the Model Binningcomponent.2.3.1.10. Run the simulation and viewthe results in the Data Display.2.3.1.11. There are two pages to the Data Display. The first showscollector current (IC) and base current (IB) versus VBE. Thesecond page shows Beta versus VBE. Indeed, Beta isdifferent for the different size devices. Notice that for the“size=25” device, Beta does not quite reach 150. This is dueto the interaction of Beta with other parameters such as IKFand VAF.2.3.1.12. Go back to the schematic and change IKF to 80e-3 for allthree models. Re-simulate. View the results.Return to the schematic again and change IKF back to 40e-3for all three models. Change VAF on all three models to 75.Re-simulate.Notice the effect of IKF and VAF on measured Beta. Modelparameters can sometimes have significant interactions.2.3.1.13. View the first Data Display page where IC and IB are shownversus VBE. Double click on the plot grid. This will bring upthe “Plot Options” dialog box. Double clicking on the tracewould bring up the “TraceOptions” dialog box.Select the “Plot Options” tab.Select the “Y-Axis” on the left.Click “More” to the right of“Axis Label”. Notice the formatis “Engineering”. This makesthe Y-Axis list out in nA, uA,and mA instead of scientificexponential notation. Click“Cancel” and “Cancel” to closethe dialog boxes.2.3.1.14. Return to the first DDS page. Save the schematic and theData Display. Close the Data Display and Simulation StatusWindow. Close the design“Model_Binning_BJT_Example.dsn”.2.3.2. Model_Binning_MOSFET_Example.dsn2.3.2.1. Open the schematic“Model_Binning_MOSFET_Example.dsn”.2.3.2.2. This design shows the model binning concept in 2 dimensions(W and L). The previous BJT model binning design showedbinning only in one dimension (Area).2.3.2.3. The purpose of model binning is to enable device modelingengineers to have different models for a device depending onits size (Area) or geometry (W, L). This can be veryimportant for small devices (e.g. short-channel MOSFET’s),where the behavior of the device changes drastically withgate width and gate length.2.3.2.4. This schematic uses the SPICE Level 1 MOSFET model forsimplicity while demonstrating the model binning concept.In reality, modeling engineers and IC designers who workwith the Berkeley BSIM3 MOSFET model deal withgeometry-dependence all the time.2.3.2.5. BSIM3 is one of the most recent and most “accurate”MOSFET models. Where “accurate” means that the modelequations match the measured data in most instances andeffectively predict device performance over wide ranges ofbias, temperature, and device size.The BSIM3 model is a MOSFET model that deals with short-channel MOSFET’s. Short-channel MOSFET’s are verycommon technology today, found in many modern SiGe andBiCMOS processes.BSIM3 has over 100 model parameters total. The acronymBSIM stands for Berkeley Short-Channel Insulated Gate FETModel. The latest version is BSIM4. Both BSIM3 and BSIM4will be available shortly in ADS and IC-CAP.To see the BSIM3 model in the ADS schematic window,change to the “Devices-MOS” component palette. Thispalette contains many different MOSFET models includingBSIM1, BSIM2, BSIM3, and BSIM3SOI. BSIM3SOI is forsilicon-on-insulator technologies. Insert some model cardsand check them out. Delete these model cards when you arefinished reviewing them.2.3.2.6. Take another look at the schematic. Notice that only one DCbias point is being simulated here:VGS = 2.5 Volts VDS = 5.0 VoltsSince VTO = 0.827 Volts, VGS is greater than VTO. Therefore,the device must be in the “ohmic” or “saturation” regions.However, VDS is much greater than (VGS-VTO). Therefore,this device is in the “saturation” region, where the VGSsquare-law characteristic applies:IDS = 0.5*KP*(W/L)*(VGS-VTO)2*(1+LAMBDA*VDS) 2.3.2.7. Look closely at VAR4. Here, the variable “Ratio” is defined asthe ratio of W/L. This is an important quantity in IC design, asmentioned earlier.2.3.2.8. Notice the VAR variables passed to the Data Display in theDC simulation (DC1):LAMBDA, Ratio, VDS, VGS, and VTOThese will be important in the extraction of KP for each ofour different sized devices.2.3.2.9. The parameters “Length” and Width” are part of the MOSFETdevice “MOSFET1”. Model binning can ONLY be done withparameters that are part of the actual device (like Length,Width, and Temp.2.3.2.10. Take a close look at the Parameter Sweep, “Sweep1”, and theDC simulation, “DC1”. Notice that there will be a total of fourdevices simulated, over a range of two different lengths andtwo different widths:Device 1: W = 100 um, L = 10 um (W/L = 10)Device 2: W = 100 um, L = 50 um (W/L = 2)Device 3: W = 500 um, L = 10 um (W/L = 50)Device 4: W = 500 um, L = 50 um (W/L = 10)2.3.2.11. Take a look at the four device models. Notice the onlydifference is the KP (transconductance) parameter:ShortNarrow: KP = 20uA/V2ShortWide: KP = 60 uA/V2LongNarrow: KP = 10 uA/V2LongWide: KP = 30 uA/V22.3.2.12. Double-click on the Model Binning component (BinModel1):Notice the Length and Width ranges for the four models.Close the model binning window with “Cancel”.2.3.2.13. When the simulation is run, the four devicetransconductances should come out like this:Device 1: W = 100 um, L = 10 um, KP = 20 uA/V2Device 2: W = 100 um, L = 50 um, KP = 10 uA/V2Device 3: W = 500 um, L = 10 um, KP = 60 uA/V2Device 4: W = 500 um, L = 50 um, KP = 30 uA/V22.3.2.14. Run the simulation andview the results in theData Display.2.3.2.15. View the first Data Display page, “Operating Region”. Thecalculations here verify that the devices are in the“saturation” region. Thus, the following formula can be usedto extract KP:KP = IDS / (0.5*Ratio*(VGS-VTO)2*(1+LAMBDA*VDS))To use this formula, the following parameters were sentforward from the schematic:Ratio, VGS, VTO, LAMBDA, VDS2.3.2.16. View the second Data Display page, “Calculated KP’s”. Thevalues of the passed parameters are listed out. KP’s areextracted using the above formula. The KP’s match thevalues listed in the four models.2.3.2.17. Note that the W (width) and L (length) values are shown inmicrons. Double click on any listing column. Change to the“Plot Options” tab. Notice the format is “Engineering”.2.3.2.18. Close the Data Display. Do not save DDS changes. Close theSimulation Status Window. Close the design“Model_Binning_MOSFET_Example.dsn”.3. VENDOR_MODELS_prj3.1. AT36 Chip PHEMT3.1.1. ATF36_CHIP_MODEL.dsn3.1.1.1. Copy and Open the project “VENDOR_MODELS_prj”.3.1.1.2. Open the schematic “ATF36_CHIP_MODEL.dsn”.3.1.1.3. This is the model of the ATF36 PHEMT chip from AgilentSemiconductor.3.1.1.4. A PHEMT is a pseudomorphic high mobility electron device.Think of a PHEMT like a GaAsFET with a heterojunction.Similarly, think of HBT’s (heterojunction bipolar transistors)as BJT’s with heterojunctions.3.1.1.5. A heterojunction is a semiconductor junction where twodissimilar semiconductor materials meet (like InGaAs andGaAs).3.1.1.6. Before heterojunctions were developed in HBT’s andHEMT’s, semiconductor devices used homojunctions whereboth the p-doped and n-doped materials were silicon, or bothGaAs.3.1.1.7. Heterojunctions add another degree of freedom for devicedesigners. They allow device designers to optimizeproperties like HBT base resistance and HBT current gainindependent of each other. Whereas, before with siliconBJT’s, these two properties were inextricably linked together.3.1.1.8. With heterojunctions of different materials, device designerscan now control the bandgap voltage of the junction bychanging the junction materials on either side (InGaAs –GaAs junction) or by changing their stoichiometric ratios(e.g. Ga0.47In0.53As - GaAs). This is important for LED’s sincethe bandgap voltage of an LED is directly related to thewavelength of light emitted.3.1.1.9. Look back at the AT36_CHIP_MODEL schematic. Notice thatthe Statz GaAsFET model is being used here. Agilent choseto use this model because it best fits the measured data (eventhough the Statz model was developed for GaAsFET’s, notPHEMT’s). However, GaAsFET’s and PHEMT’s aresomewhat similar in construction, concept, and operation.3.1.1.10. Currently, there are few industry-standard PHEMT models,because PHEMT’s are relatively new devices. Some modelsthat are used for PHEMT’s come from GaAsFET models, likeEEFET3 and Statz. However, the EEHEMT1 model wasdeveloped specifically for HEMT’s and PHEMT’s.3.1.1.11. Double-click on the Statz model card. Click “Help”. Thesehelp pages show the Statz I-V equations, as well as, otherrelated material. The reference for the Statz model is listedat the end of the help pages. Close the “Help” page. Click“Cancel”.Close the “ATF36_CHIP_MODEL.dsn” schematic.3.2. ATF36077 Packaged PHEMT3.2.1. ATF36077_HB_Convergence.dsn3.2.1.1. Open the schematic, “ATF36077_HB_Convergence.dsn”.3.2.1.2. Take a look at the schematic. Note the use of a circulatoragain to isolate the “Vsource” node.3.2.1.3. This design looks like a normal harmonic balance simulationwith the “RF_freq” variable setting the same frequency in theharmonic balance controller and on the source. The“RF_power” variable is also present to make changing theinput power level easy.3.2.1.4. However, notice the two extra blocks, “SwpPlan1” and“Sweep1”. Also notice the variable “Order” in VAR2, and inthe harmonic balance controller, “HB1”.“SwpPlan1” sets variable “Order” from 3 to 25 in steps of 1.“Sweep1” performs a harmonic balance simulation for eachvalue of “Order”. Thus, harmonic balance simulations areperformed with the Order parameter set from 3 to 25.3.2.1.5. Run the simulation and viewthe results in the Data Display.3.2.1.6. There are two pages in the Data Display. The first shows thevalues of the fundamental, second harmonic, and thirdharmonic versus Order. Please study these closely anddiscuss them with your instructor.Notice that all harmonic levels may not converge at the sameOrder. Notice the fundamental and second harmonicsconverge at about Order = 15. Whereas, the third harmonicconverges at about Order = 12.Harmonics can also converge at different Orders for eachcircuit.From these results, we can conclude that for a harmonicbalance simulation, the Order parameter should bedetermined by iteration for every circuit.Follow the general procedure:1) Start with Order = 3. Simulate. Check allharmonic power levels.2) Change the Order to 5. Simulate. Check allharmonic power levels again. Are they changing orare they the same?3) If they are changing, increase the Order until theharmonic power levels remain approximately thesame.Start with Order = 3 since this will be a fast simulation.Higher Orders result in longer simulation times, but moreaccurate results.3.2.1.7. Change to the second Data Display page. This page showsthe same data as the first page, but in tabular form. Noticethe number of frequencies increases directly with increasingorder.3.2.1.8. Stay on page 2 and save the Data Display. Close the DataDisplay. Re-open the same Data Display. Notice that it opensup starting on page 2 now. Change to page 1 and save theData Display.3.2.1.9. Close the Data Display. Close the Simulation Status Window.Close the schematic.4. SDD_EXAMPLES_prj4.1.1. Amplifier_Model_DC.dsn4.1.1.1. Copy and open the “SDD_EXAMPLES” project.4.1.1.2. Open the schematic “Amplifier_Model_DC.dsn”.4.1.1.3. This design performs a DC sweep from –2 Volts to +2 Voltson the input of this amplifier circuit. The output is loadedwith a 1 Megaohm resistor.4.1.1.4. The amplifier is a subcircuit. It has a small signal gain (A) of20, and input resistance (Ri) of 100 Megaohms, an outputresistance (Ro) of 0 Ohms, and a supply limit (Vs) of +/- 15Volts. These amplifier parameters are passed into thesubcircuit via “File > Design Parameters”.4.1.1.5. Let’s take a look at the amplifier subcircuitby pushing down into it:4.1.1.6. Notice the use of atwo-port SDD(SDD2P).An SDD is a“symbolically defineddevice” which isdefined in the timedomain.。
- 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。
ADS Fundamentals - 2002LAB 4: AC SimulationsOverview - This lab continues the amp_1900 project and uses the same sub-circuit as the previous lab. This exercise teaches the basics of AC simulation, including small signal gain and noise. It also shows many detailed features of the data display for controlling and manipulating data.OBJECTIVES∙Perform AC small signal and noise simulations.∙Adjust pin/wire labels.∙Sweep variables and write equations.∙Control plots, traces, datasets, and AC sources.Lab 4: AC Simulations4-2 Table of Contents1. Copy & Paste (Ctrl+C / Ctrl+V) from one design to another. (3)2. Modify the copied circuit and pin labels (4)3. Push and pop to verify the sub circuit. (5)4. Set up an AC simulation with Noise. (5)5. Simulate and list the noise data (5)6. Control the output of equations and node voltages. (6)7. Simulate without noise. (7)8. Write a data display equation using a measurement equation (7)9. Work with measurement and data display equations. (8)10. Plot the phase and group delay for the ac analysis data (9)11. Variable Info and the w hat function. (10)12. OPTIONAL - Sweep Vcc (as if the battery voltage is decreasing) (11)Lab 4: AC Simulations4-3 PROCEDURE1. Copy & Paste (Ctrl +C / Ctrl +V) from one design to another.a. Open the last design (dc_net) and copy the circuit shown highlighted here by dragging the cursor around the area - this is known as rubber banding. With the items highlighted, copy then by using the keyboard keys Ctrl + C or the Edit > Copy command. Using Ctrl + C is preferred because it eliminates mouse clicks.b. Use the File> New Design command to create a new schematic and name it: ac_sim . Then use Ctrl + V or use Edit > Paste and insert (ghost image) the copy by clicking into the new schematic.c. Save the ac_sim design. You must save it or it will not be written to the database.d. Click the command Window > Designs Open . This command gives you access to designs that are open in memory but not visible in a window or not saved in memory. When the dialog appears, select dc_net and click OK . Then close dc_net design using File > Close Design (no need to save the changes).e. In the empty schematic window, reopen the ac_sim design using theFile > Open Design icon . This gives you a list of all the designs in the project. If a design is created but not saved initially, it will not be in this list and you will need to use the command Window > Designs Open to access it.Lab 4: AC Simulations4-42. Modify the copied circuit and pin labels.Delete wires, insert new components, and rewire as needed. The steps follow:a. Disconnect the DC source and move it to the side with a ground.b. Insert two ideal DC_Block capacitors from the Lumped-Components palette or use component history.c. Insert a V_AC source from the Sources-Freq Domain palette. Ground the source. Then add a 50 ohm load resistor and ground to the output.d. Modify the Pin/Wire (node) labels. Click the Name icon. Add Vcc as a label to both RC and the DC source. This will connect them electrically instead of a wire.e. Add Vin and Vout as shown. Also, if you did any OPTIONAL steps in lab 3, remove VC and VBE by clicking on those labels when the dialog is blank (shown here) or use the command : Edit >Wire/Pin Label > Remove Wire/Pin Label .f. Verify that the circuit looks like the one shown here.NOTE on Wire/Pin Label Attributes : You can drag labels to move them and you can edit attributes by double clicking on them or by using the command: Edit >Wire/Pin Label > Wire/Pin Label Attributes.Lab 4: AC Simulations4-5 3. Push and pop to verify the sub circuit.a. Select the bjt_pkg and push into the sub-circuit (use the icons) to checkyour sub circuit, and then pop out again.4. Set up an AC simulation with Noise.a. Insert an AC Simulation controller. Then edit the start, stop, and step frequencies: 100 MHz to 4 GHz in 100 MHz steps.b. In the Noise tab, check the box for Calculate noise and add the Vout node. Set the Mode to Sort by Name for each noise contributor. Sort by value is good for large circuits to see the largest contributors first. Also, all noise values will be simulated if a Dynamic range (threshold) is not set.c. Turn on the Display for each of the parameters as shown here.5. Simulate and list the noise data.a. Simulate (F7).b. In the data display, insert a list (icon) of name and vnc (voltage noise contributors) using the Ctrl key to select them both. As shownhere, at each frequency, Q1.BJT1 is the total noise voltage for the device and is composed of: Q1.BJT1.ibe and Q1.BJT1.ice. However, these are not correlated voltages but have been added as noise powers: (V total )2 = (V ibe )2 + (V ice )2. The total vnc is the same as Vout noise.c. Savethe schematic and data display.Lab 4: AC Simulations4-66. Control the output of equations and node voltages.a. In the ac_sim schematic, insert a MeasEqn from any simulation palette. Or, you can type in MeasEqn in component history.b. Directly on the schematic screen, edit (type) the equation to compute voltage gain using the node (pin) labels Vin and Vout. Use the keyboard arrow key to move across the equal (=) sign.c. Edit the AC simulation controller and go to the Output tab. The default is for all labeled node voltages (pin/wire labels) and all Measurement equations to be reported in the dataset. You will change this in the next steps.d. Uncheck the box for Node Voltages and click on the Add/ Remove button.e. Select Vin and Vout from the list of available outputs and Add them as shown here - then click OK . Only those node voltages will be written into the dataset after simulation and Vcc will not. This works for measurement equations also.d. Click OK to dismiss the dialog – you are now ready to simulate.NOTE on node name display : You can display the node names (Display tab –NodeName check box) but it is not necessary.Lab 4: AC Simulations4-7 7. Simulate without noise.a. In the schematic, turn off the noise calculation by changing (typing) yes to no as shown here. This will save simulation time and memory, especially for large circuits. Of course, this will make your dataset list (name and vnc) invalid.b. Save the schematic and Simulate (F7).8. Write a data display equation using a measurement equation.a. In the data display, delete the invalid noise listing.b. Insert a data display equation (use the icon).c. In the dialog, write an equation for the gain in dB as shown here. Notice that you are inserting the schematic measurement equation into your data display equation and click OK :Note on equations - If the measurement equation for voltage gain was not already calculated, you would write the data display equation with all the required values, for example: gain_dB = 20 * log (mag (Vout) / mag (Vin)). However, because that voltage gain was already calculated, it is easier tosimply insert it here.Lab 4: AC Simulations4-89. Work with measurement and data display equations.a. Insert a list of the measurement equation gain_voltage and the DDS equation you just wrote gain_dB . Again, schematic measurement equations are automatically written into the dataset as shown here. But equations you write in the data display are not - they are accessed in the data display Equations memory. To display your dataset equation, gain_dB, click on the arrow box (shown here) and then select it and add it. Click OK and both equations will appear in the list.b. Scroll down the list to values around 1900 MHz, using the arrow buttons as shown.c. Insert the cursor directly into the gain_voltage column and type in the dB function as shown. Then add parentheses so that it reads: dB (gain_voltage). This demonstrates the flexibility of the data display for operating (with ADS functions) directly on data and equations.d. Click the data display Undo command to return to remove the dB function.e. Edit the list (double click) and change it to a rectangular plot by selecting the icon.f. Insert the cursor directly onto the Y-axis label and change gain_voltage to dB (gain_voltage) similar to the way you did in the list. Then undo it. Again, thisshows the power of functions and the data display.Lab 4: AC Simulations4-9 NOTE on dB values – Converting the AC analysis voltage to dB is not the same as S-parameter analysis in dB that uses power (V and I) and also has a 50 ohm source Z.10. Plot the phase and group delay for the ac analysis dataa. Insert a rectangular plot of the phase of Vin and Vout and put markers on 1900 MHz. The phase inversion is not 180 degrees due to the bjt_pkg parasitics. Add markers and you will see that the phase is closer to 180 at lower frequencies. You may want to Hot Key the new marker command using the DDS Options > Hot Key similar to schematic.b. Insert a new equation to calculate group delay . As shown here, use the phase of Vout and the diff function then plot the equation. The diff function calculates the difference between points on the slope. The minus sign gives the result in decreasing value. Place a marker on the trace and notice that it will be on either side of 1900 MHz (+/- 50 MHz) because of the diff function.c. Go back to the schematic, change the step size to 10 MHz , simulate again and watchthe plot update.d. Edit (double click) the marker. In the readout tab, set Format to Engineering with 2 significant digits as shown here - you will see the Y axis value change to pico (pico-seconds)and the X axis resolve to 1.90 GHz.e. OPTIONAL - Try grouping the group delay equation and the plot so they stay together when you move them. Use the Shift key and select the plot and the equation. Then click : Edit > Group . They should now movetogether in the data display.Lab 4: AC Simulations4-10 11. Variable Info and the what function.a. Insert a new list (dataset is still ac_sim ). Add Vout, select it, and click on the Trace Options button. You can do this in a new page if desired or zoom out by 2 for more room on the display.b. When the dialog box appears, click on the Variable Info button and another dialog will appear as shown here. Select the Vout data and you will see that the dependency for Vout is 391 frequency points. This should be the same for all the items in the dataset because only frequency was swept.c. Close the dialog, click OK, and go back to the list of Vout. Insert the cursor in the Vout column and type in the what function as shown: what (Vout). Notice that you get the same variable information. Later on, you will use this function to determine how to index into dataset tables with multiple sweeps or mixing products.NOTE on functions : You can read about the what function and other ADS functions (abs, real, s_stab_circle, etc.) by clicking the Functions Help button whenever you insert an equation in the data display. When the Help browser appears complete, select the MeasEqn Function Reference and scroll down to the function of interest. Try this and look over some of the information to seehow ADS functions are described if you have time.Lab 4: AC Simulations4-11 12. OPTIONAL - Sweep Vcc (as if the battery voltage is decreasing)This step will require you to use the skills you already learned in the previous lab exercises. You will set up a parameter sweep for Vcc from 5 volts to 2 volts in 0.25 volt steps.a. In your schematic, insert a VAR (variable equation) initializing Vbias = 5 volts .b. Redefine the source: Vdc = Vbias .c. Insert a Parameter Sweep from any simulation palette. Then set the SweepVar (sweep variable) to be Vbias . Be sure the Simulation Instance Name of the AC simulation controller is also set as shown here.d. Change the dataset name = ac_bat_swp and Simulate . When the simulation is completed and the DDS opens, a dialog will appear asking if you want to change the dataset – answer NO. Then plot the mag of Vout . A set of curves for each step will appear as shown here.e. To display trace labels of Vbias, edit the trace using the Trace Options tab and check the Display Label box.f.Insert markers as desired.Trace Options used to Display label of Vbias on right of plot. Trace lines canalso be thickened.Lab 4: AC Simulations4-12g. Save all your work .EXTRA EXERCISES :1. In a new design, simulate with port noise and ports. To do this, use a P_AC source as the input port 1(Num=1) and place a Term on the output as port 2 (Num=2). These two components are shown here with the port numbers.2. In a new design, insert an I_AC constant current source and simulate. To do this, you need to put a large resistance in parallel with the source because the simulator needs to verify a dc path to ground and the current sources are open circuits.3. Insert the P_AC source and look at the power gain. Also, sweep another parameter and plot the results.4. Try using the node settings in the AC simulation palette. You can set initial voltages at nodes using the Node Set or by referring to name nodes using the NodeSetByName component.。