单片机外文文献翻译
51单片机英文文献及翻译
Data Memory
数据存储器
Te context with microcontrollers,
术语“数据存储器”用于微控制器。
The memory which stores data,i.e.RAM,is called data memory.
用来存储数据的存储器，即RAM，被称作数据存储器
The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.
8048系列的不同版本的微控制器包含64、128、256字节的RAM。
Data Memory The term data memory is used in the context with microcontrollers,The memory which stores data,i.e.RAM,is called data memory.The diffenent versions of 8048 series of microcontrollers microcontrollers contain 64,128.256 bytes of RAM.The 8048AH,8049AH and 8050AH contain 64,128 and 256 bytes of RAM respectively.64/128/256 bytes of RAM is used either as read/write memory or general-purpose registers.
There is need of cyclical reading (lower than 1 minute periods) of the actual values from the real-time clock and the sensors for pressure and temperature, and to store the read values into the microcontroller’s memory. The communication with the real-time clock and the sensors is possible with the use of I2C interface and the previously defined in the specifications protocols for reading and writing.
单片机方面毕业设计外文文献翻译
中文译文单片机单片机也被称为微控制器（Microcontroller Unit），常用英文字母的缩写MCU表示单片机，它最早是被用在工业控制领域。
单片机由芯片内仅有CPU的专用处理器发展而来。
最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。
INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。
早期的单片机都是8位或4位的。
其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。
此后在8031上发展出了MCS51系列单片机系统。
基于这一系统的单片机系统直到现在还在广泛使用。
随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。
90年代后随着消费电子产品大发展，单片机技术得到了巨大提高。
随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。
而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。
目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端[1]的型号也只有10美元。
当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。
而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。
单片机比专用处理器更适合应用于嵌入式系统，因此它得到了最多的应用。
事实上单片机是世界上数量最多的计算机。
现代人类生活中所用的几乎每件电子和机械产品中都会集成有单片机。
手机、电话、计算器、家用电器、电子玩具、掌上电脑以及鼠标等电脑配件中都配有1-2部单片机。
而个人电脑中也会有为数不少的单片机在工作。
单片机英文文献资料及翻译
单片机英文文献资料及翻译单片机(英文：Microcontroller)Microcontroller is a small computer on a single integrated circuit that contains a processor core, memory, and programmable input/output peripherals. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.A microcontroller's processor core is typically a small, low-power computer dedicated to controlling the operation of the device in which it is embedded. It is often designed to provide efficient and reliable control of simple and repetitive tasks, such as switching on and off lights, or monitoring temperature or pressure sensors.MEMORYMicrocontrollers typically have a limited amount of memory, divided into program memory and data memory. The program memory is where the software that controls the device is stored, and is often a type of Read-Only Memory (ROM). The data memory, on the other hand, is used to store data that is used by the program, and is often volatile, meaning that it loses its contents when power is removed.INPUT/OUTPUTMicrocontrollers typically have a number of programmable input/output (I/O) pins that can be used to interface with external sensors, switches, actuators, and other devices. These pins can be programmed to perform specific functions,such as reading a sensor value, controlling a motor, or generating a signal. Many microcontrollers also support communication protocols like serial, parallel, and USB, allowing them to interface with other devices, including other microcontrollers, computers, and smartphones.APPLICATIONSMicrocontrollers are widely used in a variety of applications, including:- Home automation systems- Automotive electronics- Medical devices- Industrial control systems- Consumer electronics- RoboticsCONCLUSIONIn conclusion, microcontrollers are powerful and versatile devices that have become an essential component in many embedded systems. With their small size, low power consumption, and high level of integration, microcontrollers offer an effective and cost-efficient solution for controlling a wide range of devices and applications.。
单片机英文文献及翻译)
Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。
单片机英文文献及翻译
附录A英文文献翻译原文Temperature Control Using a Microcontroller:An Interdisciplinary Undergraduate Engineering Design ProjectJames S. McDonaldDepartment of Engineering ScienceTrinity UniversitySan Antonio, TX 78212AbstractThis paper describes an interdisc iplinary design project which was done under the author’s supervision by a group of four senior students in the Department of Engineering Science at Trinity University. The objective of the project was to develop a temperature control system for an air-filled chamber. The system was to allow entry of a desired chamber temperature in a prescribed range and to exhibit overshoot and steady-state temperature error of less than 1 degree Kelvin in the actual chamber temperature step response. The details of the design developed by this group of students, based on a Motorola MC68HC05 family microcontroller, are described. The pedagogical value of the problem is also discussed through a description of some of the key steps in the design process. It is shown that the solution requires broad knowledge drawn from several engineering disciplines including electrical, mechanical, and control systems engineering.1 IntroductionThe design project which is the subject of this paper originated from a real-world application.A prototype of a microscope slide dryer had been developed around an OmegaTM modelCN-390 temperature controller, and the objective was to develop a custom temperature control system to replace the Omega system. The motivation was that a custom controller targeted specifically for the application should be able to achieve the same functionality at a much lower cost, as the Omega system is unnecessarily versatile and equipped to handle a wide variety of applications.The mechanical layout of the slide dryer prototype is shown in Figure 1. The main element of the dryer is a large, insulated, air-filled chamber in which microscope slides, each with a tissue sample encased in paraffin, can be set on caddies. In order that the paraffin maintain the proper consistency, the temperature in the slide chamber must be maintained at a desired (constant) temperature. A second chamber (the electronics enclosure) houses a resistive heater and the temperature controller, and a fan mounted on the end of the dryer blows air across theheater, carrying heat into the slide chamber. This design project was carried out during academic year 1996–97 by four students under the author’s supervision as a Senior Design project in the Department of Engineering Science at Trinity University. The purpose of this paper isto describe the problem and the students’ solution in some detail, and to discuss some of the pedagogical opportunities offered by an interdisciplinary design project of this type. The students’ own report was presented a t the 1997 National Conference on Undergraduate Research [1]. Section 2 gives a more detailed statement of the problem, including performance specifications, and Section 3 describes the students’ design. Section 4 makes up the bulk of the paper, and discusses in some detail several aspects of the design process which offer unique pedagogical opportunities. Finally, Section 5 offers some conclusions.2 Problem StatementThe basic idea of the project is to replace the relevant parts of the functionality of an Omega CN-390 temperature controller using a custom-designed system. The application dictates that temperature settings are usually kept constant for long periods of time, but it’s nonetheless important that step changes be tracked in a “reasonable” manner. Thus the main requirements boil down to·allowing a chamber temperature set-point to be entered,·displaying both set-point and actual temperatures, and·tracking step changes in set-point temperature with acceptable rise time, steady-state error, and overshoot.Although not explicitly a part of the specifications in Table 1, it was clear that the customer desired digital displays of set-point and actual temperatures, and that set-point temperature entry should be digital as well (as opposed to, say, through a potentiometer setting).3 System DesignThe requirements for digital temperature displays and setpoint entry alone are enough to dictate that a microcontrollerbased design is likely the most appropriate. Figure 2 shows a block diagram of the stude nts’ design.The microcontroller, a MotorolaMC68HC705B16 (6805 for short), is the heart of the system. It accepts inputs from a simple four-key keypad which allow specification of the set-point temperature, and it displays both set-point and measured chamber temperatures using two-digit seven-segment LED displays controlled by a display driver. All these inputs and outputs are accommodated by parallel ports on the 6805. Chamber temperature is sensed using apre-calibrated thermistor and input via one of the 6805’s analog-to-digital inputs. Finally, a pulse-width modulation (PWM) output on the 6805 is used to drive a relay which switches line power to the resistive heater off and on.Figure 3 shows a more detailed schematic of the electronics and their interfacing to the 6805. The keypad, a Storm 3K041103, has four keys which are interfaced to pins PA0{ PA3 of Port A, configured as inputs. One key functions as a mode switch. Two modes are supported: set mode and run mode. In set mode two of the other keys are used to specify the set-point temperature: one increments it and one decrements. The fourth key is unused at present. The LED displays are driven by a Harris Semiconductor ICM7212 display driver interfaced to pins PB0{PB6 of Port B, configured as outputs. The temperature-sensing thermistor drives, through a voltage divider, pin AN0 (one of eight analog inputs). Finally, pin PLMA (one of two PWM outputs) drives the heater relay.Software on the 6805 implements the temperature control algorithm, maintains the temperature displays, and alters the set-point in response to keypad inputs. Because it is not complete at this writing, software will not be discussed in detail in this paper. The control algorithm in particular has not been determined, but it is likely to be a simple proportional controller and certainly not more complex than a PID. Some control design issues will be discussed in Section 4, however.4 The Design ProcessAlthough essentially the project is just to build a thermostat, it presents many nice pedagogical opportunities. The knowledge and experience base of a senior engineering undergraduate are just enough to bring him or her to the brink of a solution to various aspects of the problem. Yet, in each case, realworld considerations complicate the situation significantly.Fortunately these complications are not insurmountable, and the result is a very beneficial design experience. The remainder of this section looks at a few aspects of the problem which present the type of learning opportunity just described. Section 4.1 discusses some of the features of a simplified mathematical model of the thermal properties of the system and how it can beeasily validated experimentally. Section 4.2 describes how realistic control algorithm designs can be arrived at using introductory concepts in control design. Section 4.3 points out some important deficiencies of such a simplified modeling/control design process and how they can be overcome through simulation. Finally, Section 4.4 gives an overview of some of the microcontroller-related design issues which arise and learning opportunities offered.4.1 MathematicalModelLumped-element thermal systems are described in almost any introductory linear control systems text, and just this sort of model is applicable to the slide dryer problem. Figure 4 shows a second-order lumped-element thermal model of the slide dryer. The state variables are the temperatures Ta of the air in the box and Tb of the box itself. The inputs to the system are the power output q(t) of the heater and the ambient temperature T¥. ma and mb are the masses of the air and the box, respectively, and Ca and Cb their specific heats. μ1 and μ2 are heat transfer coefficients from the air to the box and from the box to the external world, respectively.It’s not hard to show that the (linearized) state equationscorresponding to Figure 4 areTaking Laplace transforms of (1) and (2) and solving for Ta(s), which is the output of interest, gives the following open-loop model of the thermal system:where K is a constant and D(s) is a second-order polynomial.K, tz, and the coefficients ofD(s) are functions of the variousparameters appearing in (1) and (2).Of course the various parameters in (1) and (2) are completely unknown, but it’s not hard to show that, regardless of their values, D(s) has two real zeros. Therefore the main transfer function of interest (which isthe one from Q(s), since we’ll assume constant ambient temperature) can be writtenMoreover, it’s not too hard to show that 1=tp1 <1=tz <1=tp2, i.e., that the zero lies between the two poles. Both of these are excellent exercises for the student, and the result is the openloop pole-zero diagram of Figure 5.Obtaining a complete thermal model, then, is reduced to identifying the constant K and the three unknown time constants in (3). Four unknown parameters is quite a few, but simple experiments show that 1=tp1 _ 1=tz;1=tp2 so that tz;tp2 _ 0 are good approximations. Thus the open-loop system is essentially first-order and can therefore be written(where the subscript p1 has been dropped).Simple open-loop step response experiments show that,for a wide range of initial temperatures and heat inputs, K _0:14 _=W and t _ 295 s.14.2 Control System DesignUsing the first-order model of (4) for the open-loop transfer function Gaq(s) and assuming for the moment that linear control of the heater power output q(t) is possible, the block diagram of Figure 6 represents the closed-loop system. Td(s) is the desired, or set-point, temperature,C(s) is the compensator transfer function, and Q(s) is the heater output in watts.Given this simple situation, introductory linear control design tools such as the root locus method can be used to arrive at a C(s) which meets the step response requirements on rise time, steady-state error, and overshoot specified in Table 1. The upshot, of course, is that a proportional controller with sufficient gain can meet all specifications. Overshoot is impossible, and increasing gains decreases both steady-state error and rise time.Unfortunately, sufficient gain to meet the specifications may require larger heat outputs than the heater is capable of producing. This was indeed the case for this system, and the result is that the rise time specification cannot be met. It is quite revealing to the student how useful such an oversimplified model, carefully arrived at, can be in determining overall performance limitations.4.3 Simulation ModelGross performance and its limitations can be determined using the simplified model of Figure 6, but there are a number of other aspects of the closed-loop system whose effects on performance are not so simply modeled. Chief among these are·quantization error in analog-to-digital conversion of the measured temperature and· the use of PWM to control the heater.Both of these are nonlinear and time-varying effects, and the only practical way to study them is through simulation (or experiment, of course).Figure 7 shows a SimulinkTM block diagram of the closed-loop system which incorporates these effects. A/D converter quantization and saturation are modeled using standard Simulink quantizer and saturation blocks. Modeling PWM is more complicated and requires a customS-function to represent it.This simulation model has proven particularly useful in gauging the effects of varying thebasic PWM parameters and hence selecting them appropriately. (I.e., the longer the period, the larger the temperature error PWM introduces. On the other hand, a long period is desirable to avoid excessiv e relay “chatter,” among other things.) PWM is often difficult for students to grasp, and the simulation model allows an exploration of its operation and effects which is quite revealing.4.4 The MicrocontrollerSimple closed-loop control, keypad reading, and display control are some of the classic applications of microcontrollers, and this project incorporates all three. It is therefore an excellent all-around exercise in microcontroller applications. In addition, because the project isto produce an actua l packaged prototype, it won’t do to use a simple evaluation board with theI/O pins jumpered to the target system. Instead, it’s necessary to develop a complete embedded application. This entails the choice of an appropriate part from the broad range offered in a typical microcontroller family and learning to use a fairly sophisticated development environment. Finally, a custom printed-circuit board for the microcontroller and peripherals must be designed and fabricated.Microcontroller Selection. In view of existing local expertise, the Motorola line of microcontrollers was chosen for this project. Still, this does not narrow the choice down much. A fairly disciplined study of system requirements is necessary to specify which microcontroller, out of scores of variants, is required for the job. This is difficult for students, as they generally lack the experience and intuition needed as well as the perseverance to wade through manufacturers’ selection guides.Part of the problem is in choosing methods for interfacing the various peripherals (e.g., what kind of display driver should be used?). A study of relevant Motorola application notes [2, 3, 4] proved very helpful in understandingwhat basic approaches are available, and what microcontroller/peripheral combinations should be considered.The MC68HC705B16 was finally chosen on the basis of its availableA/D inputs and PWMoutputs as well as 24 digital I/O lines. In retrospect this is probably overkill, as only oneA/D channel, one PWM channel, and 11 I/O pins are actually required (see Figure 3). The decision was made to err on the safe side because a complete development system specific to the chosen part was necessary, and the project budget did not permit a second such system to be purchased should the firstprove inadequate.Microcontroller Application Development. Breadboarding of the peripheral hardware, development of microcontroller software, and final debugging and testing of a customprinted-circuit board for the microcontroller and peripherals all require a development environment of some kind. The choice of a development environment, like that of themicrocontroller itself, can be bewildering and requires some faculty expertise. Motorola makes three grades of development environment ranging from simple evaluation boards (at around $100) to full-blown real-time in-circuit emulators (at more like $7500). The middle option was chosen for this project: the MMEVS, which consists of _ a platform board (which supports all 6805-family parts), _ an emulator module (specific to B-series parts), and _ a cable and target head adapter (package-specific). Overall, the system costs about $900 and provides, with some limitations, in-circuit emulation capability. It also comes with the simple but sufficient software development environment RAPID [5].Students find learning to use this type of system challenging, but the experience they gain in real-world microcontroller application development greatly exceeds the typical first-course experience using simple evaluation boards.Printed-Circuit Board. The layout of a simple (though definitely not trivial) printed-circuit board is another practical learning opportunity presented by this project. The final board layout, with package outlines, is shown (at 50% of actual size) in Figure 8. The relative simplicity of the circuit makes manual placement and routing practical—in fact, it likely gives better results than automatic in an application like this—and the student is therefore exposed to fundamental issues of printed-circuit layout and basic design rules. The layout software used was the very nice package pcb,2 and the board was fabricated in-house with the aid of our staff electronics technician.5 ConclusionThe aim of this paper has been to describe an interdisciplinary, undergraduate engineering design project: a microcontroller- based temperature control system with digital set-point entry and set-point/actual temperature display. A particular design of such a system has been described, and a number of design issues which arise—from a variety of engineering disciplines—have been discussed. Resolution of these issues generally requires knowledge beyond that acquired in introductory courses, but realistically accessible to advance undergraduate students, especiallywith the advice and supervision of faculty.Desirable features of the problem, from a pedagogical viewpoint, include the use of a microcontroller with simple peripherals, the opportunity to usefully apply introductorylevel modeling of physical systems and design of closed-loop controls, and the need for relatively simple experimentation (for model validation) and simulation (for detailed performance prediction). Also desirable are some of the technologyrelated aspects of the problem including practical use of resistive heaters and temperature sensors (requiring knowledge of PWM and calibration techniques, respectively), microcontroller selection and use of development systems, and printedcircuit design.AcknowledgementsThe author would like to acknowledge the hard work, dedication, and ability shown by the students involved in this project: Mark Langsdorf, Matt Rall, PamRinehart, and David Schuchmann. It is their project, and credit for its success belongs to them.References[1] M. Langsdorf, M. Rall, D. Schuchmann, and P. Rinehart,“Temperature control of a microscope slide dryer,” in1997 National Conference on Undergraduate Research,(Austin, TX), April 1997. Poster presentation.[2] Motorola, Inc., Phoenix, AZ, Temperature Measurementand Display Using the MC68HC05B4 and the MC14489,1990. Motorola SemiconductorApplicationNote AN431.[3] Motorola, Inc., Phoenix, AZ, HC05 MCU LED DriveTechniques Using the MC68HC705J1A, 1995. MotorolaSemiconductor Application Note AN1238.[4] Motorola, Inc., Phoenix, AZ, HC05MCU Keypad DecodingTechniques Using the MC68HC705J1A, 1995. MotorolaSemiconductor Application Note AN1239.[5] Motorola, Inc., Phoenix, AZ, RAPID Integrated DevelopmentEnvironment User’s Manual, 1993. (RAPID wasdeveloped by P & E Microcomputer Systems, Inc.).附录B英文文献翻译中文单片机温度控制：一个跨学科的本科生工程设计项目JamesS.McDonald工程科学系三一大学德克萨斯州圣安东尼奥市78212摘要本文所描述的是作者领导由四个三一大学高年级学生组成的团队进行的一个跨学科工程项目的设计。
单片机基础外文翻译参考文献
单片机基础外文翻译参考文献(文档含中英文对照即英文原文和中文翻译)原文:Fundamentals of Single-chip MicrocomputerDr. Dobbs MacintoshJournalAbstractT h e s i n gl e-chi p m i c r o com pu t er i s t h e cul m i na t i on of bo t h t h e d e v el opm e nt o f t h e di gi t al c om p ut e r a nd t h e i nt e gra t e d c i r c ui t a rgu a b l y t h e t ow m o s t s i gn i fi c ant i nv en t i on s of t h e 20t h ce n t u r y .T h es e t o w t yp e s o f a rc hi t e c t u r e a r e fo un d i n s i n gl e-c hi pm i c r o com pu t e r.S om e e m p l o y t h e s pl i t p ro gr a m/d at a m em o r y o f t h e H a r v a rd a r ch i t e ct u r e, s ho wn i n F i g.3-5A-1, ot h er s f o l l o w t h e p hi l o so ph y,w i d e l y a d a p t ed f o r ge n e r al-pu rp os e com p ut e rs an d m i c r op r oc e s s o rs,of m ak i n g n o l o gi c al di s t i nc t i on be t w ee n p ro gr a m a n d d at a m em o r y a s i n t h e P r i n c et on ar c hi t e ct u r e.In ge n e r a l t er m s a si n gl e-c hi p m i cro c om put e r i s c ha r ac t e ri z ed b y t h e i n co r po r at i o n o f al l t h e u ni t s o f a c om put e r i n t o a s i n gl e d e vi c e.Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory– Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 128 x 8-bit Internal RAM• 32 Programmable I/O Lines• Two 16-bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low-power Idle and Power-down ModesDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. Theon-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded controlapplications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-orderaddress bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programmingand verification.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When theAT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes programexecution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsFigure 2. External Clock Drive ConfigurationPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operatio n must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erasedby using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.译文:单片机基础摘要：单片机是电脑和集成电路发展的巅峰，有据可查的是它们也是20世纪最意义的两大发明。
单片机-毕业论文外文文献翻译
单片机单片机也被称为微控制器（Microcontroller Unit），常用英文字母的缩写MCU 表示单片机，它最早是被用在工业控制领域。
单片机由芯片内仅有CPU的专用处理器发展而来。
最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。
INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。
早期的单片机都是8位或4位的。
其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。
此后在8031上发展出了MCS51系列单片机系统。
基于这一系统的单片机系统直到现在还在广泛使用。
随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。
90年代后随着消费电子产品大发展，单片机技术得到了巨大提高。
随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。
而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。
目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。
当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。
而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。
单片机比专用处理器更适合应用于嵌入式系统，因此它得到了最多的应用。
事实上单片机是世界上数量最多的计算机。
现代人类生活中所用的几乎每件电子和机械产品中都会集成有单片机。
手机、电话、计算器、家用电器、电子玩具、掌上电脑以及鼠标等电脑配件中都配有1-2部单片机。
而个人电脑中也会有为数不少的单片机在工作。
汽车上一般配备40多部单片机，复杂的工业控制系统上甚至可能有数百台单片机在同时工作！单片机的数量不仅远超过PC机和其他计算的总和，甚至比人类的数量还要多。
单片机外文文献翻译(2024)
引言：单片机（Microcontroller）是一种广泛应用于嵌入式系统中的小型计算机芯片。
它集成了处理器核心、存储器、外设接口和时钟电路等核心部件，可以独立运行。
随着全球化的发展，外文文献对于学习和研究单片机领域来说至关重要。
本文翻译的外文文献《MicrocontrollerbasedTrafficLightControlSystem》详细介绍了基于单片机的交通信号灯控制系统。
概述：交通信号灯控制是现代都市交通系统中至关重要的一环。
传统的交通信号灯控制系统通常由定时器控制，不能根据实际交通情况动态调整信号灯的时间。
而基于单片机的交通信号灯控制系统可以实现根据实时交通流量来动态调整信号灯的时间，优化交通效率。
本文将详细介绍该系统的设计和实现。
正文：一、单片机选型1.1.CPU性能：本文选择了一款高性能的32位单片机作为控制核心，它具有较高的处理能力和较大的存储器容量，可以同时处理多条交通路口的信号控制。
1.2.外设接口：该单片机具有丰富的外设接口，可以与交通信号灯、传感器和通信设备等进行连接，实现信号控制和数据交互。
1.3.低功耗设计：为了节约能源和延长系统寿命，在单片机选型时考虑了低功耗设计，降低系统运行的能耗。
二、硬件设计2.1.交通信号灯：在设计交通信号灯时，考虑了日夜可见性和能耗。
采用了高亮度LED作为信号灯光源，同时添加了光敏传感器控制信号灯的亮度，以满足不同时间段的亮度需求。
2.2.传感器：通过安装车辆感应器和行人感应器等传感器，可以在实时监测交通流量的基础上，智能调整信号灯时间，提高路口的交通效率。
2.3.通信设备：在交通信号灯控制系统中引入了通信设备，可以实现各交通路口之间的信息交互和协调控制，提高整体交通系统的效率。
三、软件设计3.1.程序架构：采用了多任务的实时操作系统，将交通信号灯控制、传感器数据处理和通信设备控制等功能分别封装成不同的任务，实现了系统的高效运行和任务调度。
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外文文献一单片机简介单片机是一种集成在电路芯片，是采用超大规模集成电路技术把具有数据处理能力的中央处理器CPU随机存储器RAM、只读存储器ROM、多种I/O口和中断系统、定时器/计时器等功能（可能还包括显示驱动电路、脉宽调制电路、模拟多路转换器、A/D转换器等电路）集成到一块硅片上构成的一个小而完善的计算机系统。
单片机也被称为微控制器（Microcontroller），是因为它最早被用在工业控制领域。
单片机由芯片内仅有CPU的专用处理器发展而来。
最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。
INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。
二、单片机的发展趋势现在可以说单片机是百花齐放，百家争鸣的时期，世界上各大芯片制造公司都推出了自己的单片机，从8位、16位到32位，数不胜数，应有尽有，有与主流C51系列兼容的，也有不兼容的，但它们各具特色，互成互补，为单片机的应用提供广阔的天地。
纵观单片机的发展过程，可以预示单片机的发展趋势，大致有：1.低功耗CMOSMCS-51系列的8031推出时的功耗达630mW，而现在的单片机普遍都在100mW左右，随着对单片机功耗要求越来越低，现在的各个单片机制造商基本都采用了CMOS(互补金属氧化物半导体工艺)。
象80C51就采用了HMOS(即高密度金属氧化物半导体工艺)和CHMOS(互补高密度金属氧化物半导体工艺)。
CMOS虽然功耗较低，但由于其物理特征决定其工作速度不够高，而CHMOS则具备了高速和低功耗的特点，这些特征，更适合于在要求低功耗象电池供电的应用场合。
所以这种工艺将是今后一段时期单片机发展的主要途径。
2.微型单片化现在常规的单片机普遍都是将中央处理器(CPU)、随机存取数据存储(RAM)、只读程序存储器(ROM)、并行和串行通信接口，中断系统、定时电路、时钟电路集成在一块单一的芯片上，增强型的单片机集成了如A/D转换器、PMW(脉宽调制电路)、WDT(看门狗)、有些单片机将LCD(液晶)驱动电路都集成在单一的芯片上，这样单片机包含的单元电路就更多，功能就越强大。
甚至单片机厂商还可以根据用户的要求量身定做，制造出具有自己特色的单片机芯片。
此外，现在的产品普遍要求体积小、重量轻，这就要求单片机除了功能强和功耗低外，还要求其体积要小。
现在的许多单片机都具有多种封装形式，其中SMD(表面封装)越来越受欢迎，使得由单片机构成的系统正朝微型化方向发展。
3.主流与多品种共存现在虽然单片机的品种繁多，各具特色，但仍以80C51为核心的单片机占主流，兼容其结构和指令系统的有PHILIPS公司的产品，ATMEL公司的产品和中国台湾的Winbond 系列单片机。
所以C8051为核心的单片机占据了半壁江山。
而Microchip公司的PIC精简指令集(RISC)也有着强劲的发展势头，中国台湾的HOLTEK公司近年的单片机产量与日俱增，与其低价质优的优势，占据一定的市场分额。
此外还有MOTOROLA公司的产品，日本几大公司的专用单片机。
在一定的时期内，这种情形将得以延续，将不存在某个单片机一统天下的垄断局面，走的是依存互补，相辅相成、共同发展的道路。
三、仿真器的发展纵观国内近二十年的仿真技术发展历程，根据仿真器使用的技术来划分，国内仿真器的设计大约可以分成以下几个时期：(1) 70年代末期-80年代中期这个时期采用的技术主要是仿真开发系统，现在看来技术含量不高，用户要求也不高。
(2) 80年代末期-90年代末期这个时期主要使用华邦一颗带有仿真功能的芯片制作，采用的技术叫做Bondout。
采用这颗芯片能大大简化仿真器的设计，因此国内仿真器的水准有了大的提高，基本上可以不占用用户资源。
正是由于仿真性能的提高，国内的仿真器制作在将近10年的时间内没有进步，一直采用这种制作模式。
虽然个别厂商也尝试过别的技术来提高仿真水准，例如HOOKS技术，但是由于本身技术的限制没有成功。
相反国外的仿真器较早地使用了HOOKS技术，在初期由于HOOKS技术本身的复杂性，仿真性能和价格不如国内采用Bondout的仿真器。
随着IC技术的发展，国内制作HOOKS技术的条件已经成熟，但是国内的几家主要的生产厂商还陶醉于Bondout技术之中。
(3) 2000年开始2000年是中国仿真器市场变化最大的时期，其中最引人注目的变化是华邦仿真芯片W78958的停产。
华邦公司在设计W78958芯片时，其内部的仿真功能只是为了仿真器厂商能制作仿真器以便更好的推广W78958。
但是经过几年的变化，W78958演变成为一颗仿真器上使用的仿真专用芯片而不是用户使用的标准芯片，使用的范围也仅限于国内，一年不到20000只的用量也促使华邦公司在进入2002年后宣布将停产该芯片。
W78958停产以后，国内仿真器厂商处于一个非常尴尬的局面。
由于W78958在国内使用了将近10年，国内的用户群非常庞大，这些用户将无法得到持续的支持特别是维修方面。
另外，国内围绕在W78958上所做的技术工作也无法得到延续和提高，很多业界人士认为仿真器行业将面临另起炉灶或重新洗牌的局面。
HOOKS技术无疑是仿真器厂商在失去W78958后的替代品，但是由于没有长期跟踪和关注，短期内多数厂家无法将复杂的HOOKS技术应用于成熟的产品中。
专家们认为仿真器厂家的整体转型可能需要2－3年的周期，并且有相当的仿真器厂家将会被淘汰，市场拥有量将主要集中在少数几个仿真器厂家。
随着芯片厂家越来越多、资源越来越强，用甲厂芯片去仿真乙厂芯片的兼容仿真模式，存在资源覆盖不全(如附加端口、附加外部中断)、地址分布不同(如P4口)、操作方式不同(如EXTRAM、WTD)等缺点。
用专用仿真芯片或Philips芯片去仿真20多个厂家的400多种芯片，所需的仿真头越来越多，因此有了新一代专利技术的仿真器。
但是新一代专利技术的仿真器却使没有什么经济能力的初学者无力购买。
四、以单片机为核心的嵌入式系统单片机的另外一个名称就是嵌入式微控制器，原因在于它可以嵌入到任何微型或小型仪器或设备中。
目前，把单片机嵌入式系统和Internet连接已是一种趋势。
但是，Internet一向是一种采用肥服务器，瘦用户机的技术。
这种技术在互联上存储及访问大量数据是合适的，但对于控制嵌入式器件就成了"杀鸡用牛刀"了。
要实现嵌入式设备和Int ernet连接，就需要把传统的Internet理论和嵌入式设备的实践都颠倒过来。
为了使复杂的或简单的嵌入式设备，例如单片机控制的机床、单片机控制的门锁，能切实可行地和Internet连接，就要求专门为嵌入式微控制器设备设计网络服务器，使嵌入式设备可以和Internet相连，并通过标准网络浏览器进行过程控制。
目前，为了把单片机为核心的嵌入式系统和Internet相连，已有多家公司在进行这方面的较多研究。
这方面较为典型的有emWare公司和TASKING公司。
EmWare公司提出嵌入式系统入网的方案--EMIT技术。
这个技术包括三个主要部分：即emMicro，emGateway和网络浏览器。
目前，单片机应用中提出了一个新的问题：这就是如何使8位、16位单片机控制的产品，也即嵌入式产品或设备能实现和互联网互连？ TASKING 公司目前正在为解决这个问题提供了途径。
该公司已把emWare的EMIT软件包和有关的软件配套集成，形成一个集成开发环境，向用户提供开发方便。
五单片机应用的可靠性技术发展在单片机应用中，可靠性是首要因素为了扩大单片机的应用范围和领域，提高单片机自身的可靠性是一种有效方法。
近年来，单片机的生产厂家在单片机设计上采用了各种提高可靠性的新技术，这些新技术表现在如下几点：1、EFT（Ellectrical Fast Transient）技术EFT技术是一种抗干扰技术，它是指在振荡电路的正弦信号受到外界干扰时，其波形上会迭加各种毛刺信号，如果使用施密特电路对其整形，则毛刺会成为触发信号干扰正常的时钟，在交替使用施密特电路和RC滤波电路时，就可以消除这些毛否则令其作用失效，从而保证系统的时钟信号正常工作。
这样，就提高了单片机工作的可靠性。
Motorola 公司的 MC68HC08系列单片机就采用了这种技术。
低噪声布线技术及驱动技术在传统的单片机中，电源及地线是在集成电路外壳的对称引脚上，一般是在左上、右下或右上、左下的两对对称点上。
这样，就使电源噪声穿过整块芯片，对单片机的内部电路造成干扰。
现在，很多单片机都把地和电源引脚安排在两条相邻的引脚上。
这样，不仅降低了穿过整个芯片的电流，另外还在印制电路板上容易布置去耦电容，从而降低系统的噪声。
现在为了适应各种应用的需要，很多单片机的输出能力都有了很大提高，Motorola公司的单片机I/O口的灌拉电流可达8mA以上，而Microchip公司的单片机可达25mA。
其它公司：AMD，Fujitsu，NEC ，Infineon，Hitachi，Ateml，Tosbiba等基本上可达8～20mA的水平。
这些电流较大的驱动电路集成到芯片内部在工作时带来了各种噪声，为了减少这种影响，现在单片机采用多个小管子并联等效一个大管子的方法，并在每个小管子的输出端串上不同等效阻值的电阻，以降低di/dt，这也就是所谓"跳变沿软化技术"，从而消除大电流瞬变时产生的噪声。
2、采用低频时钟高频外时钟是噪声源之一，不仅能对单片机应用系统产生干扰，还会对外界电路产生干扰，令电磁兼容性不能满足要求。
对于要求可靠性较高的系统，低频外时钟有利于降低系统的噪声。
在一些单片机中采用内部琐相环技术，则在外部时钟较低时，也能产生较高的内部总线速度，从而保证了速度又降低了噪声。
Motorola公司的MC68HC08系列及其1 6/32位单片机就采用了这种技术以提高可靠性Foreign documents一 Microcontroller introductionSCM is A kind of integrated circuit chips, is to use very large scale integrated circuit technology has the ability to handle data CPU CPU, RAM random access memory read only memory ROM, A variety of I/O mouth and interrupt system, timer/timer function (may include display driver circuit, pulse width modulation circuit, simulation way more converter, A/D converter circuits, etc) integrated into one of these forms of A small and perfect computer system.SCM is also called micro controller (Microcontroller), because it was the first used in the industrial control area. By chip microcontroller within the CPU only dedicated processor. The first design concept is through the huge amounts of peripheral and CPU integration in a chip, make the computer system more small, more easily integrated into the complex and demanding to volume control of equipment. The INTEL Z80 is the earliest according to this design thought of the processor, and from then on, SCM and dedicated processor development and separate.二 The development trend of the single chip microcomputerNow can say MCU is let flowers blossom and schools of thought contend period, the world each big chip manufacturing companies have launched their own microcontroller, from 8 bits, 16 to 32 bit, countless, everything, and the mainstream C51 series compatible, also have compatible, but they have their special features, complementary to each other, for the application of the single chip microcomputer provide vast heaven and earth.Throughout the development process of single chip microcomputer, predicts the development trend of the single chip microcomputer, roughly:1．Low power consumption CMOSMCS-51 series of 8031 when the power consumption of the launch of the 630 mW, but now the single chip microcomputer universal in 100 mW or so, as the SCM power consumption demand more and more low, each single chip manufacturers now basic using CMOS (complementary metal oxide semiconductor process). Like 80 C51 had adopted HMOS (namely high density metal oxide semiconductor technology) and CHMOS (high density complementary metal oxide semiconductor process). Though low power consumption CMOS, but because of its physical characteristics to determine the speed of work is not quite high, and CHMOS is the high speed and have the characteristics of low power consumption, these characteristics and is more suitable for low power consumption in demand like battery power applications. So this process will be for a period of the development of the single chip microcomputer main ways2．Miniature sheet piece ofNow the single chip microcomputer universal conventional is will the central processing unit (CPU), random access memory (RAM), data read only memory (ROM)program, parallel and serial communication interface, the interrupt system, regular circuit, clocking circuit integration in A single chip, enhanced the single chip micro computer integrated as A/D converter, PMW (pulse width modulation circuit), WDT (watchdog), some SCM LCD (LCD) will drive circuit are integrated in A single chip, this single chip unit circuit will contain more, function, the stronger you will be. Even single chip manufacturer still can be customized according to the user's requirements, make its own characteristics of single chip microcomputer chip. In addition, the products now universal demand small volume, light weight, which requires the single-chip microcomputer besides function is strong and low power consumption, but also to ask its volume to small. Many of the single chip microcomputer now has a variety of packaging forms, including SMD surface packaging) has become more and more popular, makes the system constructed by single-chip microcomputer is the development direction in miniaturization. 3．The mainstream and many kinds of coexistenceNow, while the single chip microcomputer variety, each characteristic, but still with 80 C51 single chip microcomputer as the core of the mainstream, compatible with its structure and instructions of the system PHILIPS products, ATMEL company products and China Taiwan's Winbond series microcontroller. So as the core of the single chip microcomputer occupy C8051 heavily-accented screams. Microchip company and the PIC reduced instruction set (RISC) also have a strong momentum of development, China and Taiwan HOLTEK company in recent years of the single chip micro computer output grows day by day, and the advantages of high quality and low price, takes up the market share. In addition to MOTOROLA the product of the company, a few big companies for the Japanese microcontroller. In a certain period of time, this kind of situation will to continue, there won't be a single chipmicrocomputer skillfulness of monopoly situation, go is dependent complementary, supplement each other and common development road.三The development of the simulatorThroughout the domestic nearly 20 years of simulation technology development course, according to the simulation implement use technology to differentiate, the design of the domestic simulator can be divided into the following several period about:(1) 70 s-the mid 80'sThis period is mainly the adopted technology of the simulation system development, and now it is not high technical content, user requirements is not high also.(2) the 80 s-90 sThis period mainly use HuaBang a simulation of production function with chip, using technology called Bondout. Adopting the single chip can greatly simplified the design of the simulation system, therefore the domestic simulators level have improved, basically can do not take up the user resources.It is due to the improvement of the performance of the simulation, the domestic simulator in nearly 10 years of making time no progress, has been using this kind of production mode. Although individual manufacturer has also tried other technology to improve simulation level, such as HOOKS technology, but because of its technical limitations without success. Instead of foreign simulators early use HOOKS technology, in early because of the complexity of the HOOKS technology itself, the simulation performance and price as the domestic Bondout simulation device.Along with the IC technology development, the domestic production of the HOOKStechnology conditions ripe, but domestic several major production manufacturer still lose themselves in Bondout technology in.(3) started in 20002000 is the Chinese simulators market change is the biggest period, one of the most dramatic change is HuaBang simulation chip W78958 shut-down.Sinocon corp. In W78958 chip design, its internal simulation function just for simulators manufacturers can make simulator in order to better promote W78958. But after years of change, W78958 evolved into a simulation device on the use of the special chip simulation and not users with the use of the standard chip, the scope of use for domestic, less than a year the dosage of only 20000 prompted sinocon corp. In the 2002 years later announced it will stop production the chip.W78958 after production, domestic simulation device manufacturers in a very embarrassing situation. Because in the domestic use W78958 nearly 10 years, domestic user group of very large, these users will not be able to get the ongoing support especially maintenance. In addition, China has done in W78958 around the technical work will be given continue and improve, many professionals think simulators industry will face the drawing board or to shuffling of the situation. HOOKS technology is undoubtedly simulator in W78958 lost after the manufacturer substitute, but with no long-term tracking and attention, the short term most manufacturers can't will complex HOOKS technology applied to mature product. Experts think the whole transformation of the manufacturer may need to 2-3 year cycle, and so is the simulation of the factory will be eliminated, the market will be mainly the ownership in a few simulation device manufacturers.As the more and more manufacturers, resource is more and more strong, with JiaChang chip to the simulation YiChang chips compatible simulation model, existingresources does not cover all (such as additional port, additional external interruption), address distribution different (such as P4 mouth), the operation mode different (such as EXTRAM, WTD) shortcomings. Use special simulation chip or Philips chip to the simulation of a variety of more than 20 factory 400 chip, the simulation head is more and more, so have a new generation of patent technology emulator.But a new generation of patent technology of the simulator will make no economic ability unable to buy the beginners.四With the single chip processor as the core of the embedded systemSCM another name is embedded microcontroller controller, the reason is that it can be embedded into any miniature or small instrument or equipment. At present, the single chip embedded system and Internet connection is a kind of trend. But, the Internet has always been a server with fat, thin users machine technology. The technology of the Internet in the storage and access to large amounts of data is appropriate, but for control embedded devices became "kill chicken por muson mortigi oni pafiloro ne uzas". To realize the embedded equipment and Int ernet connection, it needs to put the traditional Internet theory and the practice of embedded system is upside down. In order to make the complex or simple embedded devices, such as single chip microcomputer control machine tools, single chip microcomputer control locks, can feasible and Internet connection, it requires special equipment for embedded microcontroller controller design web server, make embedded devices can be and Internet connected, and through the standard web browser process control.At present, in order to put the single chip microcomputer as the core of the embeddedsystem and Internet connected, has had a lot of companies in the more research. This aspect of the typical have emWare company and TASKING company. EmWare company to put forward the embedded system of the program-the net EMIT technology. This technology includes three main parts: that is emMicro, emGateway and a web browser. At present, the SCM put forward a new problem: this is how to make eight, 16 single-chip microcomputer control products, namely embedded products or equipment can realize interconnection and the Internet? TASKING company is currently to solve this problem provides way. The company has the emWare EMIT the software package and relevant software integration of form a complete set, forming an integrated development environment, to facilitate the development of the users.五 The reliability of the microcomputer application technology developmentIn the single chip microcomputer applications, the reliability is the primary factor in order to expand the application range of the single chip microcomputer and field, improve the reliability of the single chip microcomputer itself is a kind of effective method. In recent years, the single chip manufacturers in the design of the single chip microcomputer to improve reliability of the new technology, the new technology performance in the following:（1） EFT (Ellectrical Fast Transient) technologyEFT technology is a kind of anti-interference technology, it is to point to in the oscillating circuit by the sine signal interference, the waveform superposition of burr signal will, if use the plastic schmidt circuit, the burr would be triggered signals interferes with normal clock, in the alternate use schmidt circuit and the RC filter circuit, can eliminate the hair or make its function failure to ensure system clock signal normal work. So, improve thereliability of the single chip microcomputer. Motorola company MC68HC08 series microcontroller adopt the technology. Low noise wiring technology and drive technologyIn the traditional single chip microcomputer, the power and the ground is in integrated circuit of the shell of ChenYin feet, general is in the upper left, right or at the lower left, two for symmetry point. It is, it makes the power supply noise through the whole chip, the SCM internal circuit cause interference. Now, a lot of the single chip microcomputer and power pin arranged in two adjacent pin. So, not only reduces the through the chip of the current, and also in the printed circuit board to decorate its decoupling capacitor, so as to reduce the noise of the system. In order to adapt to all kinds of application of now need, a lot of the single chip microcomputer output ability all had the very big enhancement, the single chip microcomputer Motorola company I/O mouth filling the pull current can reach 8 mA above, and Microchip company single-chip to 25 mA. Other companies: AMD, Fujitsu, NEC, Infineon, Hitachi, Ateml, such as Tosbiba basically can reach 8 ~ 20 mA level. The current larger drive circuit integration to chip in work internal causes all sorts of noise, in order to reduce the influence, now more than the small tube single chip parallel equivalent a large pipes method, and in every little the pipe string, the output terminal of the different equivalent resistance of resistance to reduce di/dt, this also is the so-called "jump to change along the softening technology", so as to eliminate large current transient produced by the noise.（2）the low frequency clockThe clock is one of high frequency noise sources, not only can the disturbance of SCM system, and also to the outside world circuitry interference and make theelectromagnetic compatibility can't meet the requirements. Asking for high reliability system, the low frequency clock which helps reduce system noise. In some of the single chip microcomputer by internal zohar cirtle technology, is in the external clock is low, also can produce high internal bus speed, and thus makes the speed and reduce the noise. The company MC68HC08 series Motorola and its 1 6/32 a single chip adopt the technology to improve reliability。