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单片机外文翻译外文文献英文文献 51系列单片机的结构和功能

单片机外文翻译外文文献英文文献 51系列单片机的结构和功能Structure and function of the MCS-51Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system areall the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM(128B/256B),it use not depositting not can reading /data that write,such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, andcan according to count or result of timing realize the control of thecomputer. ( 6) Five cut off cutting off the control system of thesource . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Helpremembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedurecounter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IAthat will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM canarrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address isarranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC ,visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0,P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingOutput grade , P3 of mouth , P1 of P1 , connect with inside haveload resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing ofan one-chip computer. Its main function is to turn PC into 0000Hinitially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency ofutilization brilliant to shake, restore to the throne signalduration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitablefor 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is veryimportant. Pieces of one-chip computer system could normalrunning,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with theoscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.Another name of MCS is embedded micro-controller, because it can be embedded into any micro-or small-scale equipment or equipment. At present, the single-chip embedded systems and Internet connectivity is a trend. However, Internet has been used as a fat server, thin machine technology users. This technology on the Internet to store and access large amounts of data is appropriate, but for control of embedded devices has become the "sledgehammer cracking a nut," the. Embedded devices to achieve and Int ernet connection, we need the Internet to the traditional theory and practice of embedded devices are reversed. In order to make complex or simple embedded devices, such as single-chip microcomputer-controlled machine tools, single-chip microcomputer-controlled door locks, can be practical and Internet connection, requires specialized equipment for the embedded microcontroller design a web server to embed devices can be connected to Internet, and through a standard Web browser to process control.At present, in order to single-chip microcomputer as the core of embedded systems and Internet connected companies, there are many morestudies in this area. More typical in this regard have emWare and TASKING company. Embedded systems companies EmWare network program - EMIT technology. This technology consists of three main parts: the emMicro, emGateway and web browser. Which, emMicroembedded devices is a 1K-byte memory capacity accounted for only a very small web servers; emGateway stronger as a function of the user or server, and it is used to achieve more than the management of embedded devices, as well as standard access the Internet communications, as well as the support of a web browser. Web browsers use to display and embedded emObjicts data transmission between devices. If sufficient resources embedded devices, while at the same time emMicro and emGateway into embedded devices, to achieve direct access to the Inter net. Otherwise, it will require a web browser emGateway and each other. EmWare's EMIT software technology using standard Internet protocol for 8-bit and 16-bit embedded devices to manage, but costs much less traditional. At present, single-chip applications, a new problem: This is how to make the 8-bit, 16-bit single-chip microcomputer to control the product, or embedded products or equipment to achieve the interconnection and the Internet? TASKING is now to solve this problem means. The company has emWare of EMIT software packages and related supporting integration, the formation of an integrated development environment, to provide users with convenient development. Embedded Internet Union ETI (embed the Internet Consortium) is to work closelywith the development of embedded Internet solutions. Results in the near future there will be published.中文译文51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

单片机英文参考文献翻译

天津科技大学毕业生外文资料翻译姓名:学院：电子信息与自动化学院专业：测控技术与仪器一．英文原文Progress in ComputersPrestige Lecture delivered to IEE, Cambridge, on 5 February 2009Maurice WilkesThe first stored program computers began to work around 1950. The one we built in Cambridge, the EDSAC was first used in the summer of 1949.These early experimental computers were built by people like myself with varying backgrounds. We all had extensive experience in electronic engineering and were confident that that experience would stand us in good stead. This proved true, although we had some new things to learn. The most important of these was that transients must be treated correctly; what would cause a harmless flash on the screen of a television set could lead to a serious error in a computer.As far as computing circuits were concerned, we found ourselves with an embarass de richess. For example, we could use vacuum tube diodes for gates as we did in the EDSAC or pentodes with control signals on both grids, a system widely used elsewhere. This sort of choice persisted and the term families of logic came into use. Those who have worked in the computer field will remember TTL, ECL and CMOS. Of these, CMOS has now become dominant.In those early years, the IEE was still dominated by power engineering and we had to fight a number of major battles in order to get radio engineering along with the rapidly developing subject of electronics.dubbed in the IEE light current electrical engineering.properly recognised as an activity in its own right. I remember that we had some difficulty in organising a conference because the power engineers’ ways of doing things were not our ways. A minor source of irritation was that all IEE published papers were expected to start with a lengthy statement of earlier practice, something difficult to do when there was no earlier practice Consolidation in the 1960sBy the late 50s or early 1960s, the heroic pioneering stage was over and the computer field was starting up in real earnest. The number of computers in the world had increased and they were much more reliable than the very early ones . To those years we can ascribe the first steps in high level languages and the firstoperating systems. Experimental time-sharing was beginning, and ultimately computer graphics was to come along.Above all, transistors began to replace vacuum tubes. This change presented a formidable challenge to the engineers of the day. They had to forget what they knew about circuits and start again. It can only be said that they measured up superbly well to the challenge and that the change could not have gone more smoothly.Soon it was found possible to put more than one transistor on the same bit of silicon, and this was the beginning of integrated circuits. As time went on, a sufficient level of integration was reached for one chip to accommodate enough transistors for a small number of gates or flip flops. This led to a range of chips known as the 7400 series. The gates and flip flops were independent of one another and each had its own pins. They could be connected by off-chip wiring to make a computer or anything else.These chips made a new kind of computer possible. It was called a minicomputer. It was something less that a mainframe, but still very powerful, and much more affordable. Instead of having one expensive mainframe for the whole organisation, a business or a university was able to have a minicomputer for each major department.Before long minicomputers began to spread and become more powerful. The world was hungry for computing power and it had been very frustrating for industry not to be able to supply it on the scale required and at a reasonable cost. Minicomputers transformed the situation.The fall in the cost of computing did not start with the minicomputer; it had always been that way. This was what I meant when I referred in my abstract to inflation in the computer industry ‘going the other way’. As time goes on people get more for their money, not less.Research in Computer Hardware.The time that I am describing was a wonderful one for research in computer hardware. The user of the 7400 series could work at the gate and flip-flop level and yet the overall level of integration was sufficient to give a degree of reliability far above that of discreet transistors. The researcher, in a university or elsewhere, could build any digital device that a fertile imagination could conjure up. In the Computer Laboratory we built the Cambridge CAP, a full-scale minicomputer with fancy capability logic.The 7400 series was still going strong in the mid 1970s and was used for the Cambridge Ring, a pioneering wide-band local area network. Publication of the design study for the Ring came just before the announcement of the Ethernet. Until these two systems appeared, users had mostly been content with teletype-based local area networks.Rings need high reliability because, as the pulses go repeatedly round the ring, they must be continually amplified and regenerated. It was the high reliability provided by the 7400 series of chips that gave us the courage needed to embark on the project for the Cambridge Ring.The RISC Movement and Its AftermathEarly computers had simple instruction sets. As time went on designers of commercially available machines added additional features which they thought would improve performance. Few comparative measurements were done and on the whole the choice of features depended upon the designer’s intuition.In 1980, the RISC movement that was to change all this broke on the world. The movement opened with a paper by Patterson and Ditzel entitled The Case for the Reduced Instructions Set Computer.Apart from leading to a striking acronym, this title conveys little of the insights into instruction set design which went with the RISC movement, in particular the way it facilitated pipelining, a system whereby several instructions may be in different stages of execution within the processor at the same time. Pipelining was not new, but it was new for small computers The RISC movement benefited greatly from methods which had recently become available for estimating the performance to be expected from a computer design without actually implementing it. I refer to the use of a powerful existing computer to simulate the new design. By the use of simulation, RISC advocates were able to predict with some confidence that a good RISC design would be able to out-perform the best conventional computers using the same circuit technology. This prediction was ultimately born out in practice.Simulation made rapid progress and soon came into universal use by computer designers. In consequence, computer design has become more of a science and less of an art. Today, designers expect to have a roomful of, computers available to do their simulations, not just one. They refer to such a roomful by the attractive name of computer farm.The x86 Instruction SetLittle is now heard of pre-RISC instruction sets with one major exception, namely that of the Intel 8086 and its progeny, collectively referred to as x86. This has become the dominant instruction set and the RISC instruction sets that originally had a considerable measure of success are having to put up a hard fight for survival.This dominance of x86 disappoints people like myself who come from the research wings.both academic and industrial.of the computer field. No doubt, business considerations have a lot to do with the survival of x86, but there are other reasons as well. However much we research oriented people would like to think otherwise. high level languages have not yet eliminated the use of machine code altogether. We need to keep reminding ourselves that there is much to be said for strict binary compatibility with previous usage when that can be attained. Nevertheless, things might have been different if Intel’s major attempt to produce a good RISC chip had been more successful. I am referring to the i860 (not the i960, which was something different). In many ways the i860 was an excellent chip, but its software interface did not fit it to be used in a workstation.There is an interesting sting in the tail of this apparently easy triumph of the x86 instruction set. It proved impossible to match the steadily increasing speed of RISC processors by direct implementation of the x86 instruction set as had been done in the past. Instead, designers took a leaf out of the RISC book; although it is not obvious, on the surface, a modern x86 processor chip contains hidden within it a RISC-style processor with its own internal RISC coding. The incoming x86 code is, after suitable massaging, converted into this internal code and handed over to the RISC processor where the critical execution is performed.In this summing up of the RISC movement, I rely heavily on the latest edition of Hennessy and Patterson’s books on computer design as my supporting authority; see in particular Computer Architecture, third edition, 2003, pp 146, 151-4, 157-8.The IA-64 instruction set.Some time ago, Intel and Hewlett-Packard introduced the IA-64 instruction set. This was primarily intended to meet a generally recognised need for a 64 bit address space. In this, it followed the lead of the designers of the MIPS R4000 and Alpha. However one would have thought that Intel would have stressed compatibility with the x86; the puzzle is that they did the exact opposite.Moreover, built into the design of IA-64 is a feature known as predicationwhich makes it incompatible in a major way with all other instruction sets. In particular, it needs 6 extra bits with each instruction. This upsets the traditional balance between instruction word length and information content, and it changes significantly the brief of the compiler writer.In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA-64 would be compatible with earlier x86 chips. It was hard to see exactly what was meant.Chips for the latest IA-64 processor, namely, the Itanium, appear to have special hardware for compatibility. Even so, x86 code runs very slowly.Because of the above complications, implementation of IA-64 requires a larger chip than is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am completely out of my depth as regards the economics of the semiconductor industry.AMD have defined a 64 bit instruction set that is more compatible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially compatible with those offered by AMD.]The Relentless Drive towards Smaller TransistorsThe scale of integration continued to increase. This was achieved by shrinking the original transistors so that more could be put on a chip. Moreover, the laws of physics were on the side of the manufacturers. The transistors also got faster, simply by getting smaller. It was therefore possible to have, at the same time, both high density and high speed.There was a further advantage. Chips are made on discs of silicon, known as wafers. Each wafer has on it a large number of individual chips, which are processed together and later separated. Since shrinkage makes it possible to get more chips on a wafer, the cost per chip goes down.Falling unit cost was important to the industry because, if the latest chips are cheaper to make as well as faster, there is no reason to go on offering the old ones, at least not indefinitely. There can thus be one product for the entiremarket.However, detailed cost calculations showed that, in order to maintain this advantage as shrinkage proceeded beyond a certain point, it would be necessary to move to larger wafers. The increase in the size of wafers was no small matter. Originally, wafers were one or two inches in diameter, and by 2000 they were as much as twelve inches. At first, it puzzled me that, when shrinkage presented so many other problems, the industry should make things harder for itself by going to larger wafers. I now see that reducing unit cost was just as important to the industry as increasing the number of transistors on a chip, and that this justified the additional investment in foundries and the increased risk.The degree of integration is measured by the feature size, which, for a given technology, is best defined as the half the distance between wires in the densest chips made in that technology. At the present time, production of 90 nm chips is still building upSuspension of LawIn March 1997, Gordon Moore was a guest speaker at the celebrations of the centenary of the discovery of the electron held at the Cavendish Laboratory. It was during the course of his lecture that I first heard the fact that you can have silicon chips that are both fast and low in cost described as a violation of Murphy’s law.or Sod’s law as it is usually called in the UK. Moore said that experience in other fields would lead you to expect to have to choose between speed and cost, or to compromise between them. In fact, in the case of silicon chips, it is possible to have both.In a reference book available on the web, Murphy is identified as an engineer working on human acceleration tests for the US Air Force in 1949. However, we were perfectly familiar with the law in my student days, when we called it by a much more prosaic name than either of those mentioned above, namely, the Law of General Cussedness. We even had a mock examination question in which the law featured. It was the type of question in which the first part asks for a definition of some law or principle and the second part contains a problem to be solved with the aid of it. In our case the first part was to define the Law of General Cussedness and the second was the problem;A cyclist sets out on a circular cycling tour. Derive an equation giving the direction of the wind at any time.The single-chip computerAt each shrinkage the number of chips was reduced and there were fewer wiresgoing from one chip to another. This led to an additional increment in overall speed, since the transmission of signals from one chip to another takes a long time.Eventually, shrinkage proceeded to the point at which the whole processor except for the caches could be put on one chip. This enabled a workstation to be built that out-performed the fastest minicomputer of the day, and the result was to kill the minicomputer stone dead. As we all know, this had severe consequences for the computer industry and for the people working in it.From the above time the high density CMOS silicon chip was Cock of the Roost. Shrinkage went on until millions of transistors could be put on a single chip and the speed went up in proportion.Processor designers began to experiment with new architectural features designed to give extra speed. One very successful experiment concerned methods for predicting the way program branches would go. It was a surprise to me how successful this was. It led to a significant speeding up of program execution and other forms of prediction followedEqually surprising is what it has been found possible to put on a single chip computer by way of advanced features. For example, features that had been developed for the IBM Model 91.the giant computer at the top of the System 360 range.are now to be found on microcomputersMurphy’s Law remained in a state of suspension. No longer did it make sense to build experimental computers out of chips with a small scale of integration, such as that provided by the 7400 series. People who wanted to do hardware research at the circuit level had no option but to design chips and seek for ways to get them made. For a time, this was possible, if not easyUnfortunately, there has since been a dramatic increase in the cost of making chips, mainly because of the increased cost of making masks for lithography, a photographic process used in the manufacture of chips. It has, in consequence, again become very difficult to finance the making of research chips, and this is a currently cause for some concern.The Semiconductor Road MapThe extensive research and development work underlying the above advances has been made possible by a remarkable cooperative effort on the part of the international semiconductor industry.At one time US monopoly laws would probably have made it illegal for UScompanies to participate in such an effort. However about 1980 significant and far reaching changes took place in the laws. The concept of pre-competitive research was introduced. Companies can now collaborate at the pre-competitive stage and later go on to develop products of their own in the regular competitive manner.The agent by which the pre-competitive research in the semi-conductor industry is managed is known as the Semiconductor Industry Association (SIA). This has been active as a US organisation since 1992 and it became international in 1998. Membership is open to any organisation that can contribute to the research effort.Every two years SIA produces a new version of a document known as the International Technological Roadmap for Semiconductors (ITRS), with an update in the intermediate years. The first volume bearing the title ‘Roadmap’ was issued in 1994 but two reports, written in 1992 and distributed in 1993, are regarded as the true beginning of the series.Successive roadmaps aim at providing the best available industrial consensus on the way that the industry should move forward. They set out in great detail.over a 15 year horizon. the targets that must be achieved if the number of components on a chip is to be doubled every eighteen months.that is, if Moore’s law is to be maintained.-and if the cost per chip is to fall.In the case of some items, the way ahead is clear. In others, manufacturing problems are foreseen and solutions to them are known, although not yet fully worked out; these areas are coloured yellow in the tables. Areas for which problems are foreseen, but for which no manufacturable solutions are known, are coloured red. Red areas are referred to as Red Brick Walls.The targets set out in the Roadmaps have proved realistic as well as challenging, and the progress of the industry as a whole has followed the Roadmaps closely. This is a remarkable achievement and it may be said that the merits of cooperation and competition have been combined in an admirable manner.It is to be noted that the major strategic decisions affecting the progress of the industry have been taken at the pre-competitive level in relative openness, rather than behind closed doors. These include the progression to larger wafers.By 1995, I had begun to wonder exactly what would happen when the inevitable point was reached at which it became impossible to make transistors any smaller. My enquiries led me to visit ARPA headquarters in Washington DC, where I was given a copy of the recently produced Roadmap for 1994. This made it plain that seriousproblems would arise when a feature size of 100 nm was reached, an event projected to happen in 2007, with 70 nm following in 2010. The year for which the coming of 100 nm (or rather 90 nm) was projected was in later Roadmaps moved forward to 2004 and in the event the industry got there a little sooner.I presented the above information from the 1994 Roadmap, along with such other information that I could obtain, in a lecture to the IEE in London, entitled The CMOS end-point and related topics in Computing and delivered on 8 February 1996.The idea that I then had was that the end would be a direct consequence of the number of electrons available to represent a one being reduced from thousands to a few hundred. At this point statistical fluctuations would become troublesome, and thereafter the circuits would either fail to work, or if they did work would not be any faster. In fact the physical limitations that are now beginning to make themselves felt do not arise through shortage of electrons, but because the insulating layers on the chip have become so thin that leakage due to quantum mechanical tunnelling has become troublesome.There are many problems facing the chip manufacturer other than those that arise from fundamental physics, especially problems with lithography. In an update to the 2001 Roadmap published in 2002, it was stated that the continuation of progress at present rate will be at risk as we approach 2005 when the roadmap projects that progress will stall without research break-throughs in most technical areas “. This was the most specific statement about the Red Brick Wall, that had so far come from the SIA and it was a strong one. The 2003 Roadmap reinforces this statement by showing many areas marked red, indicating the existence of problems for which no manufacturable solutions are known.It is satisfactory to report that, so far, timely solutions have been found to all the problems encountered. The Roadmap is a remarkable document and, for all its frankness about the problems looming above, it radiates immense confidence. Prevailing opinion reflects that confidence and there is a general expectation that, by one means or another, shrinkage will continue, perhaps down to 45 nm or even less.However, costs will rise steeply and at an increasing rate. It is cost that will ultimately be seen as the reason for calling a halt. The exact point at which an industrial consensus is reached that the escalating costs can no longer be met will depend on the general economic climate as well as on the financial strength of the semiconductor industry itself.。

单片机英文文献资料及翻译

单片机英文文献资料及翻译单片机(英文：Microcontroller)Microcontroller is a small computer on a single integrated circuit that contains a processor core, memory, and programmable input/output peripherals. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.A microcontroller's processor core is typically a small, low-power computer dedicated to controlling the operation of the device in which it is embedded. It is often designed to provide efficient and reliable control of simple and repetitive tasks, such as switching on and off lights, or monitoring temperature or pressure sensors.MEMORYMicrocontrollers typically have a limited amount of memory, divided into program memory and data memory. The program memory is where the software that controls the device is stored, and is often a type of Read-Only Memory (ROM). The data memory, on the other hand, is used to store data that is used by the program, and is often volatile, meaning that it loses its contents when power is removed.INPUT/OUTPUTMicrocontrollers typically have a number of programmable input/output (I/O) pins that can be used to interface with external sensors, switches, actuators, and other devices. These pins can be programmed to perform specific functions,such as reading a sensor value, controlling a motor, or generating a signal. Many microcontrollers also support communication protocols like serial, parallel, and USB, allowing them to interface with other devices, including other microcontrollers, computers, and smartphones.APPLICATIONSMicrocontrollers are widely used in a variety of applications, including:- Home automation systems- Automotive electronics- Medical devices- Industrial control systems- Consumer electronics- RoboticsCONCLUSIONIn conclusion, microcontrollers are powerful and versatile devices that have become an essential component in many embedded systems. With their small size, low power consumption, and high level of integration, microcontrollers offer an effective and cost-efficient solution for controlling a wide range of devices and applications.。

单片机英文文献及翻译)

Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。

单片机英文参考文献

单片机英文参考文献篇一：5-单片机+外文文献+英文文献+外文翻译中英对照AT89C51的介绍（原文出处：http：///resource/）描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。

和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。

片内含有8位中央处理器和闪烁存储单元，有较强的功能的AT89C51单片机能够被应用到控制领域中。

功能特性AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定时/计数器，1个5向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。

另外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。

闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。

掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。

引脚描述VCC：电源电压 GND：地 P0口：P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。

作为输出口时，每一个管脚都能够驱动8个TTL电路。

当“1”被写入P0口时，每个管脚都能够作为高阻抗输入端。

P0口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。

P0口在闪烁编程时，P0口接收指令，在程序校验时，输出指令，需要接电阻。

沈阳航空工业学院电子工程系毕业设计（外文翻译）P1口：P1口一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。

对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。

因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。

闪烁编程时和程序校验时，P1口接收低8位地址。

单片机英文文献及翻译

附录A英文文献翻译原文Temperature Control Using a Microcontroller:An Interdisciplinary Undergraduate Engineering Design ProjectJames S. McDonaldDepartment of Engineering ScienceTrinity UniversitySan Antonio, TX 78212AbstractThis paper describes an interdisc iplinary design project which was done under the author’s supervision by a group of four senior students in the Department of Engineering Science at Trinity University. The objective of the project was to develop a temperature control system for an air-filled chamber. The system was to allow entry of a desired chamber temperature in a prescribed range and to exhibit overshoot and steady-state temperature error of less than 1 degree Kelvin in the actual chamber temperature step response. The details of the design developed by this group of students, based on a Motorola MC68HC05 family microcontroller, are described. The pedagogical value of the problem is also discussed through a description of some of the key steps in the design process. It is shown that the solution requires broad knowledge drawn from several engineering disciplines including electrical, mechanical, and control systems engineering.1 IntroductionThe design project which is the subject of this paper originated from a real-world application.A prototype of a microscope slide dryer had been developed around an OmegaTM modelCN-390 temperature controller, and the objective was to develop a custom temperature control system to replace the Omega system. The motivation was that a custom controller targeted specifically for the application should be able to achieve the same functionality at a much lower cost, as the Omega system is unnecessarily versatile and equipped to handle a wide variety of applications.The mechanical layout of the slide dryer prototype is shown in Figure 1. The main element of the dryer is a large, insulated, air-filled chamber in which microscope slides, each with a tissue sample encased in paraffin, can be set on caddies. In order that the paraffin maintain the proper consistency, the temperature in the slide chamber must be maintained at a desired (constant) temperature. A second chamber (the electronics enclosure) houses a resistive heater and the temperature controller, and a fan mounted on the end of the dryer blows air across theheater, carrying heat into the slide chamber. This design project was carried out during academic year 1996–97 by four students under the author’s supervision as a Senior Design project in the Department of Engineering Science at Trinity University. The purpose of this paper isto describe the problem and the students’ solution in some detail, and to discuss some of the pedagogical opportunities offered by an interdisciplinary design project of this type. The students’ own report was presented a t the 1997 National Conference on Undergraduate Research [1]. Section 2 gives a more detailed statement of the problem, including performance specifications, and Section 3 describes the students’ design. Section 4 makes up the bulk of the paper, and discusses in some detail several aspects of the design process which offer unique pedagogical opportunities. Finally, Section 5 offers some conclusions.2 Problem StatementThe basic idea of the project is to replace the relevant parts of the functionality of an Omega CN-390 temperature controller using a custom-designed system. The application dictates that temperature settings are usually kept constant for long periods of time, but it’s nonetheless important that step changes be tracked in a “reasonable” manner. Thus the main requirements boil down to·allowing a chamber temperature set-point to be entered,·displaying both set-point and actual temperatures, and·tracking step changes in set-point temperature with acceptable rise time, steady-state error, and overshoot.Although not explicitly a part of the specifications in Table 1, it was clear that the customer desired digital displays of set-point and actual temperatures, and that set-point temperature entry should be digital as well (as opposed to, say, through a potentiometer setting).3 System DesignThe requirements for digital temperature displays and setpoint entry alone are enough to dictate that a microcontrollerbased design is likely the most appropriate. Figure 2 shows a block diagram of the stude nts’ design.The microcontroller, a MotorolaMC68HC705B16 (6805 for short), is the heart of the system. It accepts inputs from a simple four-key keypad which allow specification of the set-point temperature, and it displays both set-point and measured chamber temperatures using two-digit seven-segment LED displays controlled by a display driver. All these inputs and outputs are accommodated by parallel ports on the 6805. Chamber temperature is sensed using apre-calibrated thermistor and input via one of the 6805’s analog-to-digital inputs. Finally, a pulse-width modulation (PWM) output on the 6805 is used to drive a relay which switches line power to the resistive heater off and on.Figure 3 shows a more detailed schematic of the electronics and their interfacing to the 6805. The keypad, a Storm 3K041103, has four keys which are interfaced to pins PA0{ PA3 of Port A, configured as inputs. One key functions as a mode switch. Two modes are supported: set mode and run mode. In set mode two of the other keys are used to specify the set-point temperature: one increments it and one decrements. The fourth key is unused at present. The LED displays are driven by a Harris Semiconductor ICM7212 display driver interfaced to pins PB0{PB6 of Port B, configured as outputs. The temperature-sensing thermistor drives, through a voltage divider, pin AN0 (one of eight analog inputs). Finally, pin PLMA (one of two PWM outputs) drives the heater relay.Software on the 6805 implements the temperature control algorithm, maintains the temperature displays, and alters the set-point in response to keypad inputs. Because it is not complete at this writing, software will not be discussed in detail in this paper. The control algorithm in particular has not been determined, but it is likely to be a simple proportional controller and certainly not more complex than a PID. Some control design issues will be discussed in Section 4, however.4 The Design ProcessAlthough essentially the project is just to build a thermostat, it presents many nice pedagogical opportunities. The knowledge and experience base of a senior engineering undergraduate are just enough to bring him or her to the brink of a solution to various aspects of the problem. Yet, in each case, realworld considerations complicate the situation significantly.Fortunately these complications are not insurmountable, and the result is a very beneficial design experience. The remainder of this section looks at a few aspects of the problem which present the type of learning opportunity just described. Section 4.1 discusses some of the features of a simplified mathematical model of the thermal properties of the system and how it can beeasily validated experimentally. Section 4.2 describes how realistic control algorithm designs can be arrived at using introductory concepts in control design. Section 4.3 points out some important deficiencies of such a simplified modeling/control design process and how they can be overcome through simulation. Finally, Section 4.4 gives an overview of some of the microcontroller-related design issues which arise and learning opportunities offered.4.1 MathematicalModelLumped-element thermal systems are described in almost any introductory linear control systems text, and just this sort of model is applicable to the slide dryer problem. Figure 4 shows a second-order lumped-element thermal model of the slide dryer. The state variables are the temperatures Ta of the air in the box and Tb of the box itself. The inputs to the system are the power output q(t) of the heater and the ambient temperature T¥. ma and mb are the masses of the air and the box, respectively, and Ca and Cb their specific heats. μ1 and μ2 are heat transfer coefficients from the air to the box and from the box to the external world, respectively.It’s not hard to show that the (linearized) state equationscorresponding to Figure 4 areTaking Laplace transforms of (1) and (2) and solving for Ta(s), which is the output of interest, gives the following open-loop model of the thermal system:where K is a constant and D(s) is a second-order polynomial.K, tz, and the coefficients ofD(s) are functions of the variousparameters appearing in (1) and (2).Of course the various parameters in (1) and (2) are completely unknown, but it’s not hard to show that, regardless of their values, D(s) has two real zeros. Therefore the main transfer function of interest (which isthe one from Q(s), since we’ll assume constant ambient temperature) can be writtenMoreover, it’s not too hard to show that 1=tp1 <1=tz <1=tp2, i.e., that the zero lies between the two poles. Both of these are excellent exercises for the student, and the result is the openloop pole-zero diagram of Figure 5.Obtaining a complete thermal model, then, is reduced to identifying the constant K and the three unknown time constants in (3). Four unknown parameters is quite a few, but simple experiments show that 1=tp1 _ 1=tz;1=tp2 so that tz;tp2 _ 0 are good approximations. Thus the open-loop system is essentially first-order and can therefore be written(where the subscript p1 has been dropped).Simple open-loop step response experiments show that,for a wide range of initial temperatures and heat inputs, K _0:14 _=W and t _ 295 s.14.2 Control System DesignUsing the first-order model of (4) for the open-loop transfer function Gaq(s) and assuming for the moment that linear control of the heater power output q(t) is possible, the block diagram of Figure 6 represents the closed-loop system. Td(s) is the desired, or set-point, temperature,C(s) is the compensator transfer function, and Q(s) is the heater output in watts.Given this simple situation, introductory linear control design tools such as the root locus method can be used to arrive at a C(s) which meets the step response requirements on rise time, steady-state error, and overshoot specified in Table 1. The upshot, of course, is that a proportional controller with sufficient gain can meet all specifications. Overshoot is impossible, and increasing gains decreases both steady-state error and rise time.Unfortunately, sufficient gain to meet the specifications may require larger heat outputs than the heater is capable of producing. This was indeed the case for this system, and the result is that the rise time specification cannot be met. It is quite revealing to the student how useful such an oversimplified model, carefully arrived at, can be in determining overall performance limitations.4.3 Simulation ModelGross performance and its limitations can be determined using the simplified model of Figure 6, but there are a number of other aspects of the closed-loop system whose effects on performance are not so simply modeled. Chief among these are·quantization error in analog-to-digital conversion of the measured temperature and· the use of PWM to control the heater.Both of these are nonlinear and time-varying effects, and the only practical way to study them is through simulation (or experiment, of course).Figure 7 shows a SimulinkTM block diagram of the closed-loop system which incorporates these effects. A/D converter quantization and saturation are modeled using standard Simulink quantizer and saturation blocks. Modeling PWM is more complicated and requires a customS-function to represent it.This simulation model has proven particularly useful in gauging the effects of varying thebasic PWM parameters and hence selecting them appropriately. (I.e., the longer the period, the larger the temperature error PWM introduces. On the other hand, a long period is desirable to avoid excessiv e relay “chatter,” among other things.) PWM is often difficult for students to grasp, and the simulation model allows an exploration of its operation and effects which is quite revealing.4.4 The MicrocontrollerSimple closed-loop control, keypad reading, and display control are some of the classic applications of microcontrollers, and this project incorporates all three. It is therefore an excellent all-around exercise in microcontroller applications. In addition, because the project isto produce an actua l packaged prototype, it won’t do to use a simple evaluation board with theI/O pins jumpered to the target system. Instead, it’s necessary to develop a complete embedded application. This entails the choice of an appropriate part from the broad range offered in a typical microcontroller family and learning to use a fairly sophisticated development environment. Finally, a custom printed-circuit board for the microcontroller and peripherals must be designed and fabricated.Microcontroller Selection. In view of existing local expertise, the Motorola line of microcontrollers was chosen for this project. Still, this does not narrow the choice down much. A fairly disciplined study of system requirements is necessary to specify which microcontroller, out of scores of variants, is required for the job. This is difficult for students, as they generally lack the experience and intuition needed as well as the perseverance to wade through manufacturers’ selection guides.Part of the problem is in choosing methods for interfacing the various peripherals (e.g., what kind of display driver should be used?). A study of relevant Motorola application notes [2, 3, 4] proved very helpful in understandingwhat basic approaches are available, and what microcontroller/peripheral combinations should be considered.The MC68HC705B16 was finally chosen on the basis of its availableA/D inputs and PWMoutputs as well as 24 digital I/O lines. In retrospect this is probably overkill, as only oneA/D channel, one PWM channel, and 11 I/O pins are actually required (see Figure 3). The decision was made to err on the safe side because a complete development system specific to the chosen part was necessary, and the project budget did not permit a second such system to be purchased should the firstprove inadequate.Microcontroller Application Development. Breadboarding of the peripheral hardware, development of microcontroller software, and final debugging and testing of a customprinted-circuit board for the microcontroller and peripherals all require a development environment of some kind. The choice of a development environment, like that of themicrocontroller itself, can be bewildering and requires some faculty expertise. Motorola makes three grades of development environment ranging from simple evaluation boards (at around $100) to full-blown real-time in-circuit emulators (at more like $7500). The middle option was chosen for this project: the MMEVS, which consists of _ a platform board (which supports all 6805-family parts), _ an emulator module (specific to B-series parts), and _ a cable and target head adapter (package-specific). Overall, the system costs about $900 and provides, with some limitations, in-circuit emulation capability. It also comes with the simple but sufficient software development environment RAPID [5].Students find learning to use this type of system challenging, but the experience they gain in real-world microcontroller application development greatly exceeds the typical first-course experience using simple evaluation boards.Printed-Circuit Board. The layout of a simple (though definitely not trivial) printed-circuit board is another practical learning opportunity presented by this project. The final board layout, with package outlines, is shown (at 50% of actual size) in Figure 8. The relative simplicity of the circuit makes manual placement and routing practical—in fact, it likely gives better results than automatic in an application like this—and the student is therefore exposed to fundamental issues of printed-circuit layout and basic design rules. The layout software used was the very nice package pcb,2 and the board was fabricated in-house with the aid of our staff electronics technician.5 ConclusionThe aim of this paper has been to describe an interdisciplinary, undergraduate engineering design project: a microcontroller- based temperature control system with digital set-point entry and set-point/actual temperature display. A particular design of such a system has been described, and a number of design issues which arise—from a variety of engineering disciplines—have been discussed. Resolution of these issues generally requires knowledge beyond that acquired in introductory courses, but realistically accessible to advance undergraduate students, especiallywith the advice and supervision of faculty.Desirable features of the problem, from a pedagogical viewpoint, include the use of a microcontroller with simple peripherals, the opportunity to usefully apply introductorylevel modeling of physical systems and design of closed-loop controls, and the need for relatively simple experimentation (for model validation) and simulation (for detailed performance prediction). Also desirable are some of the technologyrelated aspects of the problem including practical use of resistive heaters and temperature sensors (requiring knowledge of PWM and calibration techniques, respectively), microcontroller selection and use of development systems, and printedcircuit design.AcknowledgementsThe author would like to acknowledge the hard work, dedication, and ability shown by the students involved in this project: Mark Langsdorf, Matt Rall, PamRinehart, and David Schuchmann. It is their project, and credit for its success belongs to them.References[1] M. Langsdorf, M. Rall, D. Schuchmann, and P. Rinehart,“Temperature control of a microscope slide dryer,” in1997 National Conference on Undergraduate Research,(Austin, TX), April 1997. Poster presentation.[2] Motorola, Inc., Phoenix, AZ, Temperature Measurementand Display Using the MC68HC05B4 and the MC14489,1990. Motorola SemiconductorApplicationNote AN431.[3] Motorola, Inc., Phoenix, AZ, HC05 MCU LED DriveTechniques Using the MC68HC705J1A, 1995. MotorolaSemiconductor Application Note AN1238.[4] Motorola, Inc., Phoenix, AZ, HC05MCU Keypad DecodingTechniques Using the MC68HC705J1A, 1995. MotorolaSemiconductor Application Note AN1239.[5] Motorola, Inc., Phoenix, AZ, RAPID Integrated DevelopmentEnvironment User’s Manual, 1993. (RAPID wasdeveloped by P & E Microcomputer Systems, Inc.).附录B英文文献翻译中文单片机温度控制：一个跨学科的本科生工程设计项目JamesS.McDonald工程科学系三一大学德克萨斯州圣安东尼奥市78212摘要本文所描述的是作者领导由四个三一大学高年级学生组成的团队进行的一个跨学科工程项目的设计。

单片机-毕业论文外文文献翻译

单片机单片机也被称为微控制器（Microcontroller Unit），常用英文字母的缩写MCU 表示单片机，它最早是被用在工业控制领域。

单片机由芯片内仅有CPU的专用处理器发展而来。

最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。

INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。

早期的单片机都是8位或4位的。

其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。

此后在8031上发展出了MCS51系列单片机系统。

基于这一系统的单片机系统直到现在还在广泛使用。

随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。

90年代后随着消费电子产品大发展，单片机技术得到了巨大提高。

随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。

而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。

目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。

当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。

而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。

单片机比专用处理器更适合应用于嵌入式系统，因此它得到了最多的应用。

事实上单片机是世界上数量最多的计算机。

现代人类生活中所用的几乎每件电子和机械产品中都会集成有单片机。

手机、电话、计算器、家用电器、电子玩具、掌上电脑以及鼠标等电脑配件中都配有1-2部单片机。

而个人电脑中也会有为数不少的单片机在工作。

汽车上一般配备40多部单片机，复杂的工业控制系统上甚至可能有数百台单片机在同时工作！单片机的数量不仅远超过PC机和其他计算的总和，甚至比人类的数量还要多。

单片机外文文献翻译(2024)

引言：单片机（Microcontroller）是一种广泛应用于嵌入式系统中的小型计算机芯片。

它集成了处理器核心、存储器、外设接口和时钟电路等核心部件，可以独立运行。

随着全球化的发展，外文文献对于学习和研究单片机领域来说至关重要。

本文翻译的外文文献《MicrocontrollerbasedTrafficLightControlSystem》详细介绍了基于单片机的交通信号灯控制系统。

概述：交通信号灯控制是现代都市交通系统中至关重要的一环。

传统的交通信号灯控制系统通常由定时器控制，不能根据实际交通情况动态调整信号灯的时间。

而基于单片机的交通信号灯控制系统可以实现根据实时交通流量来动态调整信号灯的时间，优化交通效率。

本文将详细介绍该系统的设计和实现。

正文：一、单片机选型1.1.CPU性能：本文选择了一款高性能的32位单片机作为控制核心，它具有较高的处理能力和较大的存储器容量，可以同时处理多条交通路口的信号控制。

1.2.外设接口：该单片机具有丰富的外设接口，可以与交通信号灯、传感器和通信设备等进行连接，实现信号控制和数据交互。

1.3.低功耗设计：为了节约能源和延长系统寿命，在单片机选型时考虑了低功耗设计，降低系统运行的能耗。

二、硬件设计2.1.交通信号灯：在设计交通信号灯时，考虑了日夜可见性和能耗。

采用了高亮度LED作为信号灯光源，同时添加了光敏传感器控制信号灯的亮度，以满足不同时间段的亮度需求。

2.2.传感器：通过安装车辆感应器和行人感应器等传感器，可以在实时监测交通流量的基础上，智能调整信号灯时间，提高路口的交通效率。

2.3.通信设备：在交通信号灯控制系统中引入了通信设备，可以实现各交通路口之间的信息交互和协调控制，提高整体交通系统的效率。

三、软件设计3.1.程序架构：采用了多任务的实时操作系统，将交通信号灯控制、传感器数据处理和通信设备控制等功能分别封装成不同的任务，实现了系统的高效运行和任务调度。

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外文原文A: Fundamentals of Single-chip MicrocomputerT h e s i n gl e-c hi p m i c r o c om p ut e r i s t h e c u l m i n at i on o f bot h t h e d e v el opm e nt o f t h e di gi t a l co m p ut e r a nd t h e i n t egr a t e d ci r c ui t a rgua b l y t h e t o w m o s t s i gni fi c an t i nv e nt i o ns o f t he 20t h c e nt u r yT h es e t ow t yp e s o f a r c hi t e ct u re a r e fou n d i n s i n gl e-ch i p m i c r o com pu t e r. S om e em pl o y t h e s pl i t p r o gr am/d at a m e m o r y o f t h e Ha r v a rd a r c hi t e ct u re, s ho w n i n Fi g.3-5A-1, ot h e rs fo l l o w t h e p hi l os op h y,w i de l y a d a p t ed for ge n e r a l-p ur po s e co m p ut e rs an d m i cr o p ro c es s o rs, o f m a ki n g no l o gi c al d i st i n ct i o n b et w e en p ro gr a m a nd d a t a m e m o r y a s i n t h e P ri n c et on a r c hi t ec t u r e, s ho w n i n Fi g.3-5A-2.In ge n e r a l t e rm s a s i n gl e-c hi p m i c r oc o m p ut e r i s c h ar ac t e ri z ed b y t h e i n co rp o r at i on o f al l t h e u ni t s o f a c om p ut e r i nt o a si n gl e d e vi c e, a s s ho w n i nFig.3-5A-1 A Harvard typeRead only memory (ROM)R OM i s u su al l y f o r t h e p er m an e nt,no n-v ol at i l e st o r a ge o f an a pp l i c at i on s p r o gr am.M a n y m i c ro c om put e r s an d m i cr o co nt ro l l e rs a r e i nt en d ed f or h i gh-v ol u m e a pp l i c a t i on s a nd h en c e t he e c on om i c al m a nu f a ct ur e of t he d e vi c es re qu i re s t h a t t h e c ont e nt s of t h e p ro gr a m m em o r y b e c om m i t t ed p e rm a n en t l y d u r i ng t he m an u f ac t u r e o f ch i ps. C l e a rl y,t hi s i m pl i e s a r i go ro us a p pr o a ch t o R OM c od e d ev e l o pm e nt s i n c e c h ange s c an no t b e m ad e a f t e r m an u f ac t u r e .T hi s d e v el o pm e nt pr o c e s s m a y i n vo l v e em ul at i on us i n g a s op hi st i c at e d d ev el o pm e nt s ys t e m wi t h a h a rd w a re em ul a t i on c ap a bi l i t y a s w e l l as t h e u se of po w e r fu l s o ft w ar e t oo l s.S om e m a nu f a ct ur e rs p ro vi d e ad di t i o na l R O M opt i o ns by i n c l u di n g in t h ei r r a n ge d e vi c es wi t h (o r i nt e nd ed f o r u s e wi t h)us e r p r o gr am m a bl e m em o r y.T he s i m pl e st of t h e s e i s us u a l l y d e v i c e w hi c h c an o p er at e i n a m i c r op r oc e ss o r m od e b y u s i n g s om e of t h e i n put/o ut p ut l i n es a s a n ad d r ess a n d d at a bu s f or a cc e s si n g ex t e r n al m e m or y.T h i s t yp e o f d e vi c e c a n b e h av e f u n ct i on al l y a s t h e s i n gl e chi p m i c ro c om pu t e r f rom w hi ch i t i s d e ri v ed al b eit w i t h r est ri c t e d I/O an d a m od i f i ed ex t e rn a l ci r cui t. Th e u s e o f t h es e R O M l e ss de vi c es i s c om m o n ev en i n p ro du c t i o n ci r cu i t s w h er e t he vo l u m e d oes n ot j us t i f y t h e d eve l opm e nt co s t s o f cu st om o n-c hi p R OM[2];t h er e c an s t i l l b e a si gn i fi c ant s av i n g i n I/O a nd ot h e r c hi ps c om p a r ed t o a co nv e nt i on al m i c r op r oc e ss o r b ase d ci r cu i t. M o r e ex a c t re pl a c em e nt f o r R OM d e vi c es c an b e ob t ai n e d i n t he fo rm o f v a ri a nt s wi t h 'p i gg y-b a c k' EP R O M(E r as a bl e p r o gr am m a bl e R OM)so ck e t s or d evi c e s wi t h E P R OM i n s t e ad o f R OM。

T h es e d e vi c es a r e na t ur a l l y m o r e ex p en si v e t h an e qui v al en t R O M d ev i ce, b ut d o p r ovi d e c om pl et e ci r cu i t e qu i v al en t s. EP R OM b as ed d e vi c es ar e al s o ex t r e m el y a t t r a ct i ve fo r l o w-v ol um e a p pl i c a t i o ns w h er e t h e y p r o vi d e t h e a d v an t a ge s o f a si n gl e-ch i p d evi c e, i n t e rm s o f o n-c hi p I/O,e t c. ,w i t h t h e c o nv e ni en c e o f f l ex i b l e u s e r pr o gr am m a bi l i t y.Random access memory (RAM).R AM i s f o r t h e s t or a ge o f wo rk i n g v ar i ab l es an d d at a u se d du ri n g p r o gr am ex e c ut i on. Th e s i ze o f t hi s m em o r y v a ri e s wi t h d e vi c e t yp e b u t i t h as t he s a m e c h a ra c t er i st i c wi d t h (4,8,16 b i t s e t c.) as t h e pr o c es s o r,S p e ci al f u n ct i on r e gi st e rs, s u ch as s t a ck poi nt e r o r t i m e r r e gi st e r a r e o ft en l o gi ca l l y i n co rp o r at ed i nt o t h e R AM ar e a. It i s a l s o co m m on i n H a rd t yp e m i c r o com pu t er s t o t r e at t h e R A M a re a a s a c ol l e c t i o n o f r e gi s t e r;i t i s u n ne c e ss a r y t o m ak e di s t i n ct i on be t we e n R A M a nd p ro ce s s o r r e gi s t e r as i s d o ne i n t h e c as e o f a m i c ro p ro c es s o r sys t e m si n c e R AM an d re gi s t e rs a re not u su a l l y p h ys i c a l l y s e p a ra t ed i n a m i c ro c om put e r .Central processing unit (CPU).T h e C P U i s m u ch l i k e t h at o f a n y m i c r op r oc e ss o r. Ma n y a p pl i c a t i o ns o f m i cr o co m p ut e rs an d m i cr o co nt ro l l e rs i nv ol ve t h e h an dl i n g o f bi n ar y-c o d e d de c i m al(B C D)d a t a (fo r n um e ri c al d i s pl a ys,f o r ex am p l e),h e n c e i t i s co m m on t o fi n d t hat t h e C P U i s w el l a d a pt ed t o h a ndl i ng t h i s t yp e o f d at a.It i s al s o co m m on t o f i n d goo df a c i l i t i es f or t est i ng,s e t t i ng a nd r es et t i n g i n di vi d u al bi t s o f m e m o r y o r I/O s i n c e m a n y c o n t ro l l e r a ppl i c at i on s i nv ol v e th e t u rni n g on an d o ff o f s i n gl e o ut pu t l i ne s o r t he r e a di n g t h e si n gl e l i n e. Th es e l i n e s a r e r e a di l y i n t e rf a c e d t o t w o-s t at e d e vi c es s u ch a s sw i t ch e s, t h er m o s t at s, s o l i d-s t at e r el a ys, v al v es, m ot or, e t c.Parallel input/output.P a r al l el i np ut a nd ou t p ut s ch e m e s v ar y s om e wh a t i n di ff ere n t m i cr o co m p ut e r;i n m ost a m e ch a n i sm i s p r ov i d ed t o at l e as t al l o w so m e fl ex i bi l i t y o f c h oo s i n g w hi c h pi ns a r e out pu t s a nd wh i ch ar e i np ut s. T hi s m a y a p p l y t o al l o r s om e of t he p o rt s. S om e I/O l i n es a re s ui t abl e f o r di r ec t i nt e r f a ci n g t o, for ex a m pl e,f l u o re s c en t d i sp l a ys,o r c an p ro vi de s u ffi c i en t cu r r ent t o m a k e i nt e r fa c i n g ot h e r co m p on e nt s st r ai ght f o r w a rd. S om e d evi c es a l l o w a n I/O p o rt t o b e co n fi gur e d as a s ys t e m bu s t o a l l ow o ff-c hi p m em or y a n d I/O ex p an si on.T hi s f ac i l i t y i s po t e nt i a l l y u s e f u l as a pr odu c t r a n ge d ev el op s, s i n c e su c c es s i ve enh a n c em en t s m a y b e c o m e t oo bi g f or on-c hi p m em o r y a n d i t i s un d es i r a bl e not t o bui l d o n t h e ex i s t i n g s o ft wa r e b as e.Serial input/output .S e ri al co m m u ni c at i o n w i t h t e rm i n al d ev i c es i s co m m o n m e a n s o f p ro vi d i n g a l i n k us i n g a s m a l l n um b er o f l i n e s.Th i s s o rt o f com m u ni c at i o n c a n a l s o b e ex pl oi t e d f or i nt e r f a c i n g s p e ci al f u n ct i on ch i p s or l i nki n g s e v e ra l m i c r o com pu t er s t oge t h e r .Bo t h t h e c o m m o n a s yn c h r on o us s yn c h r o no us c o m m u ni c at i o n s c he m es r eq ui r e p r ot oc o l s t h at p r ovi d e fr a m i n g (s t a rt a nd s t o p) i n fo rm a t i o n .T hi s c a n b e i m pl em e nt ed as a h a rd wa r e f a ci l i t y o r U(S) A RT(U ni v e rs a l(s yn c h r on ou s)as yn c h r o n ous r e ce i v e r/t r an s m i t t e r) r el i e vi n g t h e p ro c es s o r(a nd t h e a pp l i c at i ons pr o gr am m er)of t h i s l o w-l e ve l, t i m e-c on su m i n g,de t ai l. t i s m e r el y n e c e ss a r y t o s el e ct e d a b a ud-r at e an d p os si bl y o t h e r op t i o ns(n um b e r o f st op b i t s, p a ri t y,e t c.) a nd l oa d (or r ea d f r om) t h e s e ri a l t r an s m i t t e r (o r r e ce i ve r)b u ff e r. S e ri al i z a t i on o f t h e d at a i n t h e a pp ro p ri at e f o rm at i s t h en h a nd l e d b y t h e h ar d w ar e ci r c ui t.Timing/counter facilities.M a n y a p p l i c a t i o n of si n gl e-c hi p m i cr oc o m p ut e rs r eq ui r e a c c u r at e ev al u at i on o f el ap s ed re a l t i m e .T hi s c an b e d e t er m i n ed b y c a r e f ul as s es sm en t of t h e ex e c ut i on t i m e of ea c h b r an c h i n a pr ogr a m b ut t hi s ra pi dl y b e c om e si n e ff i ci en t fo r al l bu t s i m pl es t pr o gr am s .T h e p re f e r r ed ap p ro a c h i s t o u s et i m e r ci r cu i t t h at ca n i nd e pe nd e nt l y c o u nt p r ec i s e t i m e i n c r em e nt s an dge n e r a t e a n i nt e r rup t a ft e r a p r es e t t i m e h as el a ps ed .Thi s t yp e o f t i m e r i su su a l l y a r r a n ge d t o b e r el o ad a bl e wi t h t h e r e qu i r e d c ou nt .Th e t i m e r t h e nd e c r em e nt s t hi s v a l u e p r od u ci n g a n i nt e r r u pt o r se t t i n g a f l a g wh e n t h ec o un t er r ea c h es z e ro.B et t e r t i m e rs t h en ha v e t h e a bi l i t y t o au t om a t i c al l yr e l o a d t h e i n i t i al co u nt v al u e. T hi s r el i e v es t he p r o gr am m e r o f t h er e s po nsi bi l i t y o f r el o ad i n g t h e c ou nt e r a nd a ss es s i n g el a ps e d t i m e b e f or e t h e t i m e r r e st a rt ed ,w hi c h ot h e rw i s e w ou nd b e n e c es s ar y i f c o nt i n uo us p r e ci s el y t i m ed i nt e rr up t s w er e r eq ui r ed(as i n a c l o c k ,f o r ex a m p l e).S om et i m esa s so ci a t e d w i t h t i m e r i s a n e v en t c ou nt e r. Wi t h t hi s f a c i l i t y t h e r e i s us u al l y a s p e ci al i n pu t pi n , t h at c a n d ri v e t he co u nt er di re c t l y.Timing components.T h e cl o ck ci r cu i t ry o f m o s t m i c ro com pu t e r s r e qu i r e s on l y s i m pl e t i m i n g c o m p on e nt s. If m ax i m um p er f o rm an ce i s r e qui r e d,a cr ys t al m us t b e u s ed t o e n s u r e t he m ax i m um cl o ck fr e qu e n c y i s a pp r o ac h ed but no t ex c e ed e d.M a n y c l o ck c i rc ui t s a l s o w o rk w i t h a r es i st o r a nd c a p a ci t or a s l ow-c os t t i m i n g c o m p on e nt s or c an b e d ri v en fr om a n ex t e rn al s o u r c e.Thi s l at t e r a r r a n ge m e nt i s u s e fu l i s ex t e rn a l s yn c h r on i z a t i o n o f t h e m i c r o c o m p u t e r i s r e qu ir ed.B:PLC[1]P LC s(pr o gr am m ab l e l o gi c al co nt ro l l e r) f a c e ev e r m o re c om pl ex c h a l l en ge s t h es e d ays . W h er e o n ce t h ey q u i et l y r e p l a ce d re l a ys a nd ga v e a n o c c a si o n al r e po rt t o a c o rp or a t e m ai n fr a m e, t h e y a r e n ow gr o u p ed i n t o c el l s, gi v e n n ew j ob a nd ne w l an gu a ge s, a n d a r e f o rc e d t o c om p et e a ga i n s t a gr o w i n g a r ra y o f co nt r ol pr od u ct s. Fo r t h i s ye a r's a nn ua l P LC t e ch nol o g y u p da t e ,w e q u er i ed P LC m ak e rs o n t h es e t opi c s a nd m o r e .Programming languagesH i gh e r l ev el P LC p r o gr am m i n g l an g ua ge s h av e b ee n ar ou n d f or s om e t i m e ,b ut l at el y t he i r po pu l ar i t y h a s m us h ro om i n g. "As R a ym o nd Le v e i l l e, v i c e p r es i d en t& ge n e r a l m a na ge r, S i e m e ns E ne rg y &A u t o m a t i on .i n c; P ro gr a m m a bl e c ont r ol s ar e b e i n g use d fo r m o r e a nd m o re s op hi s t i c at e d o p e r at i on s,l a n gu age s o t h e r t ha n l ad d e r l o gi c b ec om e m or e p r ac t i c al, e ff i ci e nt,an d pow e r f ul. F o r ex a m p l e,i t's v e r y d i ff i cu l t t o w ri t e a t ri go no m et ri c f un ct i o n us i n g l ad d e r l o gi c."La n gu a ge s ga i ni n g a c c ept a n ce i n cl u d e B o ol e an, c o nt ro l s ys t e m f l ow c h a rt i n g, a nd s uc h fu n ct i on c h a rt l a n gu a ges as G r a ph c e t an d i t s v a ri a t i o n .An d t h e r e's i n cr e a s i n g i nt e re s t in l a n gu a ges l i k e C and B AS IC.PLCs in process controlT h us f ar,P LC s h ave n ot b ee n u s ed ex t e ns i v el y f o r c o nt i n u ous p ro c es s c o nt ro l .Wi l l t hi s co nt i n ue? "Th e f ee l i n g t h a t I'v e go t t en," s a ys K e n J an not t a, m a n ge r,p ro du c t p l a n ni n g, s e ri e s O n e a nd S e ri e s S i x p ro d uc t,a t G E F a nu c N o rt h Am e ri c a ,'i s t h at P LC s w i l l b e us e d i n t h e p ro c es s i n dus t r y b u t not n e c e ss a ri l y f o r p r oc e s s c ont r ol."S e ve r al v e nd o rs-ob vi ou sl y b e t t i n g t ha t t he op po si t e w i l l h a pp en-h a v e i nt ro du c e d P LC s op t i m i z e d fo r pr o c es s ap pl i c at i o n .R i c h Rya n,m a n ge r, c o m m e r ci al m a rk e t i n g,A l l en-br a dl e y P ro gr a m m ab l e C on t rol s D i v.,c i t es P LC s's i n c r ea si n g u s e s u ch i nd ust r i es a s f oo d,c h em i c al s,an d p e t r ol e um. Rya n f e el s t h e r e are t wo t yp e s of a pp l i c at i o ns i n whi c h t h e y'r e a p p ro p ri at e. "o n e,"h e s a ys,"i s w h e r e t h e s i z e o f t h e p r o c ess co nt ro l s ys t e m t h at's b ei n g a u t om a t ed do e s n't j u s t i f y D C S[d i s t ri bu t ed c on t r ol s ys t e m].Wi t h t he st a rt i ng p r i c e t a gs o f cho s e p r od uc t s b ei ng r e l a t i v e l y h i gh, a p r o gr am m a bl ec o nt ro l l e r m a ke s s en s e fo r s m al l, l ow l oo p co un t ap pl i c at i on .Th e s e c ond i s w he r e yo u h av e t o i n t e gr at e t h e l o op cl o s el y w i t h t h e s eq u ent i a l l o gi c a l.B a t ch c on t rol l er s a r e p ri m e ex a m pl e ,wh e r e t h e s e qu e n c e and m ai nt ai ni n g t h e pr oc e s s v a ri a bl e a re i nt e rt wi n ed s o cl os e l y t h a t t h e b en e fi t s of h avi ng a p r o gr am m a bl e co nt ro l l e r t o d o th e s e qu e nti al l o gi ca l o ut we i ghs s om e o f t h e di s ad va n t a ges o f n ot h av i n g a d i st ri b ut ed con t rol s ys t e m."B i l l B a r ko vi t z, pr e si d en t o f Tr i con ex,p r ed i ct s t h at"al l fut u r e c o nt ro l l e rs t h a t co m e out i n t h e pr o c e s s c ont r ol s ys t em b us i n es s wi l l e m br a c e a l ot o f m or e P LC t e ch nol o g y a n d a l o t m o r e P LC f un ct i o n al i t y t h a n t h e y e v e r di d be f o re ."Communications and MAPC om m un i c a t i o ns are vi t a l t o a n i nd i vi du al au t om a t i o n ce l l an d t o b e a u t om a t ed f a ct o r y a s a wh ol e. We'v e h e a r d a l o t ab ou t M A P i n t h e l as t f ew ye a r s,a n d a l o t of c om p an i e s h a v e j um pe d o n t h e b an d w a gon.[2]M a n y, h o w ev e r,we r e d i sa p po i nt e d w h en a f ul l y-d e f i n ed and co m p l e t ed M AP s p e ci fi c at i on di dn't a pp e a r i m m ed i a t el y .S a ys La r r y K o m a r e k:"R i gh t n ow, M A P i s s t i l l a m ovi n g t a rget fo r t h e m a nu f a ct ur e rs, a s p e c i f i ca t i on t h at i s n ot fi n a l.P re s en t l y,f o r ex am pl e.p eo pl e ar e i nt ro du ci ng p r od u ct s t o m e e t t h e M AP2.1s t an d a rd .Ye t2.1-ba s ed pro d uc t s wi l l b e o bs o l et e w h e n t h e n ew s t an da r d f or M AP3.0 i s i nt r od u ce d."B e c a u s e o f t hi s,m a n y P LC v e nd o rs a r e h ol di n g o ff o n ful l M AP i m pl e m e nt at i o ns. O m ro n,fo r ex am p l e,h a s a n on goi n g M AP-co m p at i b i l i t y p r o gr am;[3]b ut F ra n k N e w bu rn,vi c e p r esi d en t o f O m ro n's In d us t r i alD i vi s i o n ,r ep or t s t ha t be c a us e o f t h e l ac k o f a fi rm d ef i ni t i on ,O m r on's P LC s d o n't ye t t al k t o MA P.S i n c e i t's un l i k e l y t h at an i n di vi d u al P LC wo ul d t al k t o b ro a d M AP a n yw a y, m a k e rs a r e c on c en t r a t i n g on pr o p ri et a r y n e t wo r ks. A c co r di n g t o S a l P ro v anz a no, u s e r s f e a r t h at i f t h e y do get on bo a r d an d ve nd o rs wi t h dr a w f r om M A P, t h e y'l l b e t h e o n es l e ft ho l d i n g a c om m u ni c at i o ns s t ru c t u r e t h a t's n ot s up po rt e d.Universal I/OW h i l e t h er e a r e con c e r ns ab ou t t h e l ac k o f com p at i bl e co m m uni c at i o ns b e t w e e n P LC s fr om di ff er e nt ve nd o rs,t he c on n e ct i on at t h e o t h e r en d-t h e I/O-i s ev e n m o re f r a gm ent e d .Wi t h r a r e ex c ep t i on s,I/O i s s t i l l p r op ri e t a r y .Ye t t he r e a r e t h os e wh o f e e l t h a t I/O w i l l e v e nt ua l l y b e c om e m o re un i v e rs a l .GE F a n u c i s h opi n g t o d o t h at wi t h i t s G e ni us s m a rt I/O l i n e. T h e i n d ep e nd en t I/O m a k e rs a r e p ul l i n g i n t he s a m e d i rec t i on.M a n y s a y t h a t I/O i s s u c h a h i gh-v al u e i t em t h at P LC m ak e r s wi l l a l w a ys w a nt t o k e ep i t p ro p ri et a r y .A s K en J an no t t a, s a ys: "T h e I/O i s goi ng t o b e a di sp r op or t i o n at e am ou nt o f t he h a rd w a r e s a l e. C e r t ai nl y e a c h P LC v e nd o r i s go i n g t o t r y t o p rot e ct t h at. "F o r t h at r e a so n, he s a ys, P LC m a ke r s w o n't b e gi n s el l i ng u ni v e rs al I/O s ys t em f r om ot h e r ve n do r."i f we s t ar t s e l l i n g t h a t ki n d o f p ro du c t,"s a ys j ann ot t a, "w h at d o w e m a nu f a ct ur e?"Wi t h m or e i nt el l i gen t I/O a pp e a ri n g, S a l P ro v anz a no f e el s t hi s wi l l l e adt o m o r e di ffe r e nt i at i o n am on g I/O f ro m di ff er e nt m ak er s. "W h e re t he I/O b e c om es ex t r em el y i nt el l i gen t a nd b e co m es p a rt of t h e s ys t em,"h e s a ys,"i t r e a l l y i s h a rd t o d ef i ne w hi c h i s t he I/O an d wh i c h i s C P U. It r e a l l y C P U, i f yo u w i l l, i s eq u al l y i n t e gr a t ed i nt o t h e s ys t e m as t h e I/O."Connecting PLC I/O to PCsW h i l e di ff er e nt P LC s p r ob a bl y w i l l co nt i n ue t o u s e p r op r i e t ar y I/O, s e v e ra l v en do rs m ak e i t pos s i bl e t o con n e ct5 t h ei r I/O t o IB M P C-co m p at i b l e e q ui pm en t. Al l e-bra d e l e y, C o ul d, a nd C i n ci nn at i M i l a c r on a l r e a d y h a v e, an d r u m o r ha s i t t ha t GE i s pl a nn i n g s om et hi n g al on g t h es e s a m e l i n e s .[4]Bi ll K e t el hut, m an a ge of p ro du ct p l a nn i n g a t G E F a n uc No rt h A m e ri c a ,s e es t his s o rt o f t hi n g as al t e r n a t i v e t o u ni v ers a l I/O."I t h i n k t he t r en d,i ns t ea d o f t o wa r d u ni v e r sa l I/O, wi l l be m ul t i p l e h os t i nt e r f a c e ,"h e s a ys.J od i e G l or e,di r e ct o r o f m ar ki n g, S qu a r e D Au t o m a t i o n P r od u ct s,Vi e w s i t as a n ot h er i ndi c a t i o n t h at P LC s a r e,an d h av e b e e n fo r s om e t i m e, i n du s t ri al c o m p ut e rs.PLCs VS PCsIf t h e IB M7552, t he A c t i o n In s t r um e nt s B C22,a nd o t h e r c o m p ut e rs a re a p p e ar i n g o n t h e f ac t or y f l o o r,wo n't t h i s m e a n n e w c om p e t i t i o n f o r P LC s? R i c h Rya n:"Th e re a r e som e co nt rol f un c t i o ns t ha t ar e be t t e r j ob s f or c o m p u t e rs. P r o gr am m a bl e co nt ro l l e rs ha v e b e en fo r c ed t o f i t i n t o t ho se a p pl i c a t i o ns. "Ye t, t he m a j o ri t y o f v en d or s w e s u rv e ye d d on't l i k e t h e"P C i nv a si o n" wi l l po se a pr ob l em fo r t he m.M os t s ai d t h at P LC s an d P C s a r ee n ou gh ap a rt i n a rch i t e ct ur e t ha t t h e y w i l l us u a l l y d o t h e c o nt ro l. T h e y d o n'tf e e l t h a t P C s wi l l t a k e j o bs f rom P LC s j u s t b e c au s e P LC I/O m o du l es c an n o w b e c on n ec t ed t o P C s; t h e y b e l i ev e t hi s si m pl y m e a ns t h at P LC s a nd P C s w i l l be ab l e t o sh a re t h e s am e d at a."T h e r e a r e i nh e r ent a r c hi t e ct u r al di f f er e n c es be t w e e n a ge n e r al p u rp os e c o m p ut e r,"s a ys R i c h Rya n,"a n d a p r o gr am m a bl e co nt r ol l e r .T h e r e a r e h a r dw a r e c on s t ru ct s b ui l t i nt o al m os t e v e r y m a n uf a c t ur e's p r o gr am m a bl e c o nt ro l l e r t od a y t ha t cus t o m i z e t h e h ar d w a r e t o r un l ad d er l o gi c a nd t o s ol v e m a c hi n e co d e."O ne f un d am e nt al d i ffe r e n c e h e ci t e s i s c a l l e d s t at e of t h e m a c hi n e .Rya n:"W h e n yo u s hut t h e m a c h i n e o ff, o r i nt e rr u pt t h e c yc l e,or yo u j um p t o an ot her s p ot i n t h e c yc l e,p ro gr a m m a bl e c ont r ol l e rs i nh e r en t l y r e m em b er t h e st at e of t h e m ac hi n e:w h a t t he t i m e r s w e r e,w h at t h e co un t er s w e r e,wh at t h e s t a t e s o f a l l t h e l at c hes w e r e .C om pu t e r s d o n't i n h er e nt l y d o t h at."外文资料翻译译文单片机基础单片机是电脑和集成电路发展的巅峰，有据可查的是他们也是20世纪最有意义的两大发明。