按键扫描与LED显示驱动芯片ET6218R芯片资料

ET6218REtekMicroelectronics LED Controller/driverGeneral DescriptionET6218R is an LED Controller driver on a 1/7 to 1/8 duty factor. 7 segment output lines, 4 grid output lines, 1 segment/grid output lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to ET6218R via a three-line serial interface, ET6218R pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages.Featuresz CMOS Technologyz Low Power Consumptionz Multiple Display Modes(4～5 Grid, 7～8 segment) z Key scaning(7×1 Matrix) z 8-step Dimming Circuitryz Serial Interface for Clock, Data Input/Output, Strobe Pins zAvailable in 18-pin, DIP PackagePin ConfigurationsPin DescriptionPin No.Pin NameI/ODescription5 DI/O(DIN&DOUT) I/OData I/O Pin(N-channel, Open-Drain)This pin outputs serial data at the falling edge of the shift clock andinputs serial data at the rising edge of the shift clock(starting from the lower bit)6 CLK I Clock Input PinThis pin reads serial data at the rising edge and outputs data at thefalling edge7 STB I Serial Interface Strobe PinThe data input after the STB has fallen is processed as a commandWhen this pin is “HIGH”, CLK is ignored 8 K1 I Key Data Input PinsThe data sent to these pins are latched at the end of the display cycle(Interface Pull-Low Resistor)2 GND ─ Ground Pin10~16 SG1/KS1～SG7/KS7 O Segment Output Pins(p-channel, open drain) Also acts as the Key Source 17 SG14/GR5 O Segment/Grid Output Pins 9 VDD ─ Power Supply 1,3,4,18 GR4～GR1 O Grid Output PinsINPUT/OUTPUT CONFIGURATIONSThe schematic diagrams of the input and output circuits of the logic section are shown below. 1. Input Pins ：CLK ，STB&DIN(DI/O)2.Input Pins：K13.Output Pins：DOUT(DI/O)，GR1～GR44.Output Pins：SG1～SG75.SG14/GR5Block DiagramFunctional DescriptionCOMMANDSA command is the first byte(b0～b7) inputted to ET6218R via the DI/O Pin after STB Pin has changed from HIGH to LOW State. If for some reason the STB Pin is set to HIGH while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid.Command 1：Display Mode Setting CommandsET6218R provides 2 display mode settings as shown in the diagram below：As started earlier a command isthe first one byte(b0～b7) transmitted to ET6218R via the DI/O Pin when STB is LOW. However, for these commands,the bit 3 to bit 6(b2～b5)are ignored,bit 7&bit 8(b6～b7) are given a value of 0.The Display Mode Setting Commands determine the number of segments and grids to be used (7 to 8 segments,4 to 5 grids). A display command ON must be excuted in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned ON,the7-grid, 10-segment modes is selected.MSB LSB0 0 ──── b1 b0 b2～b5：Not RelevantDisplay Mode Setting：b1,b0—0 0：4 Grids,8 Segmentsb1,b0—0 1：5 Grids,7 SegmentsCommand 2:Data Setting CommandsData Setting Commands executes the Data Write or Data Read Modes for ET6218R. The data Setting Command, the bits 5 and 6(b4,b5) are ignored, bit 7(b6) is given the value of 1 while bit 8(b7) is given the valueof 0. Please refer to the diagram below. When Power is turned ON, bit 4 to bit 1(b3～b0) are given the value of 0.MSB LSB0 1 ──b3b2b1 b0 b4,b5：Not RelevantMode Setting： b3 —0：Normal OperationMode b3—1：Test ModeAddress Increment Mode Settings(Display Mode)：b2—0：Increment Address after Data has been Writtenb2—1：Fixes AddressData Write&Read Mode Setting：b1,b0—0 0：Write Data to Display Modeb1,b0—1 0：Read Key DataET6218R KEY MATRIX&KEY INPUT DATA STORAGE RAMET6218R Key Matrix consists of 7×1 array as shown below：Each data entered by each key is stored as follows and read by a READ Command, starting from the lastCommand 3：Address Setting CommandsAddress Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of 00H to 0DH. If the address is set to 0EH or higher,the data is ignored until a valid addressis set. When power is turned ON,the address is set at 00H.MSB LSB1 1 ──b3b2b1 b0 b4,b5：Not RelevantThe address of b3～b0：00H～0DHDISPLAY MODE AND RAM ADDRESSData transmitted from an external device to ET6218R via the interface are stored in the Display RAM andare assigned address. The RAM addresses of ET6218R are given below in 8 bits unit.SG1…………SG4 SG5…………SG8 SG9…………SG12SG13…………SG1400H L 00H U 01H L 01H U DIG1 02H L 02H U 03H L 03H U DIG2 04H L 04H U 05H L 05H U DIG3 06H L 06H U 07H L 07H U DIG4 08H L 08H U 09H L 09H U DIG5 b0…………….b3 b4………………b7xxH L xxH ULower 4 bits Higher 4 bitsCommand 4：Display Control CommandsThe Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width.Please refer to the diagram below. When the power is turned ON,a 1/16 pulse width is selected and the displayedis turned OFF(the key scaning is stopped).MSB LSB1 0 ──b3b2b1 b0b4,b5 ：Not RelevantDisplay Setting： b3—0：Display OFF(Key Scan Continues)b3—1：Display ONDimming Quantity Setting：000：Pulse width=1/16001：Pulse width =2/16010：Pulse width =4/16011：Pulse width =10/16100：Pulse width =11/16101：Pulse width =12/16110：Pulse width =13/16111：Pulse width =14/16SCANNING AND DISPLAY TIMINGThe Key Scanning and Display Timing diagram is given below. One cycle of key scanning consists of 2SERIAL COMMUNICATION FORMATThe following diagram shows the ET6218R serial communication format.The DI/O(DIN,DOUT) Pin is an N-channel,open-drain pin, therefore, it is highly recommended that an external pull-up resistor(1K～10K) must be connected to DI/O.waitIt must be noted that when the data is read, the waiting time(twait) between the rising of the eighth clock that has set the command and the galling of the first clock that has read the data is greater or equal to 1µs.SWITCHING CHARACTERISTIC WA VEFORMCLK STBt setup（Data Setup Time）≥100ns t hold（Data Hold Time）≥100nst CLK-STB（Clock-Strobe Time）≥1µs t THZ（Fall Time）≤10µst TZH（Rise Time）≤1µs t PZL（Propagation Delay Time）≤100ns fosc=Ocillation Frequency t PLZ（Propagation Delay Time）≤300ns t TZL<1µs t TLZ<10µsNote：Test condition undert THZ（Pull low risistor=10kΩ，Loading capacitor=300pf）t TLZ（Pull low risistor=10 kΩ，Loading capacitor =300pf）APPLICATIONCommand 2：Data Setting CommandCommand 3：Address Setting CommandData 1～n：Transfer Display Data(14 Bytes max) Command 4：Display Control CommandNote：1. Command 1：Display Mode Commands2. Command 2：Data Setting Commands3. Command 3：Address Setting Commands4. Command 4：Display Control CommnadsWhen IC power is applied for the first time, the contents of the Display RAM is not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting.Absolute Maximum Ratings（Ta = 25℃，GND = 0V）Parameter Symbol Ratings UnitSupply V oltage V DD-0.5～+7 VLogic Input V oltage V I-0.5～V DD+0.5 VDriver Output Current I OLGR +250 mA I OHSG -50 mAMaximum Driver Output Current/Total I TOTAL 400 mA Operating Temperature T opr-40～+85 ℃Storage Temperature T stg-55～+150 ℃Recommended Operating Range（Ta = -20～+70℃，GND = 0V）Parameter Symbol Min. Typ. Max. Unit Logic Supply V oltage V DD 3 5 5.5 V Dynamic Current(see Note)I DDdyn—— 5 mA High-Level Input V oltage V IH 0.6V DD—V DD VLow- Level Input V oltage V IL 0 —0.3V DD V Note：Test Condition：Set Display Control Commands=80H(Display Turn OFF State&under no load)Electrical Characteristics（V DD = 5V，GND = 0V，Ta = 25℃）Parameter Symbol Test Condition Min. Typ. Max.UnitHigh-Level Output Current I OHSG1V O =V DD-2V，SG1～SG7,SG14-20 -25 -40 mA I OHSG2V O =V DD-3V，SG1～SG7,SG14-25 -30 -50 mALow-Level Output Current I OLGR V O =0.3V，GR1～GR5, 100 140 —mA Low-Level Output Current I OLDOUT V O =0.4V 4 ——mASegment High-Level Output Current Tolerance I TOLSGV O =V DD-3V，SG1～SG7,SG14——+5 %High-Level Input V oltage V IH—0.6V DD— 5 VLow-Level Input V oltage V IL—0 —0.3V DDVOscillation Frequency fosc 350 500 650 kHz K1 Pull Down Resistor R KN V DD=5V 40—100 kΩ（V DD =3V , GND=0V , Ta=25℃）Parameter Symbol Test Condition Min. Typ. Max.Unit High-Level Output Current I OHSG1 V O = V DD -2V ，SG1～SG7,SG14-15 -20 -35 mALow-Level Output CurrentI OLGR V O =0.3V ，GR1～GR5, 100 140 — mA Low-Level Output Current I OLDOUT V O =0.4V 4 — — mASegment High-Level Output Current Tolerance I TOLSG V O = V DD -3V ，SG1～SG7,SG14— — +5% High-Level Input V oltage V IH — 0.8V DD—3.3 V Low-Level Input V oltage V IL — 0 — 0.3V DDVOscillation Frequency fosc 300 420 580 kHz K1 Pull Down ResistorR KN V DD =3V 40 —100 k Ω Application CircuitCOMMON CATHODE TYPE LED PANELNote ：1. The capacitor(0.1µF)connected between the GND and VDD pins must be located as close as possible to the ET6218R chip.Package Dimension。