VHDL点阵显示

数字电路课程设计报告课程：基于FPGA的点阵显示控制器的设计学院：电气信息工程学院专业：测控技术与仪器班级：姓名：学号：合作者姓名：日期：一、引言随着我国经济的高速发展,对公共场合发布信息的需求日益增长，利用LED 点阵滚动显示汉字的出现正好适应了这一市场需求，已经成为信息传播的一种重要手段。

采用传统方法设计的汉字滚动显示器，通常需要使用单片机、存储器和制约逻辑电路来进行PCB板级的系统集成。

尽管这种方案有单片机软件的支持较为灵活，但是由于受硬件资源的限制，未来对设计的变更和升级，总是难以避免要付出较多研发经费和较长投放市场周期的代价。

随着电子设计自动化（EDA）技术的进展，基于可编程FPGA器件进行系统芯片集成的新设计方法，也正在快速地到代基于PCB板的传统设计方式。

因此，基于FPGA和VHDL语言实现在8*8点阵上的汉字静态或一屏显示问题。

二、课题要求（1）技术要求1根据电路特点，用层次设计概念。

将此设计任务分成若干模块，规定每一模块的功能和各模块之间的借口，透视加深层次化设计概念；2软件的原件管理深层含义，以及模块元件之间的连接概念，对于不同目录下的同一设计，如何熔合；3适配划分前后的仿真内容有何不同概念，仿真信号对象有何不同，有更深一步了解。

熟悉了FPGA设计的调试过程中手段的多样化；4按适配划分后的管脚定位，同相关功能块硬件电路接口连线；（2）功能要求1在8*8点阵上显示汉字2可以静态显示或一屏显示3利用拨码开关来实现静态显示与一屏显示切换（3）本人的工作三、设计方案（1）工作原理8*8点阵原理：按照要求可知，点阵模块，共由8*8=64个发光二极管组成，如何在该点阵模块上显示汉字是本实验的关键。

先将要显示的每幅图像画在8*8共64个小方格的矩形框中，再在有笔划下落处的小方格里填上“1”，五笔划处填上“0”，这样就形成了与这个汉字所对应的二进制数据在该矩形矿上的分布以“正”为例，点阵分布为：1000000010000001111100011000000111111111100010011000100110000000（2）原理框图四、单元电路设计，仿真结果与分析（1）静态显示“正”library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_Unsigned.all;use ieee.std_logic_ARITH.all;ENTITY peng isport(clk,en:in std_logic;lie:out std_logic_vector(7 downto 0); --列com:out std_logic_vector(7 downto 0));--行End peng;Architecture a of peng issignal st1:std_logic_vector(7 downto 0);signal osc:std_logic;signal osd:std_logic;signal d_ff:std_logic_vector(27 downto 0);signal data:std_logic_vector(7 downto 0);signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7 downto 0);signal lie0,lie1,lie2,lie3,lie4,lie5,lie6,lie7:std_logic_vector(7 downto 0);Begincom<=data;lie<=st1;d0<="10000000";d1<="10000001";d2<="11110001";d3<="10000001";d4<="11111111";d5<="10001001";d6<="10001001";d7<="10000000";--字库正First:processbeginwait until clk='1';if(d_ff(27 downto 0)>=2e8)thend_ff(27 downto 0)<="0000000000000000000000000000";elsed_ff(27 downto 0)<=d_ff+1;end if;osc<=not d_ff(10);end process first;second:process(osc)beginif(osc='1' and osc'event and en='0')thenif st1(7 downto 0)="00000000"or st1(7 downto 0)="01111111"then st1(7 downto 0)<="11111110";data<=d0;elsif st1(7 downto 0)="11111110"thenst1(7 downto 0)<="11111101";data<=d1;elsif st1(7 downto 0)="11111101"thenst1(7 downto 0)<="11111011";data<=d2;elsif st1(7 downto 0)="11111011"thenst1(7 downto 0)<="11110111";data<=d3;elsif st1(7 downto 0)="11110111"thenst1(7 downto 0)<="11101111";data<=d4;elsif st1(7 downto 0)="11101111"thenst1(7 downto 0)<="11011111";data<=d5;elsif st1(7 downto 0)="11011111"thenst1(7 downto 0)<="10111111";data<=d6;elsif st1(7 downto 0)="10111111"thenst1(7 downto 0)<="01111111";data<=d7;end if;end if;end process second;end a;（2）一屏显示“上下五千年”Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity weng isPort(Clk,en:in std_logic;lie:out std_logic_vector(7 downto 0);--列Com:out std_logic_vector(7 downto 0));--行End weng;Architecture a of weng issignal st1:std_logic_vector(7 downto 0);signal osc:std_logic;signal osd:std_logic;signal d_ff:std_logic_vector(27 downto 0);signal data:std_logic_vector(7 downto 0);signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7 downto 0);signal lie0,lie1,lie2,lie3,lie4,lie5,lie6,lie7:std_logic_vector(6 downto 0);begincom<=data;lie<=st1;D0<="10000000"when lie0(6 downto 0)="0000000"else"00000001"when lie0(6 downto 0)="0000001"else"10000000"when lie0(6 downto 0)="0000010"else"00010000"when lie0(6 downto 0)="0000011"else"00100100"when lie0(6 downto 0)="0000100"else"00000000";D1<="10000000"when lie0(6 downto 0)="0000000"else"00000001"when lie0(6 downto 0)="0000001"else"10001001"when lie0(6 downto 0)="0000010"else"00010100"when lie0(6 downto 0)="0000011"else"00111011"when lie0(6 downto 0)="0000100"else"00000000";D2<="10000000"when lie0(6 downto 0)="0000000"else"00000001"when lie0(6 downto 0)="0000001"else"10001001"when lie0(6 downto 0)="0000010"else"00010100"when lie0(6 downto 0)="0000011"else"00101010"when lie0(6 downto 0)="0000100"else"00000000";D3<="11111111"when lie0(6 downto 0)="0000000"else "11111111"when lie0(6 downto 0)="0000001"else "11111111"when lie0(6 downto 0)="0000010"else "11111100"when lie0(6 downto 0)="0000011"else "00101010"when lie0(6 downto 0)="0000100"else "00000000";D4<="10010000"when lie0(6 downto 0)="0000000"else "00001001"when lie0(6 downto 0)="0000001"else "10001001"when lie0(6 downto 0)="0000010"else "00010010"when lie0(6 downto 0)="0000011"else "11111110"when lie0(6 downto 0)="0000100"else "00000000";D5<="10010000"when lie0(6 downto 0)="0000000"else "00010001"when lie0(6 downto 0)="0000001"else "10001001"when lie0(6 downto 0)="0000010"else "00010001"when lie0(6 downto 0)="0000011"else "00101010"when lie0(6 downto 0)="0000100"else "00000000";D6<="10010000"when lie0(6 downto 0)="0000000"else "00100001"when lie0(6 downto 0)="0000001"else "11111000"when lie0(6 downto 0)="0000010"else "00010000"when lie0(6 downto 0)="0000011"else "00101010"when lie0(6 downto 0)="0000100"else "00000000";D7<="10000000"when lie0(6 downto 0)="0000000"else "00000001"when lie0(6 downto 0)="0000001"else "10000000"when lie0(6 downto 0)="0000010"else "00010000"when lie0(6 downto 0)="0000011"else "00100000"when lie0(6 downto 0)="0000100"else "00000000";first:processbeginwait until clk='1';if(d_ff(27 downto 0)>=2e8)thend_ff(27 downto 0)<="0000000000000000000000000000"; elsed_ff(27 downto 0)<=d_ff+1;end if;osc<=not d_ff(10);osd<=not d_ff(26);end process first;second:process(osc)beginif(osc='1' and osc'event and en='0')thenif st1(7 downto 0)="00000000"or st1(7 downto 0)="01111111"then st1(7 downto 0)<="11111110";data<=d0;elsif st1(7 downto 0)="11111110"thenst1(7 downto 0)<="11111101";data<=d1;elsif st1(7 downto 0)="11111101"thenst1(7 downto 0)<="11111011";data<=d2;elsif st1(7 downto 0)="11111011"thenst1(7 downto 0)<="11110111";data<=d3;elsif st1(7 downto 0)="11110111"thenst1(7 downto 0)<="11101111";data<=d4;elsif st1(7 downto 0)="11101111"thenst1(7 downto 0)<="11011111";data<=d5;elsif st1(7 downto 0)="11011111"thenst1(7 downto 0)<="10111111";data<=d6;elsif st1(7 downto 0)="10111111"thenst1(7 downto 0)<="01111111";data<=d7;end if;end if;end process second;third:process(osd)beginif(osd='1' and osd'event and en='0')thenif lie0(6 downto 0)="0000100"thenlie0(6 downto 0)<="0000000";else lie0(6 downto 0)<=lie0+1;end if;end if;end process third;end a;五．顶层文件电路设计，仿真结果与分析顶层文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_Unsigned.all;use ieee.std_logic_ARITH.all;entity zong isport( a:in std_logic_vector(1 downto 0);clk:in std_logic;hang:out std_logic_vector(7 downto 0);lie:out std_logic_vector(7 downto 0));end entity zong;architecture one of zong iscomponent peng isport(clk,en:in std_logic;lie:out std_logic_vector(7 downto 0); --列com:out std_logic_vector(7 downto 0));end component;component weng isPort(Clk,en:in std_logic;lie:out std_logic_vector(7 downto 0);--列Com:out std_logic_vector(7 downto 0));--行end component;signal h1,h2:std_logic_vector(7 downto 0);signal l1,l2:std_logic_vector(7 downto 0);beginu1:peng port map(clk=>clk,en=>a(1),com=>h1,lie=>l1); u2:weng port map(clk=>clk,en=>a(0),com=>h2,lie=>l2); hang<=h1 or h2;lie<=l1 or l2;end architecture one;六、调试结果创建工程在Quartus II 中新建一个VHDL File文件，将vhdl代码输入这个文件，并保存到工作目录，名为zong.vhd。