IC Project Management-芯片项目管理培训教程

32, 200 MHz 32 200 MHz, cacheable
LMAU
NL-Port5 2.1
Gb/sec Fabric PTP PoFrtCBA-L2
NL-Port5 Port 2A.1
Gb/sec Fabric PTP FC A-L2
InternalBus
32, 200 MHz, cacheable 32, 200 MHz
Flash Interface
AHB Control
APB Interface
APB
Embed. ICE
DTCM
200 MHz ARM946E-S
32, 200 MHz, AHB
UART
Gigablaze 1.06/2.12
SERDES
Thor ASIC
Zou Zhige
EST-ICC
7
Behavior (Function) Simulation
IC Project Management
— — Phases of ASIC Project
Zou Zhige
Huazhong University of Science and Technology, Wuhan, China EST- ICC
Outline
• List of Phase • Prestudy Phase • Top-level Design Phase • Module Spec Phase • Module design • Subsystem Simulation • System Sim/Syn • Layout & Backend Phase • Post-layout sim/Syn • ASIC Sing-Off • Testing • Tor
expectation.
Schematic
ExOpuetcptuattioWnaWveave function wrong
X
Y
Z
timing wrong
Zou Zhige
Cell Library
I
Z
NOT IA
IA
Z
IB AND Z
EST-ICC
IB OR
Zou Zhige
EST-ICC
4
A Simple Case
• Spec • Coding • Simulation • Syntheses • Place and Layout • Extract • Post Simulation • Sign off
Zou Zhige
EST-ICC
5
ASIC Design Flow
Zou Zhige
EST-ICC
11
Logic Synthesis
• translates RTL design to gate-level design
:: aalwlwaayyss@@(p(poosseeddggeecclklk))bbeegginin
ifif(s(seel1l1))bbeegginin ifif(s(seel2l2)) oouut=t=inin11;; eelslsee oouut=t=inin22;;
Expectation Wave
module counter(cnt , clk, data, rst , load); output [3:0] cnt; input [3:0] data; input clk, rst, load; reg [3:0] cnt;
always @(posedge clk) begin if(rst ==1'b1 && load==1 'b1) cnt = data; else if(rst ==1'b1 && load==1 'b0) cnt = cnt + 1; end
• Describe the circuit behavior with Verilog HDL.
• Behavior Simulation must be done for right function.
• Compare the Simulation result and expectation.
• System level Design • Module Spec • Module Implementation • Subsystem Simulation • System Simulation/Synthesis • Layout • Post-layout sim/Syn • ASIC Sign-Off • Testing • A Simple Example
OK
A
X
B
Y
C
Z
OK
I
Z
IA
Z
NOT IA
IB AND
Z
IB OR
Zou Zhige
EST-ICC
17
HSPICE— Simulation EDA tools
• Extractive Timing Simulation by HSPICE.
1st: Schematic à netlist in Hspice format
Zou Zhige
EST-ICC
2
ASIC Design
Flow
Zou Zhige
EST-ICC
3
Levels of Design Abstraction
u Consider entire design at top levels only
u Increasing amounts of automation possible further down the stack
Small
timing constraint
modu e ifmod(clk, out, in1, in2, i n3, in4 , sel4 );
output out; in put clk, in 1, in2, in3, i n4; in put sel1, sel 2, sel3, sel4; reg out;
sel1, sel2, sel3,
always @(posedge cl k) begi n if (sel1) begin if (sel2) out=in 1; else out=in 2;
Optimization
Translation
Fast
Speed
Slow
Zou Zhige
Zou Zhige, EST,
endmodule
Zou Zhige
EST-ICC
10
Re-Simulation
•After behavior description is modified, Re-Simulate the code till the simulation according with the expectation.
33-133
MHz
Embed. ICE
DTCM
200MHz ARM946E-S
32, 200 MHz, AHB
AHB Control
Flash Interface
UART
APB APB Interface
Gigablaze
1.06/2.12 SERDES
InternalBus DMA
DMA
64, 200 MHz
Zou Zhige
Large
Area
Small Fast
EST-ICC
RTL Design
Technology A
Technology B
Speed
Slow
14
Gate Level Simulation
• Gate level simulation must be done after
synthesis.
endmodule
clk
function wrong
2
5
6
7
cnt
2
560
Zou Zhige
EST-ICC
9
Modify Description
Check out the fault and modify it.
module counter(cnt , clk, data, rst, load); output [3:0] cnt; input [3:0] data; input clk, rst, load; reg [3:0] cnt;
13
HUST EST-ICC
Logic Synthesis
• Synthesis Handles Technology Independent Design
• A RTL design can be mapped to several different technology, designers can choose that meets their requirement
always @(posedge clk) begin
if(rst=='b11 && load='=b11) cnt = data;
else if(rst='=b1 && load='=b10) cnt = cnt + 1;
end endmodule
Modify function
module counter(cnt , clk, data, rst, load); output [3:0] cnt; input [3:0] data; input clk, rst, load; reg [3:0] cnt; always @(rst) begin if(!rst) assign cnt '=b04; else deassign cnt; end always @(posedge clk) begin if(rst=='b11 && load='=b11) cnt = data; else if(rst='=b1 && load='=b10) cnt = cnt + 1; end