每层电梯的入口处设有上下请求开关

1、 每层电梯的入口处设有上下请求开关，电梯内设有乘客到达层次的停站请求开关。 2、 设有电梯所处位置指示装置及电梯运行模式（上升或下降）指示装置。 3、 电梯每秒升降一层。 4、 电梯到达有停站请求的楼层后，经过1s电梯打开，开门只是灯亮，开门4s后，电梯门关闭（关门指示灯灭），电梯继续运行，直至执行完请求信号后停在当前楼层。

5、 能记忆电梯内外的所以请求信号，并按照电梯运行规则依次响应，每个请求信号保留至执行后消除。

6、 电梯运行规则：当电梯处于上升模式时，只响应比电梯所在位置高的上楼信号，由下至上依次执行，直到最后一个上楼请求执行完毕，如更高层有下楼请求时，则直接升到有下降请求的最高楼接客，然后进入下降模式，但电梯处于下降模式时，则与上升模式相反。

7、 电梯初始状态为一层门开。

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity led1 is port(ledin:in std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0)); end led1;

architecture a_led of led1 is begin process(ledin) begin case ledin is --The sequence is "g f e d c b a" when "0000" => ledout<="0111111"; -- " show 0 " when "0001" => ledout<="0000110"; -- " show 1 " when "0010" => ledout<="1011011"; -- " show 2 " when "0011" => ledout<="1001111"; -- " show 3 " when "0100" => ledout<="1100110"; -- " show 4 " when "0101" => ledout<="1101101"; -- " show 5 " when "0110" => ledout<="1111101"; -- " show 6 " when "0111" => ledout<="0000111"; -- " show 7 " when "1000" => ledout<="1111111"; -- " show 8 " when "1001" => ledout<="1101111"; -- " show 9 " when "1010" => ledout<="1110111"; -- " show 10 " when "1011" => ledout<="1111100"; -- " show 11 " when "1100" => ledout<="0111001"; -- " show 12 " when "1101" => ledout<="1011110"; -- " show 13 " when "1110" => ledout<="1111001"; -- " show 14 " when "1111" => ledout<="1110001"; -- " show 15 " when others => ledout<="XXXXXXX"; --必须有,Here it is 'X',single quote end case; end process ; end a_led; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;

entity lift1 is port ( clk: in STD_LOGIC; --2hz信号 upin: in STD_LOGIC; --上升请求键 downin: in STD_LOGIC; --下降请求键 st_ch: in STD_LOGIC; --楼层选择键 close: in STD_LOGIC; --提前关门键 delay: in STD_LOGIC; --延时关门键 run_stop: in STD_LOGIC; --电梯运行开关 lamp: out STD_LOGIC; --运行或停止灯 run_waitdis: out STD_LOGIC_VECTOR (6 downto 0); --运行或等待时间 st_outdis: out STD_LOGIC_VECTOR (6 downto 0); --电梯所在楼层指示 directdis: out STD_LOGIC_VECTOR (6 downto 0) --楼层选择指示 ); end lift1;

architecture lift1_arch of lift1 is component led1 port(ledin:in std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0)); end component;

signal ur,dr:STD_LOGIC_VECTOR (6 downto 1); signal dir,liftor:integer range 0 to 5; signal wai_t:STD_LOGIC_VECTOR (2 downto 0); signal divide,hand,clkin:STD_LOGIC; signal ladd:STD_LOGIC_VECTOR (1 downto 0); signal closex,delayx:STD_LOGIC; signal run_wait: STD_LOGIC_VECTOR (3 downto 0); signal st_out: STD_LOGIC_VECTOR (3 downto 0); signal direct: STD_LOGIC_VECTOR (3 downto 0);

begin direct<='0'&conv_std_logic_vector(dir,3)+1; st_out<='0'&conv_std_logic_vector(liftor,3)+1; run_wait<='0'&wai_t; lamp<=ladd(1); hand<=wai_t(2) and (not wai_t(1)) and wai_t(0); closex<=close and (not ladd(1)); delayx<=delay and (not ladd(1));

urun_wait:led1 port map(run_wait,run_waitdis); ust_out:led1 port map(st_out,st_outdis); udirect:led1 port map(direct,directdis);

p0:process(clk) begin if (clk'event and clk='1') then clkin<=not clkin; end if; end process p0;

p1:process(clkin) begin if (clkin'event and clkin='1') then divide<=not divide; if (dir=5) then dir<=0; else dir<=dir+1; end if; end if; end process p1;

p2:process(ur,dr,dir,upin,downin,st_ch,liftor,wai_t,run_stop,hand) variable num,t:integer range 0 to 6; begin num:=liftor+1; t:=dir+1; if (run_stop='1') then if (((t>num) and (st_ch='1')) or (upin='1')) then case t is when 1 => ur(1)<='1'; when 2 => ur(2)<='1'; when 3 => ur(3)<='1'; when 4 => ur(4)<='1'; when 5 => ur(5)<='1'; when 6 => ur(6)<='1'; when others =>Null; end case; elsif (hand='1') then case num is when 1 => ur(1)<='0'; when 2 => ur(2)<='0'; when 3 => ur(3)<='0'; when 4 => ur(4)<='0'; when 5 => ur(5)<='0'; when 6 => ur(6)<='0'; when others =>Null; end case; end if; if (((tcase t is when 1 => dr(1)<='1'; when 2 => dr(2)<='1'; when 3 => dr(3)<='1'; when 4 => dr(4)<='1'; when 5 => dr(5)<='1'; when 6 => dr(6)<='1'; when others =>Null; end case; elsif (hand='1') then case num is when 1 => dr(1)<='0'; when 2 => dr(2)<='0'; when 3 => dr(3)<='0'; when 4 => dr(4)<='0'; when 5 => dr(5)<='0'; when 6 => dr(6)<='0'; when others =>Null; end case; end if; else ur<="000000"; dr<="000000"; end if; end process p2;