PAL audit - PAV relocation (RBAC_update version)30-31 Jul'09_20100506
LTE信令流程详解
L T E信令流程详解集团标准化工作小组 #Q8QGGQT-GX8G08Q8-GNQGJ8-MHHGN#LTE信令流程目录概述本文通过对重要概念的阐述，为信令流程的解析做铺垫，随后讲解LTE中重要信令流程，让大家熟悉各个物理过程是如何实现的，其次通过异常信令的解读让大家增强对异常信令流程的判断，再次对系统消息的解析，让大家了解系统消息的特点和携带的内容。
最后通过实测信令内容讲解，说明消息的重要信元字段。
第一章协议层与概念1.1控制面与用户面在无线通信系统中，负责传送和处理用户数据流工作的协议称为用户面；负责传送和处理系统协调信令的协议称为控制面。
用户面如同负责搬运的码头工人，控制面就相当于指挥员，当两个层面不分离时，自己既负责搬运又负责指挥，这种情况不利于大货物处理，因此分工独立后，办事效率可成倍提升，在LTE网络中，用户面和控制面已明确分离开。
1.2接口与协议接口是指不同网元之间的信息交互时的节点，每个接口含有不同的协议，同一接口的网元之间使用相互明白的语言进行信息交互，称为接口协议，接口协议的架构称为协议栈。
在LTE中有空中接口和地面接口，相应也有对应的协议和协议栈。
信令流数据流图1 子层、协议栈与流图2 子层运行方式LTE系统的数据处理过程被分解成不同的协议层。
简单分为三层结构：物理层、数据链路层L2和网络层。
图1阐述了LTE系统传输的总体协议架构以及用户面和控制面数据信息的路径和流向。
用户数据流和信令流以IP包的形式进行传送，在空中接口传送之前，IP包将通过多个协议层实体进行处理，到达eNodeB后，经过协议层逆向处理，再通过S1/X2接口分别流向不同的EPS实体，路径中各协议子层特点和功能如下：1.2.1NAS协议（非接入层协议）处理UE和MME之间信息的传输，传输的内容可以是用户信息或控制信息（如业务的建立、释放或者移动性管理信息）。
它与接入信息无关，只是通过接入层的信令交互，在UE和MME之间建立起了信令通路，从而便能进行非接入层信令流程了。
libpcap主要函数及过程详解
libpcap主要函数及过程详解/uid-21556133-id-120228.htmllibpcap（Packet Capture Library），即数据包捕获函数库，是Unix/Linux平台下的⽹络数据包捕获函数库。
它是⼀个独⽴于系统的⽤户层包捕获的API接⼝，为底层⽹络监测提供了⼀个可移植的框架。
⼀、libpcap⼯作原理libpcap主要由两部份组成：⽹络分接头(Network Tap)和数据过滤器(Packet Filter)。
⽹络分接头从⽹络设备驱动程序中收集数据拷贝，过滤器决定是否接收该数据包。
Libpcap利⽤BSD Packet Filter(BPF)算法对⽹卡接收到的链路层数据包进⾏过滤。
BPF算法的基本思想是在有BPF监听的⽹络中，⽹卡驱动将接收到的数据包复制⼀份交给BPF过滤器，过滤器根据⽤户定义的规则决定是否接收此数据包以及需要拷贝该数据包的那些内容，然后将过滤后的数据给与过滤器相关联的上层应⽤程序。
libpcap的包捕获机制就是在数据链路层加⼀个旁路处理。
当⼀个数据包到达⽹络接⼝时，libpcap⾸先利⽤已经创建的Socket从链路层驱动程序中获得该数据包的拷贝，再通过Tap函数将数据包发给BPF过滤器。
BPF过滤器根据⽤户已经定义好的过滤规则对数据包进⾏逐⼀匹配，匹配成功则放⼊内核缓冲区，并传递给⽤户缓冲区，匹配失败则直接丢弃。
如果没有设置过滤规则，所有数据包都将放⼊内核缓冲区，并传递给⽤户层缓冲区。
⼆、libpcap的抓包框架pcap_lookupdev()函数⽤于查找⽹络设备，返回可被pcap_open_live()函数调⽤的⽹络设备名指针。
pcap_open_live()函数⽤于打开⽹络设备，并且返回⽤于捕获⽹络数据包的数据包捕获描述字。
对于此⽹络设备的操作都要基于此⽹络设备描述字。
pcap_lookupnet()函数获得指定⽹络设备的⽹络号和掩码。
pcap_compile()函数⽤于将⽤户制定的过滤策略编译到过滤程序中。
WCDMA信令超级详解(包含参数)
WCDMA信令超级详解（包含参数）目录WCDMA信令超级详解（包含参数） (1)第一章呼叫信令详解（前后台） (3)1.1、重点关注参数解释 (3)1.2、呼叫流程信令图 (3)1.2.1 建立RRC连接 (3)1.2.2 直传信令连接建立（含鉴权和加密） (4)1.2.3 RAB建立过程 (5)1.2.4 振铃，接通 (6)1.3、呼叫过程前后台信令解析 (8)1.3.1 RRC CONNECTION REQUEST (8)1.3.2 RRC CONNECTION SETUP (9)1.3.3 RRC CONNECTION COMPLETE (11)1.3.4 RRC_INIT_DIRECT_TRANSF (12)1.3.5 RANAP_INITIAL_UE_MESSAGE (13)1.3.6 RANAP_COMMON_ID (14)1.3.7 RANAP_RAB_ASSIGNMENT_REQ (15)1.3.8 RANAP_DIRECT_TRANSF (16)1.4、呼叫异常信令解析 (17)1.4.1 RRC连接建立中异常流程 (17)1.4.2 RAB建立中异常信令 (21)第二章切换信令详解（前后台） (24)2.1 RNC内切换 (24)R NC内切换信令图 (24)2.2 RNC间切换 (27)RNC间切换信令图 (27)2.3 切换前后台信令解析 (30)2.3.1 MEASUREMENT CONTROL (30)2.3.2 MEASUREMENT REPORT (35)2.3.3 NBAP_RL_SETUP_RSP（RNC内） (37)2.3.4 NBAP_RL_DEL_REQ（RNC内） (38)2.3.5 PHYSICAL CHANNEL RECONFIGURA TION（RNC内） (39)2.3.6 RANAP_RELOCA TION_REQUIRED（RNC间） (41)2.3.7 RANAP_RELOCA TION_REQ_ACK（RNC间） (44)2.3.8 RANAP_RELOCA TION_COMMAND（RNC间） (45)2.3.9 PHYSICAL CHANNEL RECONFIGURA TION（RNC间） (45)2.3.10 RANAP_RELOCATION_DETECT（RNC间） (47)2.3.11 RANAP_RELOCATION_COMPLETE（RNC间） (48)2.4 切换异常信令解析 (49)2.4.1 RNC内异常信令 (49)2.4.2 RNC间异常信令 (52)第三章呼叫释放信令详解（前后台） (56)3.1 呼叫释放流程信令图 (56)3.2 呼叫释放过程前后台信令解析 (59)3.2.1 RANAP_IU_RELEASECOMMAND (59)3.2.2 RRC_RRC_CONN_REL (59)3.2.3 NBAP_RL_DEL_REQ (60)3.3 导致呼叫释放的异常分析 (61)3.3.1 CN发起Uu接口释放 (61)3.3.2 UE发起Uu接口释放 (62)3.3.3 Uu接口RRC连接释放 (62)3.3.4 Iu接口释放 (62)附录：RRC，RL，RB，RAB之间差别 (63)第一章呼叫信令详解（前后台）1.1、重点关注参数解释PCCPCH-RSCP:UE 测得主公共控制信道的码片功率PCCPCH-C/I: UE 测得主公共控制信道的载干比PCCPCH-Path Loss: 主公共控制信道的路损DPCH-RSCP: UE 测得专用信道的码片功率DPCH-C/I: UE 测得专用信道的载干比DPCH-ISCP:专用信道的干扰信号BLER:误块率，是一段时间内误块数与总TB 块数的比值。
Quest NetVault Backup Oracle解决方案介绍说明书
Protecting business-critical data stored in Oracle databases while keepingthat data online and available is easier when you have a solution with a plug-in specifically designed for Oracle. With Quest® NetVault Backup, you’ll be able to take full advantage of the world’s leading relational database management system. NetVault Backup gives you confidence that you can recover your Oracle environments, including Oracle Real Application Clusters (RAC) and Data Guard, while eliminating the need for complex scripting. Through an intuitive user interface and automated workflow processes, NetVault Backup offers a centralized console to help you set up, configure and define backup and restore policies for all your Oracle databases. Plus, you have the flexibility to select your preferred backup method without having to learn Oracle database internals, thanks to support for online backups via simple user-managed or full-featured Recovery Manager (RMAN) backups. NetVault Backup also offers granular control that minimizes downtime, providing youwith faster and more reliable backups and restores of complete databases, individual tablespaces or individual datafiles. Through automatic integration with a wide range of backup devices, you can be confident that your Oracle data is protected and safely stored off site to meet your disaster recovery and business continuity goals.NetVault Backup supports important features such as Oracle RAC, Data Guard, Automated Storage Management (ASM), Flashback Database and Transparent Data Encryption, and offers you advanced backup and recovery options in case of hardware failure or data loss. Protect your business-critical Oracle data with confidence and agility.NetVault Backup for OracleAward-winning protection for business-critical data stored in Oracle databasesBENEFITS:• User-managed or RMAN-basedonline backups• Support for RMAN compression• Protection for single-instance,multi-instance RAC and DataGuard environments• Protection for Oracle datain third-party (non-RAC)clustered environments• Backup Parameter, Control,Archived Redo Log Files andExternal Configuration Files• Protection down to datafile levels• Automatic instance configuration• Point-and-click graphic userinterface (GUI)KEY BENEFITSReduce risk with flexible backup and recovery — NetVault Backup gives you tools to simplify backup and recovery of business-critical Oracle databases. With NetVault Backup, you can create a comprehensive and flexible backup policy without the need to understand Oracle database internals. You have the flexibility to choose between simple user-managed or full-featured RMAN-based backups. Through point-and-click automated options, NetVault Backup reduces reliance on human interaction, which eliminates syntax errors caused by manual intervention.Minimize downtime by speeding uprestores (restore only what is needed) — NetVault Backup ensures databases remain online and fully accessible during backup operations, ensuring no user downtime. Integration withOracle’s Flashback Database maximizes availability by enabling you to rewind to a previous time to correct problems caused by logical data corruptions or user errors without restoring physical datafiles. When needed, you can perform full, incremental, and time-, SCN- and log sequence number-based, point-in-time restores. NetVault Backup is designedfor granular recoveries, enabling you to recover complete databases, individual tablespaces or individual datafiles.Increase business continuity through automatic integration with a widerange of backup devices — With off-site backups being an important part of the data protection plan for business-critical applications, NetVault Backup integrates with a wide range of storage devices, enabling you to store backup data on disk, in a virtual tape library (VTL) or on tape.ABOUT QUESTQuest helps our customers reducetedious administration tasks so they can focus on the innovation necessary for their businesses to grow. Quest® solutions are scalable, affordable and simple-to-use, and they deliver unmatched efficiency and productivity. Combined with Quest’s invitation to the global community to be a part of its innovation, as well as our firm commitment to ensuring customer satisfaction, Quest will continue to accelerate the delivery of the mostcomprehensive solutions for Azure cloud management, SaaS, security, workforcemobility and data-driven insight.Quest, NetVault and the Quest logo are trademarks and registered trademarks of Quest Software Inc. For a complete list of Quest marks, visit /legal/trademark-information.aspx. All other trademarks and registered trademarks are property of their respective owners.© 2017 Quest Software Inc. ALL RIGHTS RESERVED.DataSheet-NVBU4Oracle-US-KS-25712Quest4 Polaris Way, Aliso Viejo, CA 92656 | If you are located outside North America, you can find local office information on our Web site.。
2020最新中移网大-考试真题-L1-IT开发
本卷共150题, 总分100分已答: 0 未答: 150单选(共50分)待检查1. 下列关于聚类挖掘技术的说法中, 错误的是A.与分类挖掘技术相似的是, 都是要对数据进行分类处理B.不预先设定数据归类类目, 完全根据数据本身性质将数据聚合成不同类别C.要求同类数据的内容相似度尽可能小D.要求不同类数据的内容相似度尽可能小待检查2. 列出HDFS下的文件A.hdfs dfs -cpB.hdfs dfs -getC.hdfs dfs -lsD.hdfs dfs -cat待检查3. SQL语言中, 用GRANT／REVOKE语句实现数据库的（）A.完整性控制B.一致性控制C.安全性控制D.并发控制待检查4. （）遍历二叉排序树中的结点可以得到一个递增的关键字序列。
A.前序B.后序C.都不是D.中序待检查5. 不属于防火墙的常见功能的是A.防病毒B.防蠕虫C.防止溢出攻击D.审计待检查6. （）是以客户、业务、网络、运维等分析对象为中心进行的常规性分析。
A.专题分析B.主题分析C.联合分析D.自定义分析待检查7、以下（）不是存储过程的优点。
A.保证系统的安全性B.执行速度快C.模块化的程序设计D.会自动被触发待检查8、在集团要求各省的账户命名规范的格式为: XXX+连接符+AA, 其中的连接符代表:A.+B._C.-D..待检查9、Hive是建立在Hadoop之上的A.数据仓库B.集中日志系统C.对象管理器D.分布式配置系统待检查10、最基本的select语句可以只包括（）子句和（）子句。
A.select,order byB.select,group byC.select ,whereD.select ,from待检查11. 对于DDos攻击的描述那一个是正确的？A.DDoS攻击俗称洪水攻击B.DDoS攻击采用一对一的攻击方式C.DDoS攻击于DoS攻击毫无关系D.DDoS的中文名为扩充式拒绝服务待检查12. （）是Product backlogA.迭代B.燃尽图C.产品代办事项列表D.产品负责人待检查13. （）用来记录对数据库中数据进行的每一次更新操作。
orca软件包说明说明书
Package‘orca’December13,2023Version1.1-2Date2023-12-13Title Computation of Graphlet Orbit Counts in Sparse GraphsDescription Implements orbit counting using a fast combinatorial approach.Counts orbits of nodes and edges from edge matrix or data frame,or agraph object from the graph package.License LGPL-3Depends R(>=3.1)Enhances graphNeedsCompilation yesCollate orca.RLazyLoad yesLazyData yesAuthor Tomaz Hocevar[aut,cre],Janez Demsar[aut]Maintainer Tomaz Hocevar<************************.si>Repository CRANDate/Publication2023-12-1322:20:05UTCR topics documented:karate (2)orca (2)petersen (4)usastates (4)yeast (5)Index612orca karate Karate Club networkDescriptionThe network representing the friendships between members of a university-based karate club,which was originally used to model thefission process with a mathematical model.The network consists of34nodes(club members)and77edges(friendships).UsagekarateFormatA data frame with77observations and2columns.Sourcehttps:///data.php?id=105ReferencesW.W.Zachary(1977)An informationflow model for conflict andfission in small groups,Journal of Anthropological Research33(4),452-473.orca Orbit countingDescriptionCount the node or edge orbits in4-or5-node graphlets for all nodes(edges)in the given graph.Usagecount4(graph)count5(graph)ecount4(graph)ecount5(graph)Argumentsgraph A graph given as a nx2edge matrix,a data frame with edges or a graph object from the package’graph’.The nodes in the matrix or data frame are given byinteger indices that start with1.orca3 ValueA numeric matrix or orbit counts.Rows correspond to graph nodes or edges in the same order ason the input,and the columns corresponding to orbits.Author(s)Tomaz Hocevar and Janez DemsarReferencesTomaz Hocevar,Janez Demsar(2016):Computation of Graphlet Orbits for Nodes and Edges in Sparse Graphs.Journal of Statistical Software,71(10),pp.1-24.Exampleslibrary(orca)#Load and show the orbit counts for the Karate graphdata("karate")count4(karate)##Not run:#Simple analysis of School Wikipedia network:find the most similar#nodes with respect to the local network topology#Requires data from http://www.biolab.si/supp/Rorca/_downloads/schools-wiki.ziplibrary("FNN")nodes<-scan("schools-wiki-nodes.txt",what="",sep="\n")edges<-read.table("schools-wiki-edges.txt")orbits<-count4(edges)nn<-get.knn(orbits,k=10)neighbours<-nn$nn.indexdistances<-nn$nn.distcheck<-c("Canada","Germany","Isaac Newton","Albert Einstein","Mahatma Gandhi","Mahabharata")node_indices<-match(check,nodes)for(i in1:length(check)){cat("\n\n",check[i],":",sep="")cat(nodes[neighbours[node_indices[i],]],sep=",")cat("\n")cat(round(distances[node_indices[i],]),sep=",")}##End(Not run)4usastates petersen Petersen graphDescriptionThe Petersen graph is a graph with10vertices and15edges,usually drawn as a pentagram withina pentagon.UsagepetersenFormatA data frame with15observations and2columns.ReferencesJ.Petersen Sur la théorème de Tait.L’Intermédiare des Math.5,225-227.usastates Contiguous USA GraphDescriptionThe nodes of Contiguous USA Graph represent the49contiguous states of the USA.Two nodes are connected if there exists at least one driveable road between the corresponding states.UsageusastatesFormatA data frame with107observations and2columns.Source/~uno/contiguous-usa.datReferencesD.E.Knuth(2008)The Art of Computer Programming,Volume4,Fascicle0:Introduction toCombinatorial Functions and Boolean Functions,p.15.Upper Saddle River,NJ:Addison-Wesley.yeast5 yeast Yeast protein-protein interaction networkDescriptionThe network representing interactions between2361proteins.UsageyeastFormatA data frame with6646observations and2columns.Sourcehttp://vlado.fmf.uni-lj.si/pub/networks/data/bio/Yeast/Yeast.htmReferencesS.Sun,L.Ling,N.Zhang,G.Li and R.Chen(2003)Topological structure analysis of the protein-protein interaction network in budding yeast,Nucleic Acids Research,31(9),2443-2450.Index∗datasetskarate,2petersen,4usastates,4yeast,5∗graphsorca,2count4(orca),2count5(orca),2ecount4(orca),2ecount5(orca),2karate,2orca,2petersen,4usastates,4yeast,56。
AD9122器件手册
Dual, 16-Bit, 1230 MSPS,TxDAC+® Digital-to-Analog ConverterAD9122 Rev. AInformation furnished by Analresponsibility is assumed by Ana rights of third parties that may re license is granted by implication T rademarks and registered trad MA 02062-9106, U.S.A. Inc. All rights reserved.og Devices is believed to be accurate and reliable. However, nolog Devices for its use, nor for any infringements of patents or other sult from its use. Specifications subject to change without notice. No or otherwise under any patent or patent rights of Analog Devices. emarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, Tel: 781.329.4700Fax: 781.461.3113 ©2010 Analog Devices,FEATURESFlexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, R L = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidthGain and phase adjustment for sideband suppression Multiple chip synchronization interfacesHigh performance, low noise PLL clock multiplierDigital inverse sinc filterLow power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full operating conditions72-lead, exposed paddle LFCSPAPPLICATIONSWireless infrastructureW-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTEDigital high or low IF synthesisTransmit diversityWideband communications: LMDS/MMDS, point-to-point GENERAL DESCRIPTIONThe AD9122 is a dual 16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS1.Ultralow noise and intermodulation distortion (IMD)enable high quality synthesis of wideband signals frombaseband to high intermediate frequencies.2. A proprietary DAC output switching technique enhancesdynamic performance.3.The current outputs are easily configured for varioussingle-ended or differential circuit topologies.4.Flexible LVDS digital interface allows the standard 32-wirebus to be reduced to ½ or ¼ of the width.TYPICAL SIGNAL CHAINCOMPLEX BASEBANDDC COMPLEX IFf IFRFLO – f IF8281-1 Figure 1.AD9122Rev. A | Page 2 of 60TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 6 AC Specifications .......................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Differences Between the AD9122R1 and AD9122R2 ............... 18 Theory of Operation ...................................................................... 19 Serial Port Operation ................................................................. 19 Data Format ................................................................................ 19 Serial Port Pin Descriptions ...................................................... 19 Serial Port Options ..................................................................... 20 Device Configuration Register Map and Descriptions ......... 21 LVDS Input Data Ports .................................................................. 33 Word Interface Mode ................................................................. 33 Byte Interface Mode ................................................................... 33 Nibble Interface Mode ............................................................... 33 FIFO Operation .......................................................................... 33 Interface Timing ......................................................................... 35 Digital Datapath .............................................................................. 37 Premodulation ............................................................................ 37 Interpolation Filters ................................................................... 37 NCO Modulation ....................................................................... 40 Datapath Configuration ............................................................ 40 Determining Interpolation Filter Modes ................................ 41 Datapath Configuration Example ............................................ 42 Data Rates vs. Interpolation Modes ......................................... 43 Coarse Modulation Mixing Sequences .................................... 43 Quadrature Phase Correction ................................................... 44 DC Offset Correction ................................................................ 44 Inverse Sinc Filter ....................................................................... 44 DAC Input Clock Configurations ................................................ 45 DAC Input Clock Configurations ............................................ 45 Analog Outputs............................................................................... 47 Transmit DAC Operation .......................................................... 47 Auxiliary DAC Operation ......................................................... 48 Baseband Filter Implementation .............................................. 49 Driving the ADL5375-15 .......................................................... 49 Reducing LO Leakage and Unwanted Sidebands .................. 50 Device Power Dissipation .............................................................. 51 Temperature Sensor ................................................................... 52 Multichip Synchronization ............................................................ 53 Synchronization with Clock Multiplication ............................... 53 Synchronization with Direct Clocking .................................... 54 Data Rate Mode Synchronization ............................................ 54 FIFO Rate Mode Synchronization ........................................... 55 Additional Synchronization Features ...................................... 55 Interrupt Request Operation ........................................................ 57 Interrupt Service Routine .......................................................... 57 Interface Timing Validation .......................................................... 58 SED Operation ............................................................................ 58 SED Example .............................................................................. 58 Example Start-Up Routine ........................................................ 59 Outline Dimensions ....................................................................... 60 Ordering Guide .. (60)AD9122Rev. A | Page 3 of 60REVISION HISTORY3/10—Rev. 0 to Rev. AChanges to Reflect Differences Between R1 and R2Silicon................................................................................... Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Table 5 ............................................................................ 7 Change to IOVDD Rating in Table 6 .............................................. 8 Changes to Table 8 ............................................................................ 9 Changes to Figure 10 to Figure 15 ................................................ 12 Added Differences Between the AD9122R1 and AD9122R2 Section, Added Figure 36 and Figure 37; RenumberedSequentially ...................................................................................... 18 Changes to Table 10 ........................................................................ 21 Changes to Table 11 ........................................................................ 23 Changes to FIFO Operation Section ............................................ 33 Changes to Resettling the FIFO Section and Replaced Table 13; Renumbered Sequentially; Added Serial Port Initiated FIFO Reset Section, and Added FRAME Initiated Relative FIFOReset Section .................................................................................... 34 Added FRAME Initiated Absolute FIFO Reset Section andReplaced Table 14 ............................................................................ 35 Changes to Figure 54 ...................................................................... 38 Changes to Table 18 ........................................................................ 39 Changes to SED Example Section ................................................. 58 Added Example Start-Up Routine Section .................................. 59 9/09—Revision 0: Initial VersionAD9122Rev. A | Page 4 of 60FUNCTIONAL BLOCK DIAGRAMD15P—D15ND0P—D0NIOUT1P IOUT1NIOUT2P IOUT2NFSADJREFIO DCI FRAME08281-002Figure 2. AD9122 Functional Block DiagramAD9122Rev. A | Page 5 of 60SPECIFICATIONSDC SPECIFICATIONST MIN to T MAX , AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 =1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1.Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR Full-Scale Output Current 18.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V POWER CONSUMPTION 2× Mode, f DAC = 491.22 MSPS, IF = 10 MHz, PLL Off 834 mW 2× Mode, f DAC = 491.22 MSPS, IF = 10 MHz, PLL On 913 mW 8× Mode, f DAC = 800 MSPS, IF = 10 MHz, PLL Off 1135 1241 mWAVDD33 55 57 mA CVDD18 85 90 mA DVDD18 444 495 mA Power-Down Mode (Register 0x01 = 0xF1) 6.5 18.8 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V OPERATING RANGE −40 +25 +85 °C1Based on a 10 kΩ external resistor.AD9122Rev. A | Page 6 of 60DIGITAL SPECIFICATIONST MIN to T MAX , AVDD33 = 1.8 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted.1LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.DIGITAL INPUT DATA TIMING SPECIFICATIONSTable 3.Parameter Min Typ Max UnitLATENCY (DACCLK Cycles) 1× Interpolation (With or Without Modulation) 64 Cycles 2× Interpolation (With or Without Modulation) 135 Cycles 4× Interpolation (With or Without Modulation) 292 Cycles 8× Interpolation (With or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Power-Up Time 260 msAD9122Rev. A | Page 7 of 60AC SPECIFICATIONST MIN to T MAX , AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4.ParameterMin Typ Max UnitSPURIOUS-FREE DYNAMIC RANGE (SFDR) f DAC = 100 MSPS, f OUT = 20 MHz 78 dBc f DAC = 200 MSPS, f OUT = 50 MHz 80 dBc f DAC = 400 MSPS, f OUT = 70 MHz 69 dBc f DAC = 800 MSPS, f OUT = 70 MHz72 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) f DAC = 200 MSPS, f OUT = 50 MHz 84 dBc f DAC = 400 MSPS, f OUT = 60 MHz 86 dBc f DAC = 400 MSPS, f OUT = 80 MHz 84 dBc f DAC = 800 MSPS, f OUT = 100 MHz81 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f DAC = 200 MSPS, f OUT = 80 MHz −162 dBm/Hz f DAC = 400 MSPS, f OUT = 80 MHz −163 dBm/Hz f DAC = 800 MSPS, f OUT = 80 MHz−164 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f DAC = 491.52 MSPS, f OUT = 10 MHz 84 dBc f DAC = 491.52 MSPS, f OUT = 122.88 MHz 82 dBc f DAC = 983.04 MSPS, f OUT = 122.88 MHz 83 dBc W-CDMA SECOND ACLR, SINGLE CARRIER f DAC = 491.52 MSPS, f OUT = 10 MHz 88 dBc f DAC = 491.52 MSPS, f OUT = 122.88 MHz 86 dBc f DAC = 983.04 MSPS, f OUT = 122.88 MHz88dBcTable 5. Interface SpeedsBus Width Interpolation Factorf BUS (Mbps)1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 5% Nibble (4 Bits) 1×1100 1200 1230 2× (HB1) 1100 1200 1230 2× (HB2) 1100 1200 1230 4× 1100 1200 1230 8× 1100 1200 1230 Byte (8 Bits) 1×1100 1200 1230 2× (HB1) 1100 1200 1230 2× (HB2) 1100 1200 1230 4× 1100 1200 1230 8× 550 600 615 Word (16 Bits) 1×1100 1200 1230 2× (HB1) 900 1000 1000 2× (HB2) 1100 1200 1230 4× 550 600 615 8×275 300 307.5AD9122Rev. A | Page 8 of 60ABSOLUTE MAXIMUM RATINGSTHERMAL RESISTANCEThe exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead, LFCSP . The EPAD performs as an electrical and thermal connection to the board.Typical θJA , θJB , and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing θJA and θJB . Table 7. Thermal ResistancePackage θJA θJB θJC Unit Conditions 72-Lead LFCSP_VQ 20.7 10.9 1.1 °C/W EPAD solderedESD CAUTIONStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.AD9122Rev. A | Page 9 of 6008281-003D 11P D 11N D 10P D 10N D 9P D 9N D 8P D 8N D C I D C I D V D D 18D V S D 7P D 7N D 6P D 6N D 5P D 5N PIN CONFIGURATION AND FUNCTION DESCRIPTIONS12345678910111213141516CVDD18DACCLKP DACCLKNCVSS FRAMEP FRAMENIRQ D15P D15N NC IOVDD DVDD18D14P D14N D13P D13N 17D12P 18D12N 19202122232425262728293031323334P N S 3536545352515049484746454443424140393837RESET CS SCLK SDIO SDO DVDD18D0N D0P D1N D1P DVSS DVDD18D2N D2P D3N D3P D4N D4P727170696867666564636261605958575655C VD D 18C V D D 18REF C L K P R E F C L K N A V D D 33I O U T 1P I O U T 1N A V D D 33A V S S F S A D J R E F I O A V S S A V D D 33I O U T 2N I O U T 2P A V D D 33A V S S NCNOTES1. NC = NO CONNECT.2. EXPOSED PAD MUST BE CONNECTED TO AVSS.Figure 3. Pin ConfigurationAD9122Rev. A | Page 10 of 60AD9122050100150200250300350400450f OUT (MHz)TYPICAL PERFORMANCE CHARACTERISTICS0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c)08281-10150100150200250300350400450f OUT (MHz)Figure 4. Harmonics vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c )08281-10208281-1030–10–20–30–40–50–60–70–80–90–100050100150200250300350400450H A R M O N I C S (d B c )f OUT(MHz)08281-1040–10–20–30–40–50–60–70–80–90–10050100150200250300350400450H A R M O N I C S (d B c )f OUT (MHz)Figure 7. Second Harmonic vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC= 20 mA08281-1050–10–20–30–40–50–60–70–80–90–10050100150200250300350400450H A R M O N I C S (d B c )f OUT (MHz)Figure 5. Harmonics vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mAFigure 8. Third Harmonic vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC = 20 mA0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c )100200300400500600700f OUT (MHz)08281-106Figure 6. Harmonics vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA Figure 9. Second Harmonic vs. f OUT over f SC , 2× Interpolation,f DATA = 400 MSPS, Digital Scale = 0 dBFSAD9122–69–70–71–72–73–74–75–77H I G H E S T D I G I T A L S P U R (d B c )–78–79050100150200250300350400450f OUT (MHz)–7608281-10708281-110START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 500.0MHzSWEEP 6.017s (601 PTS)08281-111START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 800.0MHzSWEEP 9.634s (601 PTS)Figure 10. Highest Digital Spur vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA–60–65–70–75–80–85H I G H E S T D I G I T A L S P U R (d B c )050100150200250300350400450f OUT (MHz)08281-108Figure 11. Highest Digital Spur vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA–60–90–95–85–80–75–70–65H I G H E S T D I G I T A L S P U R (d B c )010*******400500600700f OUT (MHz)08281-109Figure 12. Highest Digital Spur vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mAFigure 13. 2× Interpolation, Single-Tone Spectrum, f DATA = 250 MSPS,f OUT= 101 MHzFigure 14. 4× Interpolation, Single-Tone Spectrum, f DATA = 200 MSPS,f OUT = 151 MHz08281-START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 800.0MHzSWEEP 9.634s (601 PTS)112Figure 15. 8× Interpolation, Single-Tone Spectrum, f DATA = 100 MSPS,f OUT = 131 MHzAD91220–90–80–70–60–50–40–30–20–10I M D (d B c )050100150200250300350400450f OUT (MHz)308281-11Figure 16. IMD vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–80–70–60–50–40–30–20–10–90I M D (d B c )050100150200250300350400450f OUT (MHz)408281-11Figure 17. IMD vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–80–70–60–50–40–30–20–10I M D (d B c )–100–90050100150200250300350400450f OUT(MHz)08281-115Figure 18. IMD vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–90–80–70–60–50–40–30–20–10050100150200250300350400450I M D (d B c )f OUT(MHz)08281-116Figure 19. IMD vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC = 20 mA–50–85–80–75–70–65–60–55050100150200250300350400450I M D (d B c )f OUT (MHz)08281-117Figure 20. IMD vs. f OUT over f SC , 2× Interpolation, f DATA = 400 MSPS,Digital Scale = 0 dBFS–40–90–85–80–75–70–65–60–55–50–45I M D (d B c)050100150200250300350400450f OUT (MHz)08281-118Figure 21. IMD vs. f OUT , PLL On vs. PLL Off, 4× Interpolation, f DATA = 200 MSPS,Digital Scale = 0 dBFS, f SC = 20 mAAD9122–152–156–154–158–160–162–164––166N S D (d B m /H z )50100150200250300350400450f OUT (MHz)908281-11Figure 22. 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL Off–154–158–156–160–162–164–166–168N S D (d B m /H z )050100150200250300350400450f OUT (MHz)08281-12Figure 23. 1-Tone NSD vs. f OUT over Digital Scale, f DATA = 200 MSPS,4× Interpolation, f SC = 20 mA, PLL Off–158–159–160–161–162–163–164–165N S D (d B m /H z )–166050100150200250300350400450f OUT (MHz)08281-121Figure 24. 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL On 161.0–165.5–165.0–164.5–164.0–163.5–163.0–162.5–162.0–161.5050100150200250300350400450N S D (d B m /H z )f OUT(MHz)08281-122Figure 25. 8-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL Off–161.0–166.5–165.5–166.0–165.0–164.5–164.0–163.5–163.0–162.5–162.0–161.5050100150200250300350400450N S D (d B m /H z )fOUT (MHz)08281-123Figure 26. 8-Tone NSD vs. f OUT over Digital Scale, f DATA = 200 MSPS,4× Interpolation, f SC = 20 mA, PLL Off–160–161–162–163–164–165–166N S D (d B m /H z)050100150200250300350400450f OUT (MHz)08281-124Figure 27. 8-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL OnAD9122–77–84–83–82–81–80–79–78A C L R (d B c )–050100150200250fOUT (MHz)50–55–60–65–70–75–80–85–900100200300400500A C L R (dB c )f OUT(MHz)08281-12508281-128Figure 28. 1-Carrier W-CDMA ACLR vs. f OUT over Digital Scale,Adjacent Channel, PLL Off–78–88–86–84–82–80–90A C L R (dB c )050100150200250fOUT (MHz)08281-126Figure 29. 1-Carrier W-CDMA ACLR vs. f OUT over f DAC ,Alternate Channel, PLL Off–70–90–85–80–75A C L R (dB c )–95050100150200250fOUT (MHz)08281-127Figure 30. 1-Carrier W-CDMA ACLR vs. f OUT over f DAC ,Second Alternate Channel, PLL Off Figure 31. 1-Carrier W-CDMA ACLR vs. f OUT , Adjacent Channel,PLL On vs. PLL Off–70–72–74–76–78–80–82–84–86–88–900100200300400500A C L R (dB c )f OUT(MHz)08281-129Figure 32. 1-Carrier W-CDMA ACLR vs. f OUT , Alternate Channel,PLL On vs. PLL Off–70–95–90–85–80–75A C L R (dB c)0100200300400500f OUT (MHz)08281-130Figure 33. 1-Carrier W-CDMA ACLR vs. f OUT , Second Alternate Channel,PLL On vs. PLL OffAD912208281-131START 133.06MHz #RES BW 30kHzVBW 30kHz STOP 166.94MHzSWEEP 143.6ms (601 PTS)START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 174.42MHzSWEEP 206.9ms (601 PTS)TOTAL CARRIER POWER –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22REF CARRIER POWER –16.89dBm/3.84000MHzLOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 1–16.92dBm 5.000MHz 3.840MHz –65.88–82.76–67.52–84.40RMS RESULTS FREQ LOWER UPPER OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.00MHz 3.840MHz –75.96–85.96–77.13–87.13–10.00dBm/10.00MHz 3.840MHz –85.33–95.33–85.24–95.253.840MHz15.00MHz2.888MHz–95.81–95.81–85.43–95.4308281-1322–16.89dBm 10.00MHz 3.840MHz –68.17–85.05–69.91–86.793–17.43dBm 15.00MHz 3.840MHz–70.42–87.31–71.40–88.284–17.64dBmFigure 35. 1-Carrier W-CDMA ACLR Performance, IF = ~150 MHzFigure 34. 4-Carrier W-CDMA ACLR Performance, IF = ~150 MHzAD9122 TERMINOLOGYIntegral Nonlinearity (INL)INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.Differential Nonlinearity (DNL)DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset ErrorThe deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1.Gain ErrorThe difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.Output Compliance RangeThe range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.Temperature DriftTemperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or T MAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius.Power Supply Rejection (PSR)The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling TimeThe time required for the output to reach and remain within a specified error band around its final value, measured fromthe start of the output transition.Spurious Free Dynamic Range (SFDR)The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output.Signal-to-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.Interpolation FilterIf the digital inputs to the DAC are sampled at a multiple rate of f DATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near f DATA/2. Images that typically appear around f DAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR)The ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image RejectionIn a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.。
Infoprint 250 導入と計画の手引き 第 7 章ホスト
SUBNETMASK
255.255.255.128
Type of service...............: TOS
*NORMAL
Maximum transmission unit.....: MTU
*LIND
Autostart.....................:
AUTOSTART
*YES
: xx.xxx.xxx.xxx
: xx.xxx.xxx.xxx
*
(
)
IEEE802.3
60 1500
: xxxx
48 Infoprint 250
31. AS/400
IP
MTU
1
1
IPDS TCP
CRTPSFCFG (V3R2)
WRKAFP2 (V3R1 & V3R6)
RMTLOCNAME RMTSYS
MODEL
0
Advanced function printing............:
AFP
*YES
AFP attachment........................:
AFPATTACH
*APPC
Online at IPL.........................:
ONLINE
FORMFEED
*CONT
Separator drawer......................:
SEPDRAWER
*FILE
Separator program.....................:
SEPPGM
*NONE
Library.............................:
connect系统调用中auditctl规则a2的含义
在Linux系统中，`auditctl`是用于管理审计规则的一个工具，它通过`auditctl`命令来定义审计规则。
这些规则用于跟踪和记录系统调用和文件操作。
在`auditctl`规则中，`a2`通常表示第二个参数（即系统调用的第二个参数）。
例如，如果你有一个规则像`a2 == some_value`，那么它会检查系统调用的第二个参数是否等于`some_value`。
但是，具体的含义会取决于你定义的规则。
例如，如果你有一个规则像`a2 > some_value`，那么它会检查系统调用的第二个参数是否大于`some_value`。
因此，为了得到具体的答案，你需要查看你的具体`auditctl`规则来确定`a2`的含义。
LTE典型信令过程
NAS:PDN connectivity request
Authentication and NAS security procedure
S6a: Update Location request
S11: Modify bearer response S1AP: Path Switch Response
X2AP: UE Context Release
Flush DL Buffer
Data Forwarding End Marker
Switch DL Path
S1 Handover
➢This type of handover takes place when there is no X2 connectivity between source eNB and target eNB.
S10: Forward SRNS Context Notification
UE Detach from old cell and sync to new cell
S10: Forward SRNS Context Ack
S1AP: MME Status Transfer
RRC: Connection Reconfiguration Complete
➢The release of resources at the source side is directly triggered from the target eNB.
UE
S-eNB
RRC: Measurement Control
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Process
improvement potential deviations
1. Part description 2. Process flowcharts 3. Control plan (PQP) 4. Process FMEA 5. Supplier/Sub-Contractor/Input Material 6. Initial Sample Inspection / ATP 7. Machines and facilities 8. Work instructions, training 9. Evaluations of line operations 10. Internal logistics 11. Packaging and transport 12. Machine maintenance 13. Meas. equipment/machine capability 14. Product approval for new parts 15. Capacity (Run @ Rate Study) 16. Bottlenecks 17. Troubleshooting operations Further corrective actions necessary:
Jeffrey/ Rex Jeffrey/ Rex Jeffrey/ Rex
Done
Done
Done
Seite 2 von 9
CM/PUQ
Process Description, Deviations
5. Supplier/Sub-Contractor/Input Material
PAL – Process Approval at Supplier
Deadline
Status
Revise the part description in PFMEA
Jeffrey/ Rex
2009.08.01
Done
2. Process flowcharts According to PQP OK
3. Control plan (PQP) PQP latest revision: RSE 710 Bracket (POD assy) rev B SGM VSB rev C SGM DVD rev G SGM TFT rev D Improvement required: 1. Revision content of historical changes cannot be traced to the affected process 2. DVP868S : process # 1.5 Soldering of protection plate to PCBA – controlled temperature is not stated Note: Additional points related to PQP, refer to #9 4. Process FMEA PFMEA latest revision: - Bracket (POD assy) rev B - VSB rev C - DVD rev F - TFT rev D Target RPN is < 72 Improvement required: 1. Scoring for detection is incorrect (eg. visual inspection should be 6-7 instead of 4) 2. Scoring for occurrence is reduced after corrective action which simply improve the failure detection 3. PFMEA is not reviewed for CA according to stated guideline (eg. where occurrence is > 8)
Rejected (deviations)
(immediate actions before process approval required)
Individual process approval results:
approved
Documentation
improvement potential deviations approved
To transfer and set up the facility in new plant
Lu-Dan
14.08.2009
ห้องสมุดไป่ตู้
Done
8. Work instructions, training There are 6 new operators and 4 experienced operators. Training has been ongoing since May’09. Basic skills training have been conducted, but reinforcement training still ongoing. Production manager, process engineer, line leader, OQC supervisor, repairer technician remain the experience team from Banciao. Improvement required: 1. The qualification matrix is not updated to latest status. 2. The screwing torque tolerance is incorrectly stated in WI (eg. 10 +/- 2kgf, 25 +/- 2kgf, supposed to be +/10%)
Add affected process # into the revision content Revise PQP to add the soldering temperature
Jeffrey/ Rex Jeffrey/ Rex
Done
Done
Revise the scoring for detection and ensure consistency Revise the scoring correctly for items with CA implementation Review PFMEA according to stated guideline
Actions Resp.
QGR_VA 510 Appendix 7
Edition 4 Date: 24.08.2006
3
Deadline
Status
No change at sub-supplier. Audit focused on incoming goods inspection/storage. Improvement required: 1. Temporary storage of incoming material before/after inspection not properly defined 2. Test jig for loader and LCD panel has not been set up at IQC after relocation 3. Wireless ESD wrist strap used at IQC is not proven
(for details see the following pages)
no no
yes yes
Completion date: Aug 31,2009 Visit date:
Renewed visit necessary Signatures: _______________________________
ST-Lin
07.08.2009
Done
5. Storage area of loader and LCD panel – condition is not monitored
ST-Lin
07.08.2009
Done
6. Initial Sample Inspection / ATP No Change for this Area
7. Machines and facilities There is no new machine/facility Improvement required: Random vibration machine and high-low temp chamber for reliability test (failure analysis) has not been set up at new plant
CM/PUQ
Supplier Details: Name: Site: Date: Participants:
PAL – Process Approval at Supplier
QGR_VA 510 Appendix 7
Edition 4 Date: 24.08.2006
1
Proton Electronic Industrial Co. Ltd (NanKan Plant) 8th Floor, No-66-8, Sec 2, Nankan Road. Lujhu Township, Taoyan Country, 338. Taiwan 29~31 July,2009 Name Thomas Lin Mr Lu Mr Rex Keng Mr Ra Keng Boey Weibeng Function Project engineer Production Manager QC supervisor QC Manager Purchasing quality manager
Clearly define storage area. Provide layout. To set up the jig and verify with golden sample. Verify the effectivity of strap, or change to proven grounding type Add a temperature controlled feature, or store all electronic components at PCBA supplier with proper temperature and humidity control. Install temperature and humidity control with regular monitoring