加法器电路设计 全加器

课设报告

课程名称集成电路设计方向综合课程设计实验项目加法器

实验仪器PC机、candence软件

系别______理学院_

姓名______ 杨凯__ __

实验日期 ____ __________

成绩_______________________

目录

一、概述 (3)

1.1课题背景 (4)

1.2课题意义 (4)

二、设计流程 (5)

三、课设内容 (5)

四、实验原理 (5)

4.1加法器基本原理 (5)

4.1.1 半加器基本原理 (5)

4.1.2 全加器基本原理 (6)

4.2.镜像加法器 (8)

五、上机步骤： (10)

5.1.画电路图步骤 (10)

5.2画版图步骤 (11)

六、加法器电路图： (11)

6.1原理图： (12)

6.2全加器电路图结构 (12)

6.3自己画的电路图 (13)

6.4波形验证： (13)

6.5 TRAN（瞬态）分析 (14)

6.6波形输出参数 (14)

6.728管全加器网表 (16)

6.8仿真波形 (17)

6.9编译仿真波形结果分析 (17)

七、版图设计 (18)

7.1版图 (18)

版图（L AYOUT）是集成电路设计者将设计并模拟优化后的电路转化成的一系列几何图形，包含了集成电路尺寸大小、各层拓扑定义等有关器件的所有物理信息。版图的设计有特定的规则，这些规则是集成电路制造厂家根据自己的工艺特点而制定的。不同的工艺，有不同的设计规则。版图在设计的过程中要进行定期的检查，避免错误的积累而导致难以修改。版图设计流程： (18)

7.2版图设计规则 (19)

7.3修改前版图 (20)

7.4修改后版图 (21)

八、课设心得 (22)

一、概述

集成电路是采用专门的设计技术和特殊的集成工艺技术，把构成半导体电路的晶体管、二极管、电阻、电容等基本单元器件，制作在一块半导体单晶片（例如硅或者砷化镓）或者陶瓷等绝缘基片上，并按电路要求完成元器件间的互连，再封装在一个外壳内，能完成特定的电路功能或者系统功能，所有的元器件及其间的连接状态、参数规范和特性状态、试验、使用、维护、贸易都是不可分割的统一体，这样而得的电路即是集成电路。

全加器作为基本的运算单元，在很多VLSI系统中都有很广泛的应用，是构建微处理器和DSP等运算电路的核心。随着信息技术的不断发展，VLSI的集成度不断提高，人们对运算电路速度、功耗提出了新的要求，以降低功耗提高速度为目标，许多解决方案不断被提出。如果能将速度、功耗、面积这些性能改进，势必对集成电路整体性能有所提升。

本文基于国际SMIC 0.18µm 1P6M 数字工艺、1.8V电源电压，计了一种电路结构简单，延时小，功耗低，芯片面积小的全加器结构；该全加器单元共用11只晶体管，通过在关键路径上采用三管XNOR门实现高速进位链，并且用反相器补充由于阈值电压损失造成的关键路径上逻辑电位的下降，满足了高速和低功耗的要求；用Verilog代码实现了全加器电路功能；使用cadence软件，绘制了全加器原理图、对原理图进行编译仿真，并验证了仿真结果。本文提出的全加器结构在速度、功耗、面积性能上均有很大的提升。

The integrated circuit is the use of a special design techniques and special integration technology, the transistors constituting the semiconductor circuit, diodes, resistors, capacitors, and other basic single components, fabricated in a semiconductor single wafer (e.g. silicon or gallium arsenide) or a ceramic insulatingon the base sheet, and press the circuit required to complete the interconnection between the components, and then encapsulated in a housing, to complete a specific circuit function or system function, and all of the components and their connection status, parameter specifications and characteristics of state, trial,use, maintenance, are indivisible unity of the trade, derived from the circuit so that the integrated circuit.

The full-adder as the basic computing unit, has a very wide range of applications in many VLSI systems is to build the core of the microprocessor and DSP arithmetic circuit. With the continuous development of IT, VLSI integration and speed of the arithmetic circuit, power consumption, new requirements, increase speed to reduce power consumption as the goal, many solutions are constantly being raised. If you can speed, power and area performance improvements, the bound has improved the overall performance of integrated circuits.

Based on the International SMIC 0.18μm 1P6M digital process, supply voltage 1.8V, namely, a circuit structure is simple, small delay, low power consumption, small chip area of the full adder structure; the unit share 11 transistors, three XNOR gate in the critical path to achieve high-speed carry chain, and to supplement the decline in the potential of logic on the critical path due to the loss of threshold voltage caused by the inverter to meet the requirements of high-speed and low power consumption. Verilog code to achieve the functionality of the full adder circuit; cadence software, draw a schematic diagram of the full adder, compiled simulation, schematic and verify the simulation results. The full adder structure proposed in this paper have greatly improved in speed, power and area performance.