计算机体系结构试题及答案(Computer architecture questions and answers)

计算机体系结构试题及答案（Computer architecture questions andanswers）Questions and answers of computer architecture1, benefiting from the development of high performance computer: (1) the development of circuit technology; (2) the development of computer architecture technology.2, structure: computer systems can be classified by function of language as a multilevel structure, each layer in different language features. Sixth: the application of virtual machine language - > fifth: high-level language virtual machine assembly language - > Fourth: - > Third: virtual machine operating system virtual machine - level second: machine language (traditional machine level) - > Level 1: micro machine level program.3, computer architecture: see computer programmer attribute, namely the general structure and functional properties.4, transparency: in computer technology, the things or properties already exists, the concept from a point of view and have called transparency.5, the proposed architecture Amdahl attribute refers to the computer machine language level programmers see.The essence of 3 6, a classic computer architecture concept is to determine the computer system hardware and software interface, which is the instruction set design, above theinterface by software function realization, interface by hardware and firmware functions to achieve.7, computer organization is the logic of the computer system; computer is a physical computer system to achieve.The difference and connection between the 8, computer architecture, computer organization, computer?Answer: a system structure can have a variety of components, a component can have a variety of physical implementation, including system structure research on organization and implementation.9, a series of machine: refers to a system of the same structure but with different organization and implementation of a series of different types of machines.10, software compatibility: the same software can be run without change on the machine system of the same structure, and the results they get the same, the only difference is the different running time.11, compatible machine: different manufacturers, has the same computer architectures.12, backward compatibility is the basic characteristics of software compatibility, is the fundamental characteristics of series machine.13, in the field of computer market can be divided into threemajor areas: servers, desktop systems, embedded computing.14, Moore: integrated circuit density approximately doubled every two years.Technology based analysis of 15 quantitative performance evaluation: (1) (a) response time: from the beginning to the end of the time between events; all the time spent on the computer to complete a task. (b): the complete flow in unit time and workload. (c) x, y assumed two computers; X faster than y means: for a given task, the response time of X is less than y. The performance of X is several times the Y refers to the response time of X / y = n response time, response time and performance is inversely proportional to.16, the probability of event priority principle: (basic idea) for the probability of events (the most common event), giving priority to use it right and resource rights, to obtain the global optimal results.17, Amdahl Law: accelerate the execution speed of a component system performance obtained speedup, the importance is limited by the components in the system of. System acceleration ratio = total execution time (improved) / total execution time (improved) =......18, Amdahl law corollary: if only for a part of the computer in the performance improvement is more improved, the effect of the system. If only a part of the whole task is optimized, so much the acceleration ratio is not greater than 1 / (1- improvement ratio).19, the performance of CPU: Cpu time = total number of clock cycles / clock frequency Cpi = total number of clock cycles (IC / CPI: the number of clock cycles per instruction; the average IC implementation process: the number of instructions.)The performance of Cpu formula: total CPU time = CPI * IC / CPI clock frequency which reflects the computer architecture and computer technology, computer instruction set; Ic reflects the structure and technology of computer programming instruction set; clock frequency: reflect the implementation of computer technology, production technology and computer organization.20, parallelism refers to at the same time or two or more than two kinds of properties of the same or different work in the same time interval.The second chapter1, according to the CPU internal storage unit type of instruction set architecture for classification, can be divided into the stack based instruction set architecture, instruction set architecture and accumulator type general register type instruction set architecture.2, general register type instruction set machine is further subdivided into 3 types:Register to register type (R-R), register memory type (R-M), a memory register.3, addressing: (1) register addressing: example: ADD R4 R3, meaning Regs[R4]<-Regs[R4]+Regs[R3](2) immediate values: example: ADD R4, addressing 3 meanings: Regs[R4]<-Regs[R4]+3(3): offset cases: ADD R4, 100 (R1) meaning:Regs[R4]+Mem[100+Regs[R1]](4) register indirect addressing: example: ADD R4 (R1) meaning: Regs[R4]<-Regs[R4]+Mem[Regs[R1]](5) index addressing: example: ADD R3 (R1+R2) meaning:Regs[R3]<-Regs[R3]+Mem[Regs[R1]+Regs[R2]](6) direct addressing or absolute addressing: for example: ADD R1, (1001): Regs[R1]<-Regs[R1]+Mem[1001] meaning(7) memory indirect addressing: example: ADD R1, a (R3) meaning: Regs[R1]<-Regs[R1]+Mem[Mem[Regs[R3]]](8) the increment addressing: example: ADD R1 (R2) + meaning: Regs[R1]<-Regs[R1]+Mem[Regs(9) decrement addressing(10) zoom addressingThe function of structure design of the instruction set, 4:The instruction set classification structure in operationThe type of operation example(1) arithmetic and logical operations on integer arithmetic and logic operations: addition, subtraction, and, or etc.(2) data transmission LOAD/STORE(3) control branch, jump, procedure call and return, trap(4) operating system calls, virtual memory management.(5) floating point addition and subtraction operation(6) is converted to decimal decimal decimal decimal add, multiply, to characters(7) string string comparison, mobile(8) the pixel operation, compression operation5, complex instruction machine (CISC): refers to strengthen the instruction function, realize the function of software to hardware design, computer system to realize the instruction set architecture based on.The shortcomings of the CISC instruction set:(1) in the command system, the frequency of use of all kinds of orders is different.(2) the CISC instruction set architecture complexity brings complexity of computer architecture, which not only increases the development time and cost, but also easy to cause the design error.(3) the CISC instruction set architecture complexity brings great burden to the VLSI design, is not conducive to the monolithic integration.(4) in the CISC instruction set architecture, many complex instructions require very complex operation, so slow.(5) in the CISC instruction set architecture, because of the directive function is not balanced, not conducive to the use of computer architecture technology (such as advanced water technology) to improve the performance of the system.In 1980s 6, reduced instruction set computer developed: its purpose is to reduce the instruction set of the complexity of the structure as far as possible, in order to simplify the realization of the goal of improving performance, but also in today's instruction set is a main trend of the structure and function of design.Follow the design principles:(1) choose to use the highest frequency of instruction, and added some of the most useful instructions.(2) the function of each instruction is as simple as possible, and completed in one machine cycle.(3) all have the same length as the instruction.(4) only the LOAD and STORE operating instructions to access memory and other instruction operation is performed in the register between.(5) in a simple and effective way to support advanced language.7 operand types: integer, decimal, floating point (point), characters, strings, vectors, stack etc..There are two ways to express 8, operand types: (1) specified by the operation code encoding. (2) data can be a mark by the hardware to explain the type of the operand specified by these tags, so as to choose the appropriate operation.9, the operand type size: byte (8), the word (16b), the word (32b), double word (64b)The third chapter1, pipeline technology: refers to a repeat of the timing process is decomposed into several sub processes, and each process can be effective in its special function with other processes executing at the same time.2, pipeline classification: (1) according to the function of the number of points: single function pipeline, multifunctional pipeline;(2) according to the connection between the same time segments to static and dynamic pipeline pipeline(3) according to the line level: component level pipeline (operation line), pipelined processor (instruction pipelining), inter processor pipeline (macropipeline)(4) according to whether there is water between each section of a feedback loop: linear and nonlinear pipeline pipeline(5) according to the data representation: scalar processor, vector processor3, the first processor controller structure comprises three independent controllers and four buffer stack. The three controller: memory controller, controller, controller operation instruction. Four: the first instruction buffer buffer stack stack, linear buffer stack, stack current readings, then write the number of stack.4, the throughput is the number: the number of tasks or output per unit time of the pipeline. TP = n / TkThe actual throughput rate is less than the maximum throughput of Tk = (k+n-1) t5, speedup: refers to the speed of the line and the function of non line speed ratio (s);Efficiency: refers to the utilization rate of pipeline equipment (E).6, if the line segment is equal to the time: throughput rate: TP=n/ (k+n-1) t TPmax=1/ tIf each execution time is not equal, complete several tasks: TP=n (sigma / Ti + (n-1) max (delta T1, Delta t2... Delta TK)7, the speedup and efficiency of the relationship: E = s/m or S = mE8, efficiency and throughput of the relationship: E = TP t0 TP = E/ or T11, efficiency: K E = n a task flow segment occupied area of the total space / time zones = T0 / K Tk?E = n/ (k+n-1) S = k? N / TP / (k+n-1) = n (k+n-1) t12, single function pipeline stack: refers to only perform one fixed function pipeline stack.13, multi functional water: water each stack stack to achieve different functions through different connections.14, nonlinear pipeline scheduling task: to find a minimum cycle, according to a new task to the input line cycle, each function section line are not in conflict, and the pipeline throughput and maximum efficiency.15, nonlinear pipeline: between some water section of feedback loop or feed-forward loop.16, start distance: continuous input even intervals between tasks.17, pipeline conflict: several tasks competing for the same water section.18, forbidden vector: distance between sets of appointments each row in the table of any of the two "x".19, conflict vector: C = (Cm? Cm-1?... C1? C2? M) which allowed maximum value in the vector20, the relevant data: in the process of execution of the instructions, if the instructions used, the number of variables, such as the operation is in front of the results of the implementation of the relevant instructions, called data.21, control: caused by conditional branch instructions, rotor program instructions, the relevant interrupt.22, three kinds of data: limit write, read after write, write.The fourth chapter1, ILP: when there are correlation between instructions in the pipeline, they can overlap parallel execution, the potential parallelism is called instruction level parallelism exists in this sequence of instructions.2, in a variety of technical development loop level parallelismin the most basic techniques are: instruction scheduling, loop unrolling technique and technical change.The fifth chapter (storage system)1, the definition method of memory storage system: two or more than two speed, capacity and price vary with hardware, software or hardware and software combination connected into a storage system. And the memory system is transparent to application programmers, and to the application programmer, it is a memory, the memory of the memory close to the speed of the fastest, the storage capacity and the storage capacity of the largest equal unit capacity price close to the lowest memory.2, the storage system is divided into two categories: (1): Cache storage system composed of Cache and main memory, the purpose is to improve the speed of memory. (2) virtual storage system consists of a main memory and hard disk, to expand memory capacity.3, the price of storage system: C = (C1S1+C2S2) / (S1+S2)4, the storage system speed: Representation: access cycle, access cycle, storage period, access time, etc..5, the hit rate of definition: probability in M1 memory access toU = N1 / (N1+N2) N1 of M1 memory access times, N2 is on the M2 memory access times.6, the efficiency of access:T1 1E = T1/T = = = f (U, T2/T1)U? T1+ (1-u) T2 u+ (1-u) T2/T1?7, using prefetching to improve the hit rate (method).Do not hit, a block of data in a plurality of adjacent M2 memory units taken out into the M1 memory.U (u+n-1 / N) = 'U' is the pre shooting technique after u is the original hit rate;The product of n as the data block size and the number of data reuse.8, accelerate the internal address transformation method: (1) the table of contents: with a small capacity high speed memory storing the page table; (2): fast and slow speed of table table table to form a two level storage system; (3): the hash function associative access into the access address access.9, the page replacement algorithm: (1) random algorithm (RAND);(2) FIFO algorithm (FIFO); (3) least recently used (LFV); (4) LRU (LRV); (5) the optimal replacement algorithm (OPT).10, "bump" phenomenon: a page is just out of the main memory, but also to be transferred.11, the stack type replacement algorithm: for an arbitrary program page address stream for the two main memory page number distribution, a memory allocated m page and n a memory page, and M = n. If at any time t, main memory page number set Bt satisfy the relation: Bt (m) = Bt (n) is a type of this kind of algorithm stack replacement algorithm.12, Cache address mapping method: (1) fully associative mapping;(2) direct mapping; (3) set associative mapping;(4) choose a set associative mapping mapping section (5).13, Cache memory replacement algorithm: (1) rotation method (2) LRV algorithm (3) comparing (4) stack method.The consistency of Cache 14, single processor:Direct method: [including write write through method, CPU writes data to Cache, while the page is written to main memory.And write back: "conflict modify method, CPU data into Cache, do not write memory, only when the replacement when the modified Cache block write back to main memory.Comparing the advantages and disadvantages of the two:(1) reliability: write direct method is better than the write back.(2) the amount of memory and communication, write back and writeless than direct method.(3) the complexity of control, direct write back write is simple.(4) the hardware implementation cost is written back to the write through law.The consistency of 15, multiprocessor: (1) the directory protocol (2) and listen to the agreementThe sixth chapter (input / output system)1, measure the performance index of I/O system mainly has the response time and reliability.Data transmission, 2 disk external transfer rate and internal transfer rate.3, the external transmission rate (burst data transmission rate): computer read from the cache data into the hard disk by disk interface, to the corresponding speed controller.4, internal transfer rate (sustained transfer rate): hard disk data from disk read, to buffer memory on the hard disk speed.5, reliable performance parameters reflecting storage peripherals are reliability, availability and credibility.6, reliability measure: mtbf.7, availability metrics: mean time between failure.8, bus: bus communication link between each subsystem shared, the two has the advantages of low cost and diversity.The main disadvantage of the 9 bus: it has exclusive use, causing the bottleneck equipment information exchange, thus limiting the total throughput of I/O system.10, split transaction bus: there is a plurality of devices, available through the packaging technology to improve the bus bandwidth, so that each I/O operation will not have to occupy the bus in the transmission process, the basic idea of the bus transaction is divided into two parts of requests and responses, such as the bus idle time interval to request and response in the a bus transaction between other bus transaction is used. (also known as water bus, bus, bus suspension packet switching)11, the control of external equipment input / output mode is divided into: direct transfer procedures, query, interrupt, DMA, channel mode.Addressing mode 12, I/O equipment: (1) memory mapped I/O or unified addressing (2) I/O addressing individual equipment13, channel: to perform limited I/O instruction, and can be a plurality of peripheral devices share a small dedicated DMA processor.14, channel function: (1) received from the CPU I/O command, and according to the peripheral equipment and the channelinstruction requires the selection of the specified connection.(2) CPU channel organization channel program, remove channel instructions from the main memory, decode the channel command, and issued a command to the device controller is selected according to the needs of. (3) as the main memory and peripheral assembly and disassembly information, data transmission and memory I/O control equipment and provide a transmission path, indicating the data memory address and send byte number. (4) specify the transfer at the end of the operation to be carried out. (5) check the peripheral equipment working state, normal or fault.(6) complete the format conversion required in data transmission process.15, types of channels: (1) channel multiplexer (2) selects the channel (3) multi channel array.The working process, 16 channels: (1) using SVCI into management program in the user program by CPU, through the management procedures to organize a channel program, and start the channel. (2) channel processor implementation of CPU for which the organization's channel program, complete the assigned work data I/O. Channel processor execute channel program was performed with the CPU user program in parallel.(3) channel program after the end to the CPU interrupt request, CPU responding to an interrupt request after second times to enter the operating system, call management program of the I/O interrupt request processing.The seventh chapter (multiprocessor)1, Cache coherence protocol: (1) the directory protocol and listen to the agreement; (2) laterally divided into: write Invalid Protocol and write update protocol; (3) longitudinally divided into single treatment protocol and single data stream protocol.2, the classification of parallel computer architecture: single instruction single data stream (SISD), single instruction multiple data stream (SIMD) and multiple instruction single data stream (MISD) and multiple instruction multiple data stream (MIMD).3, the directory protocol is divided into three categories: full map directory, the directory, the directory chain co..4, the chain Directory: by maintaining a directory pointer chain to track shared data copy.Thought: when P1 read x memory, X sent to cachel, a chain and write cachel end pointer CT also holds a pointer to a cachel in memory, P2 to read x, memory holds a pointer to a cachel2, a processor need to write x, he must be along the whole a directory even send a data information in the received signal to answer the invincible, all processors, memory to allow the processor to write rightThe cachel data block in need of replacement, to delete the cache directory from the chain, there are solutions;(1) the cachei+1 pointer to cachei+1, store the new data blockin cachel (2) cachel and cachel in the chain seat all subsequent units in X is invalid (3) using two-way chain, when replacing the no longer need to traverse the entire chain, but the pointer has doubled, agreement more perfectAdvantages: B does not limit the sharing of copy number data blocks while maintaining scalability, pointer length has the number of processors on the relation between growth, the number of processors and the number of pointers for each block of data is independent of the cacheDisadvantages: complex chain directory in Chengdu more than two directory5 definition: Internet; is symmetric systems or distributed system nodes may like processor, memory module or other devices, they exchange information through the Internet, in the topology, the Internet provides a set of interconnected or image as input and output between two groups of nodes6 (1) the number of nodes is called the network scale(2) the number of edges and nodes interconnected to the maximum value of the node is called the network diameter(3) any network nodes even the maximum length of the shortest path is called the network diameter(4) equal width (b) in the network into a two phase digestion method, the minimum number of edges cut along the road is called channel bisection width(5): refers to the designation of the routing path selection in network communication7 function: if the Internet Interconnection Network N a end and N end respectively with the integer 0, 1,...... .N algebra, is said to work with the interconnection function number and number of symmetric relations such asSaid method 8 interconnection network(1) the interconnection function representation (2) graphical representation (3) input and output the corresponding representation9 common data routing (or interconnection function) function:(1) the replacement cycle (2) (3) (4) uniform shuffle hypercube routing function (5) broadcasting and communication。