Maximum Likelihood Decoding of M-ary Orthogonal Modulated Signals for Multi-Carrier Spread-
低精度ADC 下的大规模MIMO-OFDM 信道估计算法

低精度ADC 下的大规模MIMO-OFDM 信道估计算法戈立军,朱德宝(天津工业大学电子与信息工程学院,天津300387)Channel estimation algorithm for massive MIMO-OFDM systems withlow-precision ADCsGE Li-jun ,ZHU De-bao(School of Electronics and Information Engineering ,Tiangong University ,Tianjin 300387,China )Abstract :A channel estimation algorithm based on quantized compressive sensing is proposed for massive multiple inputmultiple output-orthogonal frequency division multiplexing渊MIMO-OFDM冤systems with low-precision analog-to-digital converters (ADCs )袁which is the block sparsity multi-bit iterative hard thresholding 渊B-MIHT冤algo鄄rithm.The B-MIHT algorithm exploits the block sparsity characteristics of massive MIMO-OFDM system chan鄄nels袁and combines with the multi-bit iterative hard thresholding algorithm by constructing the equivalent blocksparse channel matrices.The algorithm estimates the channel information of massive MIMO-OFDM systems withlow-precision ADCs based on training sequences袁the simulation is performed on MATLAB platform.The results show that B-MIHT algorithm can accurately recover the channel information of massive MIMO-OFDM systems with low -precision ADCs and has good channel estimation performance under the condition that the system quantization accuracy is 5bits.When the signal to noise ratio is 30dB袁the bit error rate渊BER冤of B-MIHT algo鄄rithm is 5.45伊10-3and the normalized mean square error渊NMSE冤is 1.73伊10-3.The channel estimation perfor鄄mance loss of B-MIHT algorithm is relatively small when the number of channel paths increases.Key words :massive multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM );low-precision analog-to-digital converter (ADC );channel estimation ;quantized compressive sensing ;blocksparsity characteristic摘要:针对低精度模数转换器(ADC )下的大规模多输入多输出正交频分复用(MIMO-OFDM )系统,提出一种基于量化压缩感知的信道估计算法———块稀疏多比特迭代硬阈值(B-MIHT )算法。
数字电视标准MPEG2、DVB和ATSC的常用缩写说明书

BROADCASTING DIVISION APPLICATION NOTEThe most common abbreviations used in the standards for digital TV: MPEG2, DVB and ATSC Products:MPEG2 DTV RECORDER GENERATOR DVRGMPEG2 MEASUREMENT GENERATOR DVGMPEG2 REAL TIME MONITOR DVRMMPEG2 MEASUREMENT DECODER DVMDQAM TEST RECEIVER/DEMODULATOR EFATV TEST TRANSMITTER SFQ7BM27_0E21 MPEG2 AbbreviationsAdaptation FieldAncillary program data(especially PCR) which areuncoded and are transmittedat least every 100ms acc. toMPEG2 or 40 ms acc. to DVBspecificationsBAT Bouquet Association TableTable describing a bouquet ofprograms offered by abroadcasterBlock 8x8 pixel block, MPEG2codedCA Conditional AccessInformation of whether theprogram is scrambledCAT Conditional Access Table(PID =1):Reference to scrambledprogramsCIF Common IntermediateFormatPicture formatCRC Cyclic Redundancy CheckDCT Discrete CosineTransformDCT -1 / IDCT Inverse Discrete CosineTransformDFD Displaced Frame DifferenceDifferential picture if there ismotionDPCM Differential Pulse CodeModulationDTS Decoding Time StampStamp for decoding time, onlytransmitted if not identical withPTS; reference to PIDEIT Event Information TableTV guideES Elementary StreamCompressed data stream forvideo, audio or data.Preliminary stage toPESGOP Group of PicturesI, P, and B picturesIntra-coded pictures (I),predicted pictures (P) and bi-directional prediction pictures (B)IRD Integrated Receiver DecoderReceiver with (MPEG)decoderMPEG Motion Picture ExpertsGroupsometimes called Moving PictureExperts GroupMUSICAM Masking Pattern AdaptedUniversal Subband Integra-ted Coding and MultiplexingCompression method foraudio codingThe most common abbreviations used in thestandards for digital TV: MPEG2, DVB and ATSCThe introduction of the transmission of compressed TV signals to MPEG2 and DVB for cable, satellite and terrestrial (COFDM) lead to the creation of many abbreviations that have to be explained to the “uninitiated”. In the previous three lines, three abbreviations whose meanings are not obvious have already been mentioned. A table explaining what these abbreviations mean is therefore essential.3NIT Network Information Table Information about orbit, transponder etc.PAT Program Association Table (PID =0): List of all the programs contained in TS Multiplex with reference to PID of PMTPay Load Useful data in TSPCM Pulse Code ModulationPCR Program Clock Reference Reference in TS for the 27-MHz clock recovery. Transmitted at least every 0.1 secPES Packetized Elementary Stream Video and audio data packets and ancillary data of definable lengthPES Header Ancillary data for an elementary stream PID Packet Identification Identification of programs in the transport streamPMT Program Map Table: Reference to packets with PCR Name of programs, copyright, reference of the data streams with PIDs etc. belonging to the relevant programPrediction Prediction of a picture (P or B) with indication of a motion vectorProfile Subdivision of video coding into different resolutions PS Program Stream Multiplex of several audio and video PES using the same clock. PSI Program Specific Informa- tionData transmitted in TS for the demultiplexer in the receiver (eg PAT, PMT, CAT)PTS Presentation Time Stamp Time stamp for vision and sound, transmitted at least every 0.7 sec. Integrated into PES Q Quantization Q -1 Inverse quantization QS Quantization scalingRLC Run Length CodingCoding of data with different number of bits. Frequentlyreoccurring data has the smallest number of bits, data seldom reoccurring have the highest number of bits.RST Running Status TableAccurate and fast adaptation to a new program run if time changes occur in the scheduleSection A table is subdivided into several sections. If there is a change, only the section affected is transmitted SI Service InformationAll the data required by the receiver to demultiplex and decode the various programs in the TS SIF Source Input FormatSCR System Clock Reference Reference in ES for synchro- nizing the system demultiplex clock in the receiver,transmitted at least every 0.7 sec. Integrated into PESSDT Service Description Table Description of programs offeredSTCSystem Time Clock427-MHz clock, regenerated from PCR for a jitter-free readout of MPEG dataSYNC(_byte) Synchronization byte in TS header value 0x47 TS Transport StreamTS Header The first 4 bytes of each TS packet contain the data (PID) required for the demultiplexer in addition to the sync byte (0x47). These bytes are never scrambled.TDT Time and Date table UTC time and dateTOT Time Offset Table UTC time and date with indication of local time offsetUTC Universal Time, Co- ordinated Greenwich meantimeVBR Variable Bit RateVLC Variable Length Coding Coding of data with variable number of bits (also see RLC )ZigZag Scan Zigzag scan of quantized DCT coeffi- cient matrix. This gives an efficient run length coding (RLC )52 DVB and ATSC AbbreviationsADSL Asymmetric digital subscrib- er line A COFDM-coded digital data stream with a rate up to 8 Mbit/s (down stream) and 1 Mbit/s (up stream) is transmitted via telephone lines, mainly for video on demand.ATSC Advanced Television Systems Committee american standardization group for digital terrestrial transmissionCNR Carrier to Noise Ratio Indicates how far the noise level is down on carrier levelCOFDM Coded Orthogonal Frequen- cy Domain Multiplex Up to 6817 single carriers 1.116 kHz apart are QAM- modulated with up to 64 states. "Coded" means that the data to be modulated has error control. Orthogonality means that the spectra of the individual carriers do (almost) not influence each other as a spectral maximum always coincides with a spectrum zero of the adjacent carriers. A single-frequency network is used for the actual transmission.Constellation Diagram Way of representing the I and Q components for QAM or QPSK modulation. The position of the points in the constellation diagram provides information about distortions in the QAM or QPSK modulator as well as about distortions after the transmission of digitally coded signals.DVB Digital Video Broadcasting Broadcasting TV signals to a digital standardDVB-C Digital Video Broadcasting- Cable Broadcasting TV signals to a digital standard by cable DVB-S Digital Video Broadcasting- Satellite Broadcasting TV signals to digital standard via satelliteDVB-T Digital Video Broadcasting- Terrestrial Terrestrial broadcasting of TV signals to digital standardConvolutional Coding The data stream to be trans- mitted via satellite and terrestrial (DVB-S, DVB-T) is loaded bit by bit into shift registers. The data which is split and delayed as it is shifted through different registers is combined in several paths. This means that double the data rate (2 paths) is usually obtained. Puncturing follows to reduce the data rate: the time sequence of the bits is predefined by this coding and is represented by the trellis diagram .FEC Forward Error Correction Error control bits added to use- ful data in the QAM/QPSK modulator for DVB-C, -S and DVB-T.Single-frequency network Transmitter network in which all the transmitters use the same frequency. The coverage areas overlap. Influece of echoes are minimized by g uard intervals . The transmitters are separated by up to 60 km. The special6feature of these networks is efficient frequency utilizationGuard interval additional safety margin between two transmitted sym- bols in the COFDM standard. The guard interval ensures that echoes occurring in the single-frequency network are eliminated until the received symbol is processed.Interleaver The RS -protected transport packets are reshuffled byte by byte by the 12-channel interleaver. (RS FEC Reed Solomon FEC) Due to this reshuffle what were neighbouring bytes are now separated by a maximum of 2244 bytes from other TS packets. The purpose of this is the burst error control for defective data blocksMapping Conversion of bytes (8 bits) to 2n-bit wide symbols. n is thus the bit width for the I and Q quantization; eg at 64 QAM the symbol width is 2n = 6 bit, n = 3, ie I and Q are subdivided into23= 8 amplitude values eachPuncturing Puncturing (DVB-S and -T) follows to reduce the in- creased data rate after convolutional coding: Various registers are not used. The additional redundancy is used for error control. The two data streams after puncturing are directly applied as I and Q input signals to the QAM or QPSK modulator after filtering to fulfil the first Nyquist criterion.QAM Quadrature Amplitude Modulation Type of modulation for digital signals (DVB-C and -T). Two signal components I and Q are each quantized and modulated onto two orthogonal carriers as appropriate for the QAM level(4, 16, 32, 64, 128, 256). The constellation diagram is obtained by plotting the signal components with I and Q as the coordinate axes. Therefore, 2, 4, 5, 6, 7 or 8 bits of a data stream are transmitted with one symbol, depending on the QAM level (4, 16, 32, 64, 128, 256). This type of modulation is used in cable systems and for coding the COFDM single carriersQEF Quasi Error Free Less than one uncorrected error per hour at the input of the MPEG2 decoder. (BER ≤10-11)QPSK Quadrature Phase Shift Keying Type of modulation for digital signals (DVB-S and -T). The digital, serial signal components I and Q directly control phase shift keying. The constellation diagram with its four discrete states is obtained by representing the signal components using the I and Q signals as coordinate axes. Due to the high nonlinear distortion in the satellite channel, this type of modulation is used for satellite transmission: The 4 discrete states all have the same amplitude that is why non- linear amplitude distortions have no effect.RS Protection Code RS(204,188,8) (RS = Reed Solomon) 16-byte long error control code added to every transport packet consisting of 187 (scrambled) bytes +1 syncbyte with the following result: The packet has a length of 204 bytes and the decoder can correct up to T = 8 errored bytes. This code ensures a7residual Bit Error ratio BER of approx. 1x10-11 at an input error ratio of 2x10-4.SFN Single Frequency NetworkTrellis Diagram The time sequence of the bits (DVB-S and -T) is predefined by convolutional coding and, like the state diagram of a finite automaton, is represented as a trellis diagram.Viterbi Decoding Viterbi decoding makes use of the predefined time sequence of the bits through convolutional coding (DVB-S and -T). Thanks to a series of logic decisions, the most probably correct way is searched for through the trellis diagram and incorrectly transmitted bits are corrected.n VSB Modulation Transmission of n discrete amplitude values using the vestigial sideband method on normal terrestrial (ATSC) channels and conventional IF modulators. The most common variant is 8-VSB transmission already tested in the US. With 8 VSB, 3 bits (23 = 8) of the data stream are transmitted per amplitude value3. ATSC Tables and ProtocolsATSC Advanced Television Systems Committee american standardization group for digital terrestrial transmissionCAT Conditional Access Table (PID =1): Reference to scrambled programs Table ID 0x01CVCT Cable Virtual Channel Table Table ID 0xC9EIT Event Information Table Table ID 0xCB ETT Extended Text Table Table ID 0xCCETM Extended Text MessageMGT Master Giude Table Table ID 0xC7PAT Program Association Table (PID =0):List of all the programs contained in TS Multiplexwith reference to PID of PMTTable ID 0x00PITProgram Identification TablePMT TS Program Map Table: Reference to packets with PCR Name of programs, copyright, reference of the data streams with PIDs etc. belonging to the relevant program Table ID 0x02PSIP Program and SystemInformation ProtocolPTC Physical Transmission Channel RRT Rating Region Table Table ID 0xCA SI Sytem Information STT System Time TableTable ID 0xCDTVCT Terrestrial Virtual Channel Table , Table ID 0xC88 VSB Vestigial Side BandModulation8digital terrestrial broadcastmode16 VSB Vestigial Side BandModulationHigh Data Rate modeespecially for Cable Systems94 The Digital TV SystemThe transmission of digitized vision and sound together with different ancillary data is subdivided into precisely defined areas.The first area is the MPEG2 level In the coder this comprises • video compression, • sound compression,• processing of all ancillary data (including SI (see page 3), teletext etc.), • PES generation , • TS generation , • TS multiplexing ,or the inverse functions in the decoder.The output of the MPEG2 block is the output of the TS multiplexer.The second area consists of transmission levels DVB - C, DVB - S, DVB - TAt the transmitter end this comprises• energy dispersal (scrambler) and the sync inverter in the 8-sync sequence, • Reed Solomon error-control coder, • interleaver,• convolutional coding and puncturing (DVB - S),• symbol mapping (DVB - C),• modulation in QAM (DVB - C, DVB - T in COFDM), QPSK (DVB - S) or 8 VSB (DVB - T),or the inverse functions in the receiver.The input of the transmission block is the output of the TS multiplexer.5 Additional InformationOur Application Notes are regularly revised and updated. Check for any changes at .Please send any comments or suggestionsabout this Application Note to。
Vishay 接收器模块数据手册说明书

IR Receiver Modules for Remote Control SystemsDESIGN SUPPORT TOOLS MECHANICAL DATAPinning1 = GND,2 = N.C.,3 = V S,4 = OUT ORDERING CODETaping:TSOP6...TT - top view taped TSOP6...TR - side view taped FEATURES•Improved immunity against HF and RF noise•Low supply current•Photo detector and preamplifier in one package•Internal filter for PCM frequency•Improved shielding against EMI•Supply voltage: 2.5 V to 5.5 V•Improved immunity against ambient light•Insensitive to supply voltage ripple and noise•Taping available for top view and side view assembly•Material categorization: for definitions of compliance please see /doc?99912 DESCRIPTIONThe TSOP61.., TSOP63.. series are miniaturized SMD IR receivers for infrared remote control systems. A PIN diode and a preamplifier are assembled on a lead frame, the epoxy package contains an IR filter. The demodulated output signal can be directly connected to a microprocessor for decoding.The TSOP63.. series devices are optimized to suppress almost all spurious pulses from Wi-Fi and CFL sources. They may suppress some data signals if continuously transmitted.The TSOP61.. series devices are provided primarily for compatibility with old AGC1 designs. New designs should prefer the TSOP63.. series containing the newer AGC3. The TSOP65.. series are useful to suppress even extreme levels of optical noise, but may also suppress some data signals. Please check compatibility with your codes.These components have not been qualified according to automotive specifications.PARTS TABLEAGC LEGACY, FOR SHORT BURSTREMOTE CONTROLS (AGC1)NOISY ENVIRONMENTSAND SHORT BURSTS (AGC3)VERY NOISY ENVIRONMENTSAND SHORT BURSTS (AGC5)Carrier frequency 30 kHz TSOP6130TSOP6330TSOP6530 33 kHz TSOP6133TSOP6333TSOP6533 36 kHz TSOP6136TSOP6336 (1)TSOP6536 (1) 38 kHz TSOP6138TSOP6338 (2)(3)(4)(5)TSOP6538 (2)(3)(4) 40 kHz TSOP6140TSOP6340TSOP6540 56 kHz TSOP6156TSOP6356TSOP6556Package PanheadPinning 1 = GND, 2 = N.C., 3 = V S, 4 = OUTDimensions (mm)7.5 W x 5.3 H x 4.0 DMounting SMDApplication Remote controlBest choice for(1) MCIR (2) Mitsubishi (3) RECS-80 Code (4) r-map (5) XMP-1, XMP-2BLOCK DIAGRAMAPPLICATION CIRCUITNote•Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliabilityABSOLUTE MAXIMUM RATINGSPARAMETER TEST CONDITIONSYMBOLVALUE UNIT Supply voltage V S -0.3 to +6V Supply current I S 5mA Output voltage V O -0.3 to (V S + 0.3)V Output current I O 5mA Junction temperature T j 100°C Storage temperature range T stg -25 to +85°C Operating temperature range T amb -25 to +85°C Power consumptionT amb ≤ 85 °C P tot10mWELECTRICAL AND OPTICAL CHARACTERISTICS (T amb = 25 °C, unless otherwise specified)PARAMETER TEST CONDITIONSYMBOLMIN.TYP.MAX.UNIT Supply voltage V S 2.5- 5.5V Supply current V S = 5 V, E v = 0I SD 0.550.70.9mA E v = 40 klx, sunlightI SH -0.8-mA Transmission distance E v = 0, IR diode TSAL6200, I F = 250 mA, test signal see Fig. 1d -40-m Output voltage low I OSL = 0.5 mA, E e = 0.7 mW/m 2, test signal see Fig. 1V OSL --100mV Minimum irradiance Pulse width tolerance:t pi - 5/f o < t po < t pi + 6/f o, test signal see Fig. 1E e min.-0.20.4mW/m 2Maximum irradiance t pi - 5/f o < t po < t pi + 6/f o , test signal see Fig. 1E e max.50--W/m 2DirectivityAngle of half transmission distanceϕ1/2-± 50-degTYPICAL CHARACTERISTICS (T amb = 25 °C, unless otherwise specified)Fig. 1 - Output Active LowFig. 2 - Pulse Length and Sensitivity in Dark AmbientFig. 3 - Output Function Fig. 4 - Output Pulse DiagramFig. 5 - Frequency Dependence of ResponsivityFig. 6 - Sensitivity in Bright AmbientE eV O V OH V OLFig. 7 - Sensitivity vs. Supply Voltage Disturbances Fig. 8 - Max. Envelope Duty Cycle vs. Burst Length Fig. 9 - Sensitivity vs. Ambient Temperature Fig. 10 - Relative Spectral Sensitivity vs. Wavelength Fig. 11 - Horizontal DirectivityFig. 12 - Sensitivity vs. Supply VoltageSUITABLE DATA FORMATThis series is designed to suppress spurious output pulses due to noise or disturbance signals. The devices can distinguish data signals from noise due to differences in frequency, burst length, and envelope duty cycle. The data signal should be close to the device’s band-pass center frequency (e.g. 38 kHz) and fulfill the conditions in the table below.When a data signal is applied to the product in the presence of a disturbance, the sensitivity of the receiver is automatically reduced by the AGC to insure that no spurious pulses are present at the receiver’s output.Some examples which are suppressed are:•DC light (e.g. from tungsten bulbs sunlight)•Continuous signals at any frequency•Strongly or weakly modulated patterns from fluorescent lamps with electronic ballasts (see Fig. 13 or Fig. 14)•2.4 G Hz and 5 G Hz Wi-FiFig. 13 - IR Disturbance from Fluorescent Lampwith Low ModulationFig. 14 - IR Disturbance from Fluorescent Lampwith High ModulationNote•For data formats with long bursts (more than 10 carrier cycles) please see the datasheet for TSOP62.., TSOP64..169205101520I R S i g n a l A m p l i t u d eTime (ms)169215101520I R S i g n a l A m p l i t u d eTime (ms)TSOP61..TSOP63..TSOP65..Minimum burst length 6 cycles/burst 6 cycles/burst 6 cycles/burst After each burst of length A gap time is required of 6 to 70 cycles ≥ 10 cycles 6 to 35 cycles ≥ 10 cycles 6 to 24 cycles ≥ 10 cycles For bursts greater than a minimum gap time in the data stream is needed of 70 cycles > 1.2 x burst length35 cycles > 6 x burst length24 cycles > 25 ms Maximum number of continuous short bursts/second 200020002000MCIR codeYes Preferred Yes XMP-1, XMP-2 code YesPreferredYesSuppression of interference from fluorescent lampsMild disturbance patterns are suppressed (example:signal pattern of Fig. 13)Complex disturbance patterns are suppressed (example:signal pattern of Fig. 14)Critical disturbance patterns are suppressed,e.g. highly dimmed LCDsASSEMBLY INSTRUCTIONSReflow Soldering•Reflow soldering must be done within 72 h while stored under a max. temperature of 30 °C, 60 % RH after opening the dry pack envelope•Set the furnace temperatures for pre-heating and heating in accordance with the reflow temperature profile as shown in the diagram. Exercise extreme care to keep the maximum temperature below 260 °C. The temperature shown in the profile means the temperature at the device surface. Since there is a temperature difference between the component and the circuit board, it should be verified that the temperature of the device is accurately being measured•Handling after reflow should be done only after the work surface has been cooled off Manual Soldering•Use a soldering iron of 25 W or less. Adjust the temperature of the soldering iron below 300 °C•Finish soldering within 3 s•Handle products only after the temperature has cooled offVISHAY LEAD (Pb)-FREE REFLOW SOLDER PROFILETAPING VERSION TSOP..TR DIMENSIONS in millimetersREEL DIMENSIONS in millimetersLEADER AND TRAILER DIMENSIONS in millimetersCOVER TAPE PEEL STRENGTH According to DIN EN 60286-30.1 N to 1.3 N300 ± 10 mm/min.165° to 180° peel angle LABELStandard bar code labels for finished goodsThe standard bar code labels are product labels and used for identification of goods. The finished goods are packed in final packing area. The standard packing units are labeled with standard bar code labels before transported as finished goods to warehouses. The labels are on each packing unit and contain Vishay Semiconductor GmbH specific data.DRY PACKINGThe reel is packed in an anti-humidity bag to protect the devices from absorbing moisture during transportation and storage.FINAL PACKINGThe sealed reel is packed into a cardboard box. RECOMMENDED METHOF OF STORAGEDry box storage is recommended as soon as the aluminum bag has been opened to prevent moisture absorption. The following conditions should be observed, if dry boxes are not available:•Storage temperature 10 °C to 30 °C•Storage humidity ≤ 60 % RH max.After more than 72 h under these conditions moisture content will be too high for reflow soldering.In case of moisture absorption, the devices will recover to the former condition by drying under the following condition: 192 h at 40 °C + 5 °C / - 0 °C and < 5 % RH (dry air / nitrogen) or96 h at 60 °C + 5 °C and < 5 % RH for all device containers or24 h at 125 °C + 5 °C not suitable for reel or tubes.An EIA JEDEC® standard J-STD-020 level 4 label is included on all dry bags.EIA JEDEC standard J-STD-020 level 4 label is includedon all dry bagsVISHAY SEMICONDUCTOR GmbH STANDARD BAR CODE PRODUCT LABEL (finished goods) PLAIN WRITING ABBREVIATION LENGTHItem-description-18Item-number INO8Selection-code SEL3LOT-/serial-number BATCH10Data-code COD 3 (YWW)Plant-code PTC2Quantity QTY8Accepted by ACC-Packed by PCK-Mixed code indicator MIXED CODE-Origin xxxxxxx+Company logo LONG BAR CODE TOP TYPE LENGTHItem-number N8Plant-code N2Sequence-number X3 Quantity N8 Total length-21 SHORT BAR CODE BOTTOM TYPE LENGTH Selection-code X3 Data-code N3 Batch-number X10 Filter-1 Total length-17TSOP61.., TSOP63.., TSOP65.. Vishay SemiconductorsESD PRECAUTIONProper storage and handling procedures should be followed to prevent ESD damage to the devices especially when they are removed from the antistatic shielding bag. Electrostatic sensitive devices warning labels are on the packaging.VISHAY SEMICONDUCTORS STANDARDBAR CODE LABELSThe Vishay Semiconductors standard bar code labels are printed at final packing areas. The labels are on each packing unit and contain Vishay Semiconductors specific data.22645Tape and Reel Standards for Surface-Mount IR Receiver ModulesVishay Semiconductor surface-mount IR receivers are packaged on tape and reel. The following specification is based on IEC publication 286, which takes the industrial requirements for automatic insertion into account.Absolute maximum ratings, mechanical dimensions, optical and electrical characteristics for taped devices are identical to the basic catalog types and can be found in the specifications for untaped devices.PACKAGINGThe tapes of components are available on reels. Each reel is marked with labels which contain the following information: - Vishay- Type- Group- Tape code, normally part of type name- Production code- QuantityMISSING COMPONENTSUp to 3 consecutive components may be missing if the gap is followed by at least 6 components. A maximum of 0.5 % of the components per reel quantity may be missing. At least 5 empty positions are present at the start and the end of the tape to enable tape insertion.Tensile strength of the tape: > 15 N NUMBER OF COMPONENTSA. Panhead: quantity per reel:TT, top view package, 1190 pcsTR, side view package, 1120 pcsB. Heimdall: quantity per reel:TT, top view package, 2200 pcsTR, side view package, 2300 pcsC. Heimdall without lens: quantity per reel:WTT, top view package, 2200 pcsWTR, side view package, 2300 pcsD. Belobog: quantity per reel:TT1, top view package, 1800 pcsE. Belobog with shield: quantity per reel:TT1, top view package, 1500 pcsF. Minimold DF1P: quantity per reel:DF1P, 1100 pcsG. TVCastSMD TR1: quantity per reel:TR1, side view package, 2000 pcsORDER DESIGNATIONThe type designation of the device is extended by TT or TT1 for top view or TR for side view.Example:TSOP6238TR (reel packing)TSOP75238TR (reel packing)TSOP75338WTT (reel packing)TSOP57438TT1 (reel packing)TSOP57238HTT1 (reel packing)TSOP39438TR1 (reel packing)REEL DIMENSIONS FOR PANHEAD, HEIMDALL, AND TVCASTSMD TR in millimetersNote•The body structure of the reel can varyTAPING VERSION TSOP..TT (TOP VIEW) DIMENSIONS in millimeters A. Panhead (TSOP36...TT, TSSP....TT, TSOP6...TT, TSOP16...TT, TSOP96...TT)TAPING VERSION TSOP..TT (TOP VIEW) DIMENSIONS in millimeters B. Heimdall (TSOP75...TT, TSOP77...TT, TSSP77...TT, TSOP15...TT, TSOP95...TT)TAPING VERSION TSOP..TT (TOP VIEW) DIMENSIONS in millimetersC.Heimdall without lens (TSOP75...WTT, TSOP77...WTT, TSSP77...WTT, TSOP15...WTT, TSOP95...WTT)TAPING VERSION TSOP..TT1 (TOP VIEW) DIMENSIONS in millimeters D.Belobog (TSOP37...TT1, TSOP57...TT1, TSOP17...TT1, TSOP97...TT1)TAPING VERSION TSOP..TT1 (TOP VIEW) DIMENSIONS in millimetersE.Belobog with shield (TSOP37...HTT1, TSOP57...HTT1, TSOP17...HTT1, TSOP97...HTT1)TAPING VERSION TSOP..DF1P (SIDE VIEW) DIMENSIONS in millimetersF. Minimold DF1P (TSOP33...DF1P, TSOP53...DF1P, TSOP13...DF1P, TSOP93...DF1P)(6.08)(1.5 min.)(12)(1.75)(11.5)(24)(2)(4)(1.55)(0.4)(5.25)BBAAB - BA - ATAPING VERSION TSOP..TR (SIDE VIEW) DIMENSIONS in millimeters G. TVCastSMD TR1 (TSOP59...TR1, TSOP39...TR1, TSOP19...TR1, TSOP99...TR1)TAPING VERSION TSOP..TR (SIDE VIEW) DIMENSIONS in millimeters A. Panhead (TSOP36...TR, TSSP6...TR, TSOP6...TR, TSOP16...TR, TSOP96...TR)TAPING VERSION TSOP..TR (SIDE VIEW) DIMENSIONS in millimetersB. Heimdall (TSSP7...., TSOP75...TR, TSOP77...TR, TSSP7....TR, TSOP15...TR, TSOP95...TR)TAPING VERSION TSOP..TR (SIDE VIEW) DIMENSIONS in millimetersC. Heimdall without lens (TSOP75...WTR, TSOP77...WTR, TSSP...WTR, TSOP15...WTR, TSOP95...WTR)LEADER AND TRAILER DIMENSIONS in millimetersCOVER TAPE REEL STRENGTH According to DIN EN 60286-30.1 N to 1.3 N300 mm/min. ± 10 mm/min.165° to 180° peel angle LABELStandard bar code labels for finished goodsThe standard bar code labels are product labels and used for identification of goods. The finished goods are packed in final packing area. The standard packing units are labeled with standard bar code labels before transported as finished goods to warehouses. The labels are on each packing unitand contain Vishay Semiconductor GmbH specific data. VISHAY SEMICONDUCTOR GmbH STANDARD BAR CODE PRODUCT LABEL (finished goods)PLAIN WRITING ABBREVIATION LENGTHItem-description-18Item-number INO8Selection-code SEL3LOT-/serial-number BATCH10Data-code COD 3 (YWW)Plant-code PTC2Quantity QTY8Accepted by ACC-Packed by PCK-Mixed code indicator MIXED CODE-Origin xxxxxxx+Company logoLONG BAR CODE TOP TYPE LENGTHItem-number N8Plant-code N2Sequence-number X3Quantity N8Total length-21SHORT BAR CODE TOP TYPE LENGTHSelection-code X3Data-code N3Batch-number X10Filter-1Total length-17DRY PACKAGINGThe reel is packed in an anti-humidity bag to protect the devices from absorbing moisture during transportation and storage.RECOMMENDED METHOD OF STORAGEDry box storage is recommended as soon as the aluminum bag has been opened to prevent moisture absorption. The following conditions should be observed, if dry boxes are not available:•Storage temperature 10 °C to 30 °C •Storage humidity ≤ 60 % RH max.After more than 72 h under these conditions moisture content will be too high for reflow soldering.In case of moisture absorption, the devices will recover to the former condition by drying under the following condition:192 h at 40 °C + 5 °C / - 0 °C and < 5 % RH (dry air / nitrogen) or96 h at 60 °C + 5 °C and < 5 % RH for all device containers or24 h at 125 °C + 5 °C not suitable for reel or tubes.An EIA JEDEC ® standard JSTD-020 level 4 label is included on all dry bags.EIA JEDEC standard JSTD-020 level 4 label is includedon all dry bagsESD PRECAUTIONProper storage and handling procedures should be followed to prevent ESD damage to the devices especially when they are removed from the antistatic shielding bag. Electrostatic sensitive devices warning labels are on the packaging.VISHAY SEMICONDUCTORS STANDARD BAR CODE LABELSThe Vishay Semiconductors standard bar code labels are printed at final packing areas. The labels are on each packing unit and contain Vishay Semiconductors specific data.OUTER PACKAGINGThe sealed reel is packed into a pizza box.16962Legal Disclaimer Notice VishayDisclaimerALL PRODUCT, PRODUCT SPECIFICAT IONS AND DAT A ARE SUBJECT T O CHANGE WIT HOUT NOT ICE T O IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED。
MIMO-OFDM系统中信道估计解析

题目:MIMO-OFDM系统中信道估计及信号检测算法的研究独创性(或创新性)声明本人声明所呈交的论文是本人在导师指导下进行的研究工作及取得的研究成果。
尽我所知,除了文中特别加以标注和致谢中所罗列的内容以外,论文中不包含其他人已经发表或撰写过的研究成果,也不包含为获得北京邮电大学或其他教育机构的学位或证书而使用过的材料。
与我一同工作的同志对本研究所做的任何贡献均已在论文中作了明确的说明并表示了谢意。
申请学位论文与资料若有不实之处,本人承担一切相关责任。
本人签名:关于论文使用授权的说明学位论文作者完全了解北京邮电大学有关保留和使用学位论文的规定,即:研究生在校攻读学位期间论文工作的知识产权单位属北京邮电大学。
学校有权保留并向国家有关部门或机构送交论文的复印件和磁盘,允许学位论文被查阅和借阅;学校可以公布学位论文的全部或部分内容,可以允许采用影印、缩印或其它复制手段保存、汇编学位论文。
(保密的学位论文在解密后遵守此规定)本学位论文不属于保密范围,适用本授权书。
本人签名:夺^摘要MIMO-OFDM系统中信道估计及信号检测算法的研究输入多输出(MIMO)和正交频分复用(OFDM)是LTE的两大核心技术。
多输入多输出(MIMO)技术利用各种分集技术带来的分集增益可以提高系统的信道容量、数据的传输速率以及系统的频谱利用率,这些都是在不增加系统带宽和发射功率的情况下取得的;正交频分复用(OFDM)技术是多载波调制技术的一种,其物理信道是由若干个并行的正交子信道组成,因此可有效地对抗频率选择性衰落,同时通过插入循环前缀(CP)可以有效消除由多径而引起的符号间干扰(ISI)。
由于多输入多输出(MIMO)在提高系统容量和正交频分复用(OFDM)在对抗多径衰落方面的优势,基于两者结合的MIMO-OFDM系统已经引起了广泛的关注。
信道估计算法和信号检测算法是MIMO-OFDM系统的关键技术。
其中信道估计算法对MIMO-OFDM系统接收端的相干解调和空时检测起着至关重要的作用,信道估计的准确性将影响系统的整体性能。
PowerBox-系统用户手册说明书

Dear customer,We are delighted that you have decided to purchase this PowerBox accessory from our range.We hope you have many hours of pleasure and great success with your PowerBUS devices.The PowerBUS is the basis of a completely new method of wiring servos. The PowerBUS consists of a three-core cable which supplies current and signal to the servos connected to it. At first glance this is nothing unusual, but the big difference lies in the signal wire. When conventional servo signals are transferred, the signal wire always carries the information for one individual servo only - this is a PWM (Pulse Width Modulated) signal. In a servo bus system the signal wire carries posi-tional information for multiple servos in digital form. The information for individual servos includes address data, and since each servo is assigned its own individual address, it can read out …its“ information from the data stream, and convert it into a movement of the control surface. PowerBus to PWM adapters can also be emplo-yed to enable the use of servos without their own decoder; in this case the adapter carries out the decoding.The advantage of this arrangement is obvious: all you need is one three-core lead in order to supply the essential information to several servos. The wiring is much simpler, and there is also a significant weight saving.However, until now there has always been one disadvantage to bus systems: a short-circuit in one servo causes the bus lead to be blocked, and all the servos connected to it stop working. Here at PowerBox-Systems we have completely eli-minated this former drawback:The servo distributors which we have developed are protected against short-cir-cuits in the power supply lines and the signal line! This means that, if one output isshorted out at a servo distributor, within a few micro-seconds that output is swit-ched off, and the bus lead remains active.This supplementary feature is very important to flight safety, since a servo bus without it can never be suitable for use in valuable model aircraft!The following section introduces and describes the individual components of the PowerBUS:1. OVERVIEW OF POWERBUS COMPONENTSThree different types of distributor are available:Order No. 9200 - PowerBUS to PWM AdapterQuadruple distributor with integral BUS/PWM con-verterOrder No. 9210 - PowerBUS to BUS AdapterQuadruple distributor for bus-enabled servosOrder No. 9220 - PowerBUS SplitterSplitter, for converting one PowerBUS lead intotwoThe following standard cable lengths are available:Order No. 9126/30PowerBUS connecting lead, MPX plug / MPX socket, length 30 cmOrder No. 9126/60PowerBUS connecting lead, MPX plug / MPX socket, length 60 cmOrder No. 9126/90PowerBUS connecting lead, MPX plug / MPX socket, length 90 cmOrder No. 9126/120PowerBUS connecting lead, MPX plug / MPX socket, length 120 cmWe can also make up PowerBUS connecting leads to the exact lengths you require. Please refer to our webshop, where you will find a configuring tool for this purpose.2. DESCRIPTION OF POWERBUS COMPONENTSa) PowerBUS SplitterThe PowerBUS Splitter is required if the PowerBox does not feature a sufficient number of outputs. For example, if you wish to use the bus technology for both wings as weil as elevator and rudder, you will need a total of three bus leads. The following diagram shows a typical PowerBUS installation:PowerBUS ComponentsPowerBUS WiresServo Wiresb) PowerBUS to BUS AdapterThe PowerBox to BUS Adapter is designed for use with servos which are fitted with an integral bus decoder. At present these are Futaba S-Bus servos. When the-se servos are used, the channel assignment is programmed directly at the servo. The PowerBox to BUS Adapter does not feature a decoder, but nevertheless all the outputs are protected against short-circuits both in the signal wire and the power supply wires, as you would expect. The adapter includes integral signal amplifiers for all servo outputs as weil as the adapter's PowerBUS output. This means that as many bus adapters as required can be connected in series, i.e. cascaded.c) PowerBUS to PWM AdapterThe PowerBox to PWM Adapter is used for servos which are not filled with a bus decoder. In this case the channel assignment is defined at the PowerBUS to BUS Adapter. The bus signal is decoded in the adapter, which then generates conventi-onal PWM signals for the servos. This unit allows all known makes of servo to be operated with the PowerBUS system. As with the other adapters, all the outputs are protected against short-circuits both in the signal wire and the power supply wires. The adapter includes integral signal amplifiers for all servo outputs as well as the adapter's PowerBUS output. This means that as many bus adapters as re-quired can be connected in series, i.e. cascaded.3. THE POWERBUS - BASIC INFORMATIONThe PowerBUS can carry 16 channels + 2 switched channels. lt is possible to as-sign any functions you wish to the bus, thanks to the unrestricted channel assign-ment facilities of the Champion SRS and Royal SRS. This is important: for examp-le, if you wish to assign the aileron signal - as it comes from the transmitter - to the PowerBUS, and also wish to include the gyro gain and servo match settings. The door sequencer function can also be assigned to the PowerBUS.a) Procedure for setting up the PowerBoxRequirement for subsequent steps:The type of radio control system must be entered correctly at the PowerBox.lf you are using a gyro (with the Royal SRS), you must first complete the iGyro As-sistant procedure to complete the channel assignment on the input side.The first step in assigning particular outputs to the bus is to assign the function in the Output Mapping menu of the PowerBox:You will find this standard display in the OUTPUT MAPPING menu of the Royal SRS. Functions can only be assigned to the PowerBUS if they have already been defined under OUTPUT MAPPING.These instructions include an example which shows the step-by-step procedure for assigning the bus; it also shows how to use the ServoMatch function in conjunction with the PowerBUS.The function of output G is GYRO AILERON A, and the function of output H is also GYRO AILERON A. At first sight the function of both outputs is the same. However, these two functions are to be assigned to an aileron actuated by two servos. The ServoMatch function is used for fine-tuning, to ensure that the travel of both servos is identical.Note: in the case of the Champion SRS it is only possible to select the DIRECT 1 - 16 and DS1 - 6 outputs instead of the gyro channels.Once the function assignment process is complete, move the cursor to the left to P-BUS and confirm your choice by pressing the SET button. You will see this display:The column under P-BUS indicates the PowerBUS channel number. CH1 - CH16 are proportional channels, while CH17 and CH18 are switched channels. At a later stage these numbers are crucial when we move on to programming the servo or the PowerBUS adapter.The OUTPUT is user-variable; here you determine which PowerBox output (A - X) is assigned to the selected BUS channel (1 - 18).The FUNCTION column shows which function is assigned to the output you have selected. This provides a clear overview of the functions which are already assi-gned to the bus.In our example the gyro function GY AILERON A has been assigned to outputs G and H, so that these two functions can be fine-tuned later using the ServoMatch function. At the PowerBUS they have been assigned to channel numbers 2 and 3.b) Procedure for setting up the PWM AdapterOur function GY AILERON A is now assigned to bus channels 2 and 3. The next stage must be to inform the PowerBUS to PWM Adapter (description under 2c) which bus channel is to be generated at which of the four sockets (servo 1 - 4).This is the procedure:b1) Do not connect the adapter to the PowerBUS lead at this stage.b2) Connect the PowerBUS lead to the PowerBox.b3) Press the SET button on the adapter while you plug in the PowerBUS lead.b4)T he red LED lights up at servo 1, then moves step-by-step to servo 4 while you hold the button pressed in.b5)R elease the button when the red light is aligned with the servo output which you want to set up. The red LED now shines less strongly.b6)T o program the output: Briefly press the button the same number of times as the channel which you wish to set up. Tor example, press the button five times in sequence for channel 5.b7)W hen you have finished programming one output, save the setting simply by disconnecting the adapter from the PowerBUS lead. Resume at Point b2) to assign a further output.Back to our example with two ailerons:Hold the SET button pressed in while you connect the bus adapter, then immedia-tely release it again. Servo output 1 at the adapter is required to generate PowerBox output G: press the SET button twice in order to assign bus channel 2 to servo output 1. Now disconnect the bus adapter again.Hold the SET button pressed in once more while you connect the bus adapter, but this time wait until the LED moves on to servo output 2. Servo output 2 at the adap-ter is required to generate PowerBox output H: press the SET button three times in order to assign bus channel 3 to servo output 2. Disconnect the bus adapter again. Now connect the bus adapter and the two servos (outputs 1 and 2), and move the aileron stick at the transmitter: the two servos should operate in parallel.At this point you should call up the ServoMatch function at the PowerBox to ensure that the two aileron servos do not work against each other mechanically.First select output H, and fine-tune the servo which is connected to servo output 2 at the PowerBUS adapter to match the movement of the first servo. Refer to the instructions supplied with the Royal / Champion SRS for a detailed description of this procedure.4. POWERBUS CABLEPowerBUS cable is manufactured specially for PowerBox-SystemsBUS cable is extremely flexible, and is made up using very thin individual strands in order to pass the maximum current through the given cross-sectional area of 1.5mm2. The insulation is made of a special material which is also employed in full-size aviation. lt is virtually indestructible, and offers excellent protection even when reduced to just a thin film around the copper conductor. This insulation pro duces a weight reduction of about 30% compared with the much cheaper PVC. The insulation is not inflammable, and its heat resistance is much higher than the usual PVC.To save more weight, the conductors are of different thickness: power is carried by two thick wires (1.5mm2), while a thin wire of 0.25mmproduces a further weight saving of 27%.The picture clearly shows the thin insulation, the fine individual strands, and the5. PIN ASSIGNMENTOne great advantage of the PowerBUS is that it employs standard commercial MPX connectors. We supply PowerBUS leads in standard lengths, but can also make them up to the lengths you need. Please note that some installations present problems, with the result that the connectors can only be attached once the lead has been installed.The following photos show the correct pin assignments:PowerBUS socket PowerBUS plug6. SERVICE NOTEWe make every effort to provide a good service to our customers, and have now established a Support Forum which covers all queries relating to our products. This helps us considerably, as we no longer have to answer frequently asked questions again and again. At the same time it gives you the opportunity to obtain assistance all round the clock, and even at weekends. The answers come from the PowerBox team, which guarantees that the answers are correct.Please use the Support Forum before you contact us by telephone.You will find the forum at the following address:7. GUARANTEE CONDITIONSAt PowerBox-Systems we insist on the highest possible quality standards in the development and manufacture of our products. They are guaranteed “Made in Germany”!That is why we are able to grant a 24 month guarantee on the PowerBox acces-sory from the initial date of purchase. The guarantee covers proven material faults, which will be corrected by us at no charge to you. As a precautionary measure, we are obliged to point out that we reserve the right to replace the unit if we deem the repair to be economically unviable.Repairs which our Service department carries out for you do not extend the original guarantee period.The guarantee does not cover damage caused by incorrect usage, e.g. reverse polarity, excessive vibration, excessive voltage, damp, fuel, and short-circuits. The same applies to defects due to severe wear.We accept no liability for transit damage or loss of your shipment. If you wish to make a claim under guarantee, please send the device to the following address, together with proof of purchase and a description of the defect:8. LIABILITY EXCLUSIONWe are not in a position to ensure that you observe our instructions regarding in-stallation of the PowerBox accessory, fulfil the recommended conditions when using the unit, or maintain the entire radio control system competently.For this reason we deny liability for loss, damage or costs which arise due to the use or operation of the PowerBox accessory, or which are connected with such use in any way. Regardless of the legal arguments employed, our obligation to pay damages is limited to the invoice total of our products which were involved in the event, insofar as this is deemed legally permissible.We wish you every success using your new PowerBUS ! Donauwoerth, December 2020SERVICE ADDRESS PowerBox-Systems GmbH Ludwig-Auer-Straße 5D-86609 Donauwoerth Germany。
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In combating intentional interference (jamming), it is important to the communicators that the jammer who is trying to disrupt the communication does not have prior knowledge of the signal characteristics except for the overall channel bandwidth and the type of modulation, (PSK, QPSK, etc.) being used. Interference from the other users arises in the multiple-access communication systems in which a number of users share a common channel bandwidth. At any given time, a subset of these users may transmit information simultaneously over the common channel to corresponding receivers. Assuming that all the users employ the same code for the encoding and decoding of their respective information sequence, the transmitted signals in this common spectrum may be distinguished from one another by superimposing a different pseudo-random pattern, also called a code, in each transmitted signal. Thus, a particular receiver can recover the transmitted information intended for it by knowing the pseudo-random pattern, i.e., the key, used by the corresponding transmitter. This type of communication technique, which allows multiple users to simultaneously use a common channel for transmission of information, is called code division multiple access (CDMA). A message may be hidden in the background noise by spreading its bandwidth with coding and transmitting the resultant signal at a low average power. Because of its low power level, the transmitted signal is said to be “covert.” It has a low probability of being detected by a casual listener and, hence, is also called a low-probability-of intercept ( LPI ) signal. Message privacy may be obtained by superimposing a pseudo-random pattern on a transmitted message. The message can be demodulated by the intended receivers, who know the pseudo-random pattern or key used at the transmitter, but not by any other receivers who do not have knowledge of the key.• •Βιβλιοθήκη • •••
MFRC531
Short Form SpecificationFebruary 2002 Revision 2.0PhilipsSemiconductorsCONTENTS1INTRODUCTION (3)1.1Scope (3)1.2Features (3)1.3Applications (3)2BLOCK DIAGRAM (4)3MF RC531 PINNING (5)3.1Pinning Diagram (5)3.2Pin Description (6)3.2.1Antenna Interface (6)3.2.2Analog Supply (6)3.2.3Digital Supply (6)3.2.4Auxillary Pin (6)3.2.5Reset Pin (7)3.2.6Oscillator (7)3.2.7MIFARE® Interface (7)3.2.8Parallel Interface (7)3.2.9SPI Compatible Interface (8)3.3Applications (8)3.3.1Connecting Different µController's (8)3.3.2Application Example (9)4MIFARE® CLASSIC RELATED ITEMS (10)4.1CRYPTO I: Card Authentication (10)4.1.1Initiating Card Authentication (10)4.1.2Second Part of Card Authentication (10)5ELECTRICAL SPECIFICATION (11)5.1DC Characteristics (11)5.2Start up Characteristics (11)MIFARE® is a registered trademark of Philips Electronics N.V1 INTRODUCTION1.1 ScopeThe MF RC531 is member of a new family of highly integrated reader ICs for contactless communication at 13.56 MHz. This reader IC family utilises an outstanding modulation and demodulation concept completely integrated for all kinds of passive contactless communication methods and protocols at 13.56 MHz. The MFRC531 is pin- compatible to the MF RC500, the MF RC530 and the SL RC400.The MF RC531 supports all layers of theISO14443 including the type A and type B communication schemeThe MF RC531 supports contactless communication using MIFARE® Higher Baudrates. The internal transmitter part is able to drive an antenna designed for proximity operating distance (up to 100 mm) directly without additional active circuitry.The receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from ISO14443 compatible transponders.The digital part handles the complete ISO14443 framing and error detection (Parity & CRC). Additionally it supports the fast MIFARE® Classic security algorithm to authenticate MIFARE®Classic (e.g. MIFARE® Standard, MIFARE® Light) products.A comfortable parallel interface, which can be directly connected to any 8-bit µ-Processor gives high flexibility for the reader/terminal design. Additionally a SPI compatible interface is supported.1.2 Features•Highly integrated analog circuitry todemodulate and decode card response•Buffered output drivers to connect an antenna with minimum number of external components •Proximity operating distance (up to 100 mm)•Supports ISO 14443•Supports MIFARE® Dual Interface Card ICs and supports MIFARE® Classic protocol•Supports contactless communication with higher baudrates up to 424kHz •Crypto1 and secure non-volatile internal key memory•Pin-compatible to the MF RC500, MF RC530 and the SL RC400•Parallel µ-Processor interface with internal address latch and IRQ line•SPI compatible interface•Flexible interrupt handling•Automatic detection of the used µ-Processor interface type•Comfortable 64 byte send and receive FIFO-buffer•Hard reset with low power function•Power down mode per software •Programmable timer•Unique serial number•Bit- and byte-oriented framing•Internal oscillator buffer to connect 13.56 MHz quartz, optimised for low phase jitter• 3.3 V to 5 V operation for transmitter (antenna driver) in short range and proximityapplications• 3.3 V or 5V operation for the digital part1.3 ApplicationsThe MF RC531 is tailored to fit the requirements of various applications using contactless communication based on ISO/IEC 14443 standard where cost-effectiveness, small size, high performance with a single voltage supply are important.•Public transport terminals•Handheld terminals•On board units•Contactless PC terminals•Metering•Contactless public phones2 BLOCK DIAGRAMThe block diagram shows the main internal parts of the MF RC531.The parallel µController interface automatically detects the kind of 8 bit parallel interface connected to it. It includes a comfortable bi-directional FIFO buffer and a configurable interrupt output. This gives the flexibility to connect a variety of µC, even low cost devices, still meeting the requirements of high speed contactless transactions.Additionally a SPI compatible interface will be supported. The MF RC531 acts as a slave during the SPI communication. The SPI clock SCK has to be generated by the master. The SPI interface includes a comfortable bi-directional FIFO buffer. The Data processing part performs parallel serial conversion of the data. It supports framing including CRC and parity generation / checking. It operates in full transparent mode thus supporting all layers of ISO 14443 A& B.The status and control part allows configuration of the device to adapt to environmental influences and to adjust to operate with best performance. For communication with MIFARE® Classic products like MIFARE® Standard or MIFARE®Light a high speed CRYPTO 1 stream cipher unit and a secure non-volatile key memory is implemented.The analog circuit includes a transmitting part with a very low impedance bridge driver output. This allows an operating distance up to 100mm. The receiver is able to detect and decode even very weak responses. Due to a highly sophisticated implementation the receiver is no longer a limiting factor for the operating distance.3 MF RC531 PINNING3.1 Pinning DiagramThe device is packaged in a 32 pin SO-package.The device operates with 3 individual power supplies for best performance in terms of EMC behaviour and signal de-coupling. This gives outstanding RF performance and also maximum flexibility to adapt to different operating voltages of digital and analog part.3.2 Pin Description3.2.1 ANTENNA INTERFACEThe contactless antenna interface basically uses four pins:Name Type FunctionTX1, TX2O Buffered Antenna DriversVMID Analog Reference VoltageRX I Analog Antenna Input SignalTo drive the antenna the MF RC531 provides the energy carrier of 13.56 MHz through TX1 and TX2. This signal is modulated by the transmitting data according the register settings.The card responds with load modulation of the RF field. The resulting signal picked up by the antenna is coupled out from the antenna matching circuit and forwarded to the RX-pin. Inside the MF RC531 the receiver senses and demodulates the signal and processes it according to the register settings. Data is passed further on to the parallel interface where it is accessible by the µ-Controller.The MF RC531 uses a separate power supply for the driver stage.Name Type FunctionTVDD Power Transmitter Supply Voltage TGND Power Transmitter Supply Ground3.2.2 ANALOG SUPPLYFor best performance the MF RC531 analog part has a separate supply. It powers the oscillator, the analog demodulator and decoder circuitry.Name Type FunctionAVDD Power Analog Positive Supply Voltage AGND Power Analog Supply Ground3.2.3 DIGITAL SUPPLYThe MF RC531 uses a separate digital supply.Name Type FunctionDVDD Power Digital Positive Supply Voltage DGND Power Digital Supply Ground3.2.4 AUXILLARY PINInternal signals may be selected to drive this pin. It is used for design-in support and test purpose.3.2.5 RESET PINThe reset pin disables internal current sources and clocks and detaches the MF RC531 virtually from the µC bus. If RST is released, the MF RC531 executes the power up sequence.3.2.6 OSCILLATORName Type FunctionXIN I Oscillator Buffer InputXOUT O Oscillator Buffer OutputThe very fast on-chip oscillator buffer operates with a 13.56 MHz crystal connected to XIN and XOUT. If the device shall operate with an external clock it may be applied to pin XIN.3.2.7 MIFARE® INTERFACEThe MF RC531 supports the active antenna concept of MIFARE®. It may handles the base-band signals NPAUSE and KOMP of MIFARE® Core Modules (MF CMxxx) at the pins MFIN and MFOUT.Name Type FunctionMFIN I with Schmitt Trigger MIFARE® Interface InputMFOUT O MIFARE® Interface OutputThe MIFARE® interface may be used to communicate with either the analog or the digital part of the MFRC531 separately in the following ways:•The analog circuit may be used stand-alone via the MIFARE® interface. In that case MFIN will be connected to the externally generated NPAUSE signal. The MFOUT pin provides the KOMP signal.•The digital circuit may be used to drive an external analog circuit via the MIFARE® interface. In that case the MFOUT pin provides the internally generated NPAUSE signal and MFIN will be connected to the KOMP signal from the outside.3.2.8 PARALLEL INTERFACE16 pins control the parallel interface:Name Type FunctionD0 … D7I/O with Schmitt Trigger Bi-directional Data BusA0 … A2I/O with Schmitt Trigger Address LinesNWR / RNW I/O with Schmitt Trigger Not Write / Read Not WriteNRD / NDS I/O with Schmitt Trigger Not Read / Not Data StrobeNCS I/O with Schmitt Trigger Not Chip SelectALE I/O with Schmitt Trigger Address Latch EnableIRQ O Interrupt Request3.2.9 SPI COMPATIBLE INTERFACE4 pins control the SPI compatible interface.Name Type FunctionA0I/O with Schmitt Trigger MOSI, master to slavecommunicationA2I/O with Schmitt Trigger SCK, clock to be generated by themasterD0I/O with Schmitt Trigger MISO, slave to mastercommunicationALE I/O with Schmitt Trigger NSS, enables the SPIcommunication3.3 Applications3.3.1 CONNECTING DIFFERENT µCONTROLLER'SThe MF RC531 supports different parallel µC interfaces and a SPI compatible interface. An intelligent auto-detection logic automatically adapts the parallel interface to the respective bus system. Selection of the device is performed with signal NCS.To connect µ-Controllers using separated address and data bus pin ALE has to be connected to DVDD.To connect µ-Controllers using multiplexed address and data bus pin ALE has to be connected to the signal ALE of the µ-ControllerTo connect µ-Controllers using RNW and NDS (instead of NWR and NRD) the µ-Controller’s RNW has to be connected to pin NWR and NDS to pin NRD.3.3.2 APPLICATION EXAMPLE4 MIFARE® CLASSIC RELATED ITEMS4.1 CRYPTO I: Card AuthenticationFor correct authentication of MIFARE® Classic products the fast CRYPTO 1 stream cipher is available. The corresponding keys have to be programmed into the secure non-volatile key memory of the MF RC531.Only two commands need to be sent by application software to turn on CRYPTO 1 secured communication.4.1.1 INITIATING CARD AUTHENTICATION The correct key for the authentication has to be selected from the secure internal non-volatile key memory and loaded into the internal CRYPTO1 register. Next the authentication command is transmitted to the card.After receiving the first message token from the card, the µ-Controller has to check the communication status flags. If communication so far has been successful the second part of the authentication procedure can be started.4.1.2 SECOND PART OF CARD AUTHENTICATIONData to be transmitted to the card in this phase are generated automatically by the internal CRYPTO 1 unit inside the MF RC531. To request this action the according command has to be triggered.The card will respond with the second message token. Then the communication status flags have to be checked by the µ-Controller. If authentication has been successful further communication with a MIFARE® Classic card continues CRYPTO 1 enciphered.Philips Semiconductors Short From Specification Rev. 2.0 February 2002ISO 14443 Reader IC MF RC53111PUBLIC5 ELECTRICAL SPECIFICATION 5.1 DC Characteristics SYMBOL PARAMETERCONDITIONSMINTYPMAXUNITVoltage Supply 4.5 5.0 5.5VDVDD Digital Supply Voltage 3.0 3.3 3.6AVDD Analog Supply Voltage 4.5 5.0 5.5V TVDDTransmitter Supply Voltage3.35.05.5V Current Consumption I DVDD Operating Digital Supply Current Idle Command6mA I AVDD Operating Analog Supply Current Idle Command,Receiver On 25mA I TVDDOperating Buffered Antenna Driver Supply Currentcontinuous wave50mA5.2 Start up Characteristics ModeCONDITIONSCurrent UNITTimeUNITStartup times and current consumption Power on--< 1000µs Hard Reset via Reset Pin 1µA < 1000µs Soft Reset via Register Setting1µA < 1000µsDefinitionsData sheet statusObjective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may bepublished later.Product specification This data sheet contains final product specifications.Limiting valuesLimiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics section of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application informationWhere application information is given, it is advisory and does not form part of the specification.Life support applicationsThese products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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Pasica 5/v, 11000 BEOGRAD,Tel. +38111 625 344, Fax. +38111 635 777Published by:Philips Semiconductors Gratkorn GmbH, Mikron-Weg 1, A-8101 Gratkorn, Austria Fax: +43 3124 299 - 270 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Internet: Building BE-p, P.O.Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax: +3140 27 24825© Philips Electronics N.V. 1997 SCB52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without any notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.PhilipsSemiconductors。
Digilent Pmod VGA 参考手册说明书
1300 Henley CourtPullman, WA 99163509.334.6306www.store. Pmod VGA Reference ManualRevised May 5, 2017This manual applies to the Pmod VGA rev. AOverviewThe Pmod VGA (Rev. A) provides a VGA port to any board with Pmod connectivity. The VGA port can be used to drive standard displays such as televisions and monitors. The host board must be capable of driving a fast parallel data bus in order to properly drive a display with the Pmod VGA.∙Standard VGA port for connecting commonly founddisplays∙12-bit RGB444 color depth∙Simple, high-speed R-2R resistor ladder DAC∙High-speed buffers support pixel clocks up to 150 MHzThe Pmod VGA.1 SpecificationsPin Signal Description1 R0 Red 02 R1 Red 13 R2 Red 24 R3 Red 35 GND Power Supply Ground6 VCC3V3 Positive Power Supply7 G0 Green 08 G1 Green 19 G2 Green 210 G3 Green 311 GND Power Supply Ground12 VCC3V3 Positive Power SupplyTable 1. Pmod header J1.Pin Signal Description1 B0 Blue 02 B1 Blue 13 B2 Blue 24 B3 Blue 35 GND Power Supply Ground6 VCC3V3 Positive Supply Ground7 HS Horizontal Sync8 VS Vertical Sync9 NC Not Connected10 NC Not Connected11 GND Power Supply Ground12 VCC3V3 Positive Power SupplyTable 1. Pmod header J2.1.1 Physical DimensionsThe pins on the pin header are spaced 100 mil apart. The PCB is 1.7 inches (4.3 cm) long on the sides parallel to the pins on the pin header and 1.7 inches (4.3 cm) long on the sides perpendicular to the pin header.2 Functional DescriptionThe Pmod VGA uses 14 input pins to create an analog VGA output port. This translates to 12-bit color depth and two standard sync signals: Horizontal Sync (HS) and Vertical Sync (VS). The digital-to-analog conversion is done using a simple R-2R resistor ladder. The ladder works in conjunction with the 75-ohm termination resistance of the VGA display to create 16 analog signal levels for the red, blue, and green VGA signals. This circuit produces video color signals that proceed in equal increments between 0V (fully off) and 0.7V (fully on). With 4 bits each for red, blue, and green, 4096 (16x16x16) different colors can be displayed, one for each unique 12-bit pattern.When used with an FPGA host board, a video controller circuit must be created in programmable logic to drive the sync and color signals with the correct timing in order to produce a working display system. It may be possible to drive the video signals using a very fast microcontroller with a parallel bus controller; however, Digilent does not provide examples for this use case.2.1 Interfacing with the PmodVGA signal timings are specified, published, copyrighted, and sold by the VESA organization (). The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode.NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website. CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen.LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays,LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs).Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of the display end of a cathode ray tube (see Fig. 1).Electron beams emanate from “electron guns,” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.” The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow.Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom, as shown in Fig. 2. As the cathode ray moves over the surface of the display, the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point.Informati on is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution.Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns. The controller must produce synchronizing pulses at 3.3V to set the frequency at which current flows through the deflection coils, and it must ensure that video data is applied to the electron guns at the correct time. Raster video displays define a number of “rows” that corresponds to the number of horizon tal passes the cathode makes over the display area, and a number of “columns” that corresponds to an area on each row that is assigned to one “picture element”, or pixel. Typical displays use from 240 to 1200 rows and from 320 to 1600 columns. The overall size of a display and the number of rows and columns determines the size of each pixel.Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location (the Pmod VGA uses 12 bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel.A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on th e display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Fig. 3 can be derived. Timings for sync pulse-width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays.A VGA controller circuit, such as the one diagrammed in Fig. 4, decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and you can use this counter to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation.3 Additional InformationThe schematics of the Pmod VGA are available here. Additional information about the transceiver used including voltage levels and specific timings of the chip can be found by checking out its datasheet here.Example code demonstrating how to get information from the Pmod VGA can be found on its ResourceCenter here.If you have any questions or comments about the Pmod VGA, feel free to post them under the appropriate section (“Add-on Boards”) of the Digilent Forum.。
Bluetooth Testing(有关蓝牙测试)-agilent
• Test source performs the non-ideal transmitter role
Single and Multi-Slot Packet Sensitivity Tests:
Bluetooth Radio Link Requirements
Test Concept
• Test Purpose • To verify the physical layer of the Bluetooth protocol stack, that is RF and parts of BB
(PGFSK-4dB) < PDPSK < (PGFSK+1dB)
DPSK Average Power, PDPSK
Spectrum Occupancy
Bluetooth EDR Bluetooth 1.2
-20dB BW 1.5MHz
Modulation Accuracy Measurements
• Interoperability between products and brands • The Bluetooth Protocol Testing • The Bluetooth Profile Testing
Agenda
• The Bluetooth RF and Baseband Testing • The Bluetooth Protocol Testing • The Bluetooth Profile Testing
Compare ?
Reply Packet
Decode Packet
LTE介绍(诺西-英文)
…
Frequency
…
Time
25.892 Figure 1: Frequency-Time Representation of an OFDM Signal
OFDM is a digital multi-carrier modulation scheme, which uses a large number of closely-spaced orthogonal sub-carriers. Each sub-carrier is modulated with a conventional modulation scheme (such as QPSK, 16QAM, 64QAM) at a low symbol rate similar to conventional single-carrier modulation schemes in the same bandwidth.
For internal use 10 © Nokia Siemens Networks Charles / 2009-05-05
LTE System Architecture
For internal use 11 © Nokia Siemens Networks
Charles / 2009-05-05
Short TTI = 1 ms Transmission time interval HARQ: Hybrid Automatic Repeat Request
DL: OFDMA UL: SC-FDMA
1
2
NACK
ACK
1
Combined 2 decoding Rx Buffer
Channel only changes amplitude and phase of subcarriers
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Multi-Carrier Spread-Spectrum SystemsArmin Dekorsy,Stephan Fischer,and Karl-Dirk KammeyerUniversity of Bremen,FB-1,Department of TelecommunicationsP.O.Box330440,D-28334Bremen,Germany,Fax:+(49)-421/218-3341,e-mail:dekorsy@comm.uni-bremen.deABSTRACTFor a multi-carrier spread-spectrum(MC-SS)system,the innerspreading can be optimized by applying-ary orthogonal mod-ulation.In this paper,we investigate the concatenation of max-imum likelihood(ML)Viterbi decoding with-ary orthogonaldemodulation in a MC-SS system.The system operates over afrequency-selective Rayleigh fading indoor channel in the up-link.Wefirst evaluate the bit specific log-likelihood ratio for MLViterbi decoding and present an estimation of the ratio exploitingthe MC technique.Furthermore,the trade-off between channelcoding,-ary orthogonal modulation and simple spreading willbe considered by Monte-Carlo simulations.The results are al-ways compared with BPSK performance and they emphasize forthe concerned indoor transmission scenario that a moderate bit-error-rate can only be achieved if-ary orthogonal modulationis employed.All simulations are related to the European Hiperlan/2standard-ization whereas the results are generally valid.I.INTRODUCTIONFuture wireless radio systems need to make efficient use of thefrequency spectrum.One technique offering high spectrum effi-ciency is the multi-carrier-modulation technique orthogonal fre-quency division multiplexing(OFDM).With OFDM,the fadingof each subcarrier can be assumed as frequency-nonselective.Toachieve frequency diversity,OFDM can be combined with codedivision multiple access(CDMA),where the signal is spread overall subcarriers.This concept wasfirst introduced as OFDM-CDMA or also as multi-carrier(MC-)CDMA by[1,2]and isalso called MC-spread spectrum(MC-SS).In the recent few years,most publications dealing with MC-SShave been focused on classical modulation schemes such as BPSK[3,4]and several maximum likelihood(ML)decoding strategieswere proposed[5,6].Instead of using classical modulation schemes,SS techniquesoffer the possibility to apply-ary orthogonal modulation[7].With this modulation,the inner spreading of the MC-SS systemis optimized by spreading in two successive steps:(i)spreadingby the modulation itself and(ii)additional simple replication ofthe transmitted information into parallel subcarriers to performSS technique.The optimization is carried out without changingthe required bandwidth.Investigations without forward errorFigure1:MC-SS transmitter MC-SS transmitter(mobile station)with channel encoding andWalsh modulation is illustrated infig.1.For simplicity,one ofactive users is shown and subscripts are omitted.The data bits,each of duration,are convolution-ally encoded with code rate.The input of the en-coder is a sequence of subsequent data bits and the out-put is the encoded bit sequence of bits,each with duration .After block interleaving()the encoded bits are serial/parallel converted to groups of bits each.The Walsh modulation maps the encoded bits to one corre-sponding Walsh symbol(vector),including Walsh chips.Each of the parallel Walsh chips has a duration of.This modulation can also be interpreted as a block code of rate.The set of or-thogonal Walsh symbols describes the Hadamard-Matrix [7,10],and the Euclidian distance is identical for all possible pairs of symbols and equals(1)To obtain the transmitted symbols,the Walsh chips are repli-cated into parallel copies where each branch of the parallel stream is multiplied with one chip of the user specific PN-code(3) Thefirst term of(3)describes the spreading of the Walsh mod-ulation,the second one the ratio of simple spreading()over the code rate of the channel code,whereas the third term takes into account the guard time.For our comparisons,the product remains unchanged due to the exploitation of the inherently overall spreading factor1.Decreasing the BER can be achieved by sharing between channel coding,-ary orthogonal Walsh modulation and simple spreading.The data rate is based on binary modulation without channel coding()and the bandwidth is generally given.B.Coherent receiverThe MC-SS receiver for-ary orthogonal Walsh modulation is shown infig.2.Paying attention to active users,the received signal after OFDM demodulation and deinterleaving()can be written as a sum of vectors(4) with elements and.The vector represents Additive White Gaussian Noise AWGN.After multiplication with the user spe-cific code and equalization,thefirst part of despreading is ob-tained by subcorrelating subcarriers.Reception for the user is assumed(subscripts are omitted).The components of are given by(5) where indicates the equalization coefficient of the-th subcar-rier.We take into account the well-known equalization scheme maximum ratio combining(MRC)which shows the best perfor-mance for an uplink transmission[8].If perfectly known channel coefficients are assumed2,then.To enable maximumFigure2:MC-SS receiver likelihood detection(MLD),the signal is correlated with all pos-sible Walsh symbols,.The MLD canbe realized by the Fast Hadamard Transform(FHT),where theoutput vector contains decision variables.In case of MLD,optimum decoding,e.g.of a convolutional code,is performedby the application of a soft input Viterbi algorithm(V A)wherechannel state information is exploited.Therefore,the reliabil-ity estimator exploits the decision variables to calculate theassigned bit specific log-likelihood ratio which is fed to theViterbi channel decoder after deinterleaving().Afterwards,we obtain the estimated data stream with bits.III.ML DECISION DECODINGIn the following,we will derive the bit specific log-likelihoodcriterion for ML decoding of-ary orthogonally modulated sig-nals.We consider coherent MC-SS demodulation with MRC equalization.The MAI is taken into account as AWGN and inde-pendent adjacent fading subcarriers ensured by perfect frequency interleaving()are assumed.A.Antipodal TransmissionLet usfirst assume binary antipodal transmission on a single car-rier system with denoting the-th transmitted en-coded bit.Hard decision at the receiver leads to the binary en-coded bit.For a memoryless discrete binary sym-metric channel the likelihood criterion for ML channel decodingis given by[12]of the log-likelihood ratio can be interpretedas a reliability indicator for the hard decided code bit.Due to the fact that involves channel state information the application of eq.(6)results in optimum performance under time-variant channels.For example,if the transmitted signal suffers from fading and is disturbed by AWGN,the log-likelihood ratio results in(8) If equiprobable transmitted symbols are assumed,we get .Due to the statistical independence of the com-ponents of,the conditional probability density can be(9)where and.The terms and can be calculated uniquely.In case of the considered coherent MRC detection one obtain a zero mean Gaussian distribution with variance for the-th component where the hypothesis does not hold,i.e.:exp(11) with mean(13)(the union of all elementary events has probability one).The calculation of(14)requires the knowledge of the noise variance and the expected value of the average channel energy over all subcarriers. These parameters can be estimated as follows:(i)noise variance estimationAssuming that the decision variable with maximum magnitude, denoted by,represents the true hypothesis,we obviously obtain an estimate of the noise power by the mean over components containing the false hypotheses:(16) With(13)-(16),all parameters needed for the calculation of the conditional symbol probability(12)are known.The results can be summarized for all hypotheses:If the symbols are re-placed by their corresponding bit patternsin antipodal representation,we obtain(e.g.for)...(17)The application of eq.(6)requires knowledge of the probabilities of individual bit-decisions which can be gained by a columnwise evaluation of(17).Note,atfirst,that eq.(6)does not depend on the specific choice of the decision for bit,sinceand serves as a soft input for the Viterbi channel decoder.The other bits are treated equivalently.IV.SYSTEM COMPARISONA.System descriptionRelated to the European H IPERLAN/2standardization,the results followed are given for a transmission over an indoor Rayleigh fading channel.The bandwidth is in the range.A velocity of m/s results in a very low maximum Doppler frequency of about.Hence,long symbol-ary orthogonal modulation can be applied.Furthermore,due to the very low maximum Doppler frequency,the fading on each subcarrier is highly statistically dependent.To avoid bursty er-rors,sufficient frequency interleaving ()is required.First,the indoor channel is modeled assuming sufficient frequency inter-leaving.Subsequently,we take into account an exponential delayprofile with a maximum delay spread ofns and a coherent bandwidth of approximately .I.e.the number of independent subcarriers is reduced dramatically.The trade-off between coding and spreading is carried out for anunchanged product(3)and is based on binary modulation without FEC withsubcarriers.The guard time is chosen to be ns.This system design results in a data rate of kbit/s for all cases of spreading and coding.A block interleaver ()with rows and columns is used to separate the channel code and the -ary Walsh modulation.We employed two convolutional codes of rate and,both with constraint length [10].For all cases,active users are taken into account and perfect channel estimation as well as perfect synchronization is assumed for the considered user.B.Simulation ResultsFig.4shows the BER of the -ary Walsh modulation forby sharing between simple spreading andFEC of rates ;see (3).Independent of the -ary modulation the results indicate that choosing a higher amount of simple spreading combined with less powerful FEC ()outperforms the scheme with lower amountcombined with more powerful FEC ().Note the gain of approximately in at a BER of for the -ary modulation.This fact can be explained for by1010101010B E R →Figure coding,-ary Walsh modulation and simple spreading forand codes of ratethe higher loss due to an unchanged guard time but a shorter symbol duration and an additional lower energy of the coded bit in front of the Viterbi decoder 4.Moreover,less number ofsion over an indoor channel with coherence bandwidth of ap-proximately.BPSK and-ary Walsh modulation are considered.In contrast tofig.5,there exists a significant loss due to the statistical dependence of the adjacent subcarriers.The re-sults emphasize for an MC-SS uplink transmission over an indoor Rayleigh fading channel that BPSK even combined with FEC leads to an unacceptable BER.Moderate performance can only be achieved if-ary orthogonal Walsh modulation is applied. One has to mention that the degradation is mainly caused by the insufficient frequency interleaving.There exists only a slight degradation due to the assumption of independent subcarriers for the derivations of the log-likelihood ratios.V.CONCLUSIONIn this paper,we have investigated the concatenation of-ary orthogonal Walsh modulation and ML Viterbi decoding for the MC-SS transmission over a frequency-selective slowly Rayleigh fading channel in the uplink.In particular,we havefirst evalu-ated the bit specific log-likelihood ratio of the-ary orthogonal modulated signal for the ML Viterbi decoding.Assuming an un-changed bandwidth and data rate,we further analyzed the trade-off between coding and spreading to optimize the BER.Monte-Carlo simulation results indicate to better strengthen the inner spreading consisting of-ary orthogonal modulation and simple spreading with an inherently less powerful channel code.The results are always compared with BPSK performance and it is shown that already-ary orthogonal Walsh modulation outper-forms BPSK.Moreover,they emphasize that for an indoor sce-nario a moderate BER can only be achieved if the inner spreading is optimized,for example,by applying-ary orthogonal Walsh modulation.BPSK even combined with channel coding leads to an unacceptable BER.REFERENCES[1]K.Fazel and L.Papke.On the performance of convolutionally-coded CDMA/OFDM for mobile radio communication system.In Proc.IEEE Int.Symp.on Personal,Indoor and Mobile Radio Commun.(PIMRC’93),pages D3.2.1–D3.2.5,September1993. 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