微波仿真理论基础

Basic BJT Circuit

Figure 1 below shows the simplied ‘Pi’ model of a BJT.

c

Vin

Vout

Zin

Vout

B

C

Β.ib ib

Figure 1 Transistor symbol and simplified ‘Pi’ model

We can see that output consists of a current source –gm.Vbe to get the output voltage we multiply by the load resistance Rce ie Vout = -gm.Vbe.Rce (the negative sign denotes signal inversion).

The input resistance of the circuit is given by:

e temperatur room at (23.5mV)0.0235V ely approximat is and voltage thermal the as known is V (mS)

ctance Transcondu gm Kelvin in e Temperatur T 1.6022x10 charge Electron q 1.3807x10 constant Boltzmans

k where q k.T V ; V I gm where gm

β

R T 19-123-T T CQ IN =========?C

JK

The output resistance is given by:

ge(V)EarlyVolta V Where I V

rce R A CQ

A OUT ===

The voltage gain (Av) is given by:

T

A CQ A T CQ be be IN OUT V V V

I V .V I rce . V rce .V . V V A ==?=?==

gm gm

The current gain (Ai) is given by:

β- i β.i - I I A b

b

IN OUT i ===

The MOS Transistor

These devices are known as FET’s (Field effect transistors), which consist of three regions source, drain and gate. The resistance path between the drain and source is, controlled by applying a voltage to the gate. This varies the depletion layer under the gate and thus

reduces or increases the conductance path. The FET input impedance (unlike the BJT which is a few K ?) is very high (~M ?’s) and as a result the gate current can be considered as zero.

As per the BJT the FET is best described by it’s Output I-V DC characteristics (N-type

enhancement characteristics shown below), however things are complicated by the fact there are two types of FET depletion and enhancement that are both available as N-type or P-type devices. For low frequencies the enhancement devices is more commonly used (Depletion mode types will be described when discussing microwave devices).

0 = 0V

1

2

3

Triode Region Or Linear Region

GS

T GS DS V V V ?=

(1) Cut-Off Region – In this region the gate voltage is less than the pinch-off voltage Vp and therefore very little current flows.

(2) Triode Region – In this mode the device is operating below pinch-off and is effectively a variable resistor. R OUT is ~ linear but only over a small range of V DS .

(3) Saturation Region – This is the main operating region for the device. The drain voltage has to be greater than the gate voltage less the pinch-off voltage – this sets the minimum

supply voltage. The curves in the saturation region can be extrapolated to a point 1/λ, where λ is known as the ‘Channel length modulation parameter, (units V -1), - this is analogous to the BJT Early voltage.

Referring to the saturation region we can assume the response is approximately linear such that the:-

resistance high e,conductanc small ie λ.I G λ

1I λ1V I V 1

if then

0.01 to 0.001 region the in typically is λλ1V I G therefore 1I .G

1

- VDS then c mx - y form the of line straight a assume we If G e conductanc output Device curve of slope R resistance output Device curve

of slope 1

D O D

DS D DS DS D O D O

O

O

≈??

=?

????

?

??

>>??

???

??

?=+????????=+===λ

λ

To complete the model for the FET we need to add the term for the linear region which, is dependant on the device mobility and gate dimensions.

I ()

DS DS DS DS DS DS

O DQ DQ D λ.V 1.I .V λ.I I .V G I I I +=++?

+=

DS DS T GS OX O V .2-V -V .L .C .?????

????μ

()()parameter

modulation length Channel voltage

threshold Device VT ratio aspect the as Known W/L length channel Effective L width

channel Effective W oxide

gate of area unit per e capacitanc t

C device of mobility Surface Where only

region /linear saturation -non .V 1V .2V -V -V .L W .C . ID OX

OX OX O DS DS DS T GS OX O ========+??????

??????=λεμλμ

For saturation region ie V DS > (V GS -V T )

[]()

[]()parameter

ctance transcondu Intrinsic the as Known .C μ K Where λ.V 1V -V 2

L W .K

I as

written -re Sometimes parameter ctance transcondu the as Known 2L W .C μ

β Where λ.V 1V -V β I OX O P DS 2T GS P D OX O DS 2

T GS D =+?

????=?

?

?

???=+=

Usually λ.V DS << 1 so

[]

2

T GS D V -V β I ≈

The following page shows some typical values of the above parameters for use with a level 1 MOS model. The ADS version of this model is also shown

Typical MOS Spice Parameters

n-Well CMOS Level 1 SPICE Model parameters

Level 1 SPICE Parameter n-channel

MOSFET

p-channel

MOSFET

Units

Gate oxide thickness

TOX

150 150 Angstrom Transconductance

Parameter KP

50 x 10-625 x 10-6Amp/V2 Threshold Voltage VT0 1.0 -1.0 Volts

Channel-length modulation parameter LAMBDA 0.1/L

L in micron

0.1/L

L in micron

V-1

Bulk Threshold

Parameter GAMMA

0.6 0.6 V1/2

Surface Potential PHI 0.8 0.8 V

Gate-drain overlap

capacitance CGDO

5 x 10-10 5 x 10-10F/m

Gate-source overlap

capacitance CGSO

5 x 10-10 5 x 10-10F/m

Zero-bias planar bulk

depeletion

capacitance CJ

10-4 3 x 10-4F/m2

Zero-bias sidewall bulk

depletion capacitance

CJSW

5 x 10-10 3.5 x 10-10 F/m

Bulk junction potential

PB

0.95 0.95 V Planar bulk junction

grading coefficient MJ

0.5 0.5 None Sidewall bulk junction

grading coefficient

MJSW

0.33 0.33 None

VAR VAR2LAMBDA=0.1/L

L=0.5

W=100

MOSFET_NMOS MOSFET1

Mode=nonlinear

Temp=

Region=Mult=Nrs=Nrd=Ps=Pd=As=Ad=Width=W um Length=L um Model=MOSFETM1LEVEL1_Model MOSFETM1AllParams=

Imax=

Ffe=Tt=N=Tnom=Rds=Rg=Fc=Af=Kf=Gdsnoi=1

Nlev=Uo=Ld=Tpg=Nss=Nsub=Tox=150e-10Js=

Mjsw=0.33Cjsw=5e-10Mj=0.5

Cj=1e-4Rsh=Cgbo=Cgdo=5e-10

Cgso=5e-10Pb=0.95Is=

Cbs=Cbd=Rs=

Rd=Lambda=LAMBDA Phi=0.8

Gamma=0.6Kp=50e-6

Vto=1PMOS=no NMOS=yes

As with the BJT it is possible to simulate a device under ADS to produce the device Output I-V curve trace for a typical N-type MOS 3.3V 0.25um process enhancement device. The Spice data for the MOSFET model is called up from the spice file ‘tsmc_https://www.360docs.net/doc/094202092.html,’.

spiceInclude SPICE1

File="tsmc_https://www.360docs.net/doc/094202092.html,"NetlistDebugMode=0

VAR VAR1VDS=0

VGS=0

DC1

SweepVar="VDS"Start=0Stop=3.3Step=.1

Other=OutVar="MOSFET1.Gm"

Sweep1

SweepVar="VGS"

SimInstanceName[1]="DC1"SimInstanceName[2]=SimInstanceName[3]=SimInstanceName[4]=SimInstanceName[5]=SimInstanceName[6]=Start=0Stop=2Step=0.2

The resulting plot

0.0

0.5

1.0

1.5

2.0 2.5

3.0 3.5

-5

5 10

15 20 25 30 35 40 45 Vgs

VDS

IDS.i, mA

The device will also have a transconductance Curve ie V GS vs I DS . The ADS simulation below sweeps the gate voltage and measures the resulting drain current.

DC1

Other=OutVar="MOSFET1.Gm"

Step=.1

Stop=3Start=0

SweepVar="VGS"

VAR VAR1VDS=3.3

VGS=0spiceInclude SPICE1

File="tsmc_https://www.360docs.net/doc/094202092.html,"

NetlistDebugMode=0

Resulting transconductance curve, slope is the G M of the device.

0.0

0.2

0.4

0.6

0.8

1.0 1.2 1.4 1.6 1.8

2.0 2.2 2.4 2.6

2.8

3.0

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050

0.055

0.060

0.065

0.070

0.075

0.080

0.085

VGS

IDS.i

Slope of curve = gm

IDS (A)

Pinch-off voltage = 0.6V

And for the P-type device

Input transconductance trace

MOSFET_PMOS MOSFET1

Mode=nonlinear

Temp=

Region=Mult=2Nrs=Nrd=Ps=Pd=As=Ad=Width=100 um Length=0.5 um Model=MODpch3_1

DC1

Other=OutVar="MOSFET1.Gm"

Step=-.1

Stop=-5Start=0SweepVar="VGS"

VAR VAR1VDS=-3.3

VGS=0spiceInclude SPICE1

File="tsmc_https://www.360docs.net/doc/094202092.html,"NetlistDebugMode=0

Resulting trace

-5

-4

-3

-2

-1

-0.07

-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0.00

VGS

IDS.i

spiceInclude SPICE1

File="tsmc_https://www.360docs.net/doc/094202092.html,"NetlistDebugMode=0

MM9_NMOS MOSFET1

Mode=nonlinear

Mult=2

Temp=Lg=Ls=Ab=Width=100 um Length=0.5 um Model=MODnch3_1

ParamSweep Sweep1

Step=1

Stop=5Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="DC1"SweepVar="VGS"

DC1

Other=OutVar="MOSFET1.Gm"

Step=.1

Stop=3Start=0SweepVar="VDS"VAR VAR1VDS=3.3

VGS=0

Output characteristic trace

-5

-4

-3

-2

-1

-0.07

-0.06 -0.05 -0.04 -0.03 -0.02

-0.01 0.00 0.01 VDS

IDS.i

Body Effect

The FET body or ‘Bulk’ is known either as the substrate, back gate or more commonly the Body. It is normally connected to the lowest voltage potential of the circuit (usually the

source). However if is left unconnected its effect on the DC characteristics of the device must be taken into account. If we include the bulk effect the value of the threshold voltage V T will increase with increasing bulk voltage.

()

source) the to connected bulk (ie 0 V for V V normally Therefore,(Volts)

potential source Bulk V (Volts) potential level Fermi .F (Volts)parameter hold Bulk thres γ.F 2..F 2.V -γ V V BS T TO BS BS TO T ====Φ=Φ?Φ++=

If the device was biased without the bulk node connected then a change in operating point could take the device out of its saturation region and significantly change the circuit

performance. The bulk voltage is thus a very important parameter in circuit applications and therefore it is best to connect the bulk to the device source connection.

The circuit is drawn as follows:-

The simulation below shows how varying the bulk voltage will vary the pinch-off voltage of the device.

VAR VAR1VBS=0

VGS=0Sweep1

Step=0.1

Stop=1Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="DC1"SweepVar="VGS"

DC1

Other=OutVar="MOSFET1.Gm"

Step=0.5

Stop=3Start=0SweepVar="VBS"V_DC SRC4Vdc=VBS

spiceInclude SPICE1

File="tsmc_https://www.360docs.net/doc/094202092.html,"NetlistDebugMode=0

Resulting plot showing that the pinch-off voltage increases with increasing bulk voltage

0.0

0.2

0.4

0.60.8 1.0

0.000

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

IDS.i

Increasing pinch-off voltage

From the last section we found that the drain current in the saturation region =

[]2

T GS D V -V β I ≈

Transconductance

[][][][][]D 5

.0D 0.50.5-5.0D 1D D

T GS 2

T GS D T GS GS

T GS D GS 2

T GS D GS

D M I .β2 I .2β βI .2β β

I 2β

GM (1) into sub β

I

V -V then V -V β I rearrange we If

(1) - V -V 2β GM V .V -V 2β I V wrt ate differenti therefore V -V β I curve

transfer of slope ie V I

G =======?=?=??=

Output Conductance

()()()()λ.I G V I V λ..I I (2)

into sub V -V βI above From (2) - V λ..V -V β I V wrt ate Differenti λ.V 1V -V βI stic

characteri output of slope ie ?V ?I G D O DS

D

DS D D 2

T GS D DS 2

T GS D S D DS 2

T GS D DS

D

O ==??=?=?=?=?+==

Voltage Gain A

L .W K .I 2.λ1 .I .L .2.W .K .λ2 I 1.2L .W K .λ2 2L .W K β and I β.

λ2 A .λI .2.β .λ.I I .2.β λ.I β.I 2 G G e Conductanc Output ctance transcondu

A P D 0.5

-D 0.5-0.5-0.50.5P 1-1D P P D

1

0.5-D 0.511

D 0.5D 0.5D

D O M ==========???

Common-Base/Gate Circuits

Common-Base BJT circuit

The figure below shows the simplied ‘Pi’ model of a common-base BJT.

r ce

Vin

Zin

V I e wher gm 1

r 1)(βi 1).r (βi I V R T

CQ be b be b IN IN IN ===++==

gm

)r gm

1

(as V V I V .V I r r 1)r (βr .β 1)r (βi r .i .β V V A ce T A CQ A T CQ be ce be ce be b ce b IN OUT V ===≈+=+==

()

1 1ββ

)1βi β.i I I A b b IN OUT i ≈+=+==

r ce

To determine the Output impedance of the circuit we can connect a voltage source (V s + R s ) to the base and ground the input ie the emitter. We then have to resistances in parallel connected to the current source β.i b .

()equation

above into sub R r R i i Also r .i r i .i V i V

R s

be s

T b be b ce b T OUT T

OUT

OUT +=++==β

s

be be s s be s ce ce T OUT OUT be s ce s

T ce s be s T T

OUT R r r

.R R r R r .r i V R r .R r R i r R r R i .i V ++++==++????????++=ββ

()ce ce ce OUT s ce

OUT s r .1 1r .r R then large R If r R then 0 R If +=++====ββ

Common-Gate MOSFET Circuit

g

r ds

Vout

Vin

I IN

Voltage Gain A v

()

R r .R r gm A //R r gmVsg V Vsg V V V

A L dg

L dg V L dg O IN IN

O

V ?

???

????+====

Input Resistance

λI gm

1 gmVgs Vgs I V

R D IN IN IN ====

Output Resistance

As the source is low impedance ie close to ground for R OUT – r ds appears to be connected across r ds to ground.

ds dg O

O OUT //r r I V

R ==

Current Gain A i

A i = 1

Common-Emitter/Source Circuits

Common-emitter BJT circuit

The figure below shows the simplied ‘Pi’ model of a common-emitter BJT.

Vout

E

B

C

Β.ib ib

Vin

Vout

Zin

(mS)

ctance Transcondu Kelvin

in e Temperatur T 1.6022x10

charge Electron q 1.3807x10 constant Boltzmans k where

q k.T V ; V I where R 19

-123

-T T

CQ IN =========

?gm C JK gm gm β

ge(V)EarlyVolta V Where I V

rce R A CQ

A OUT ===

T

A CQ A T CQ be be IN OUT V V V

I V .V I rce . V rce .V . V V A ==?=?==

gm gm

ββ- i .i - I I A b b

IN OUT i ===

Common-Source MOS FET Circuit

drain

Vout

s

d Io

Voltage Gain A v

()

R r .R r gm - A //R r gmV - V V V

A L ds

L ds L ds IN O IN

O V ????

????+=== Input Resistance

R IN = ∞

Output Resistance

L ds O

O

OUT //R r I V

R ==

Current Gain A i

A i = ∞