IP178D 芯片datasheet

IP178D
Preliminary Data Sheet
8 Port 10/100 Ethernet Integrated Switch
(Port Mirror, TCP/UDP QoS & VIP Port QoS)
Features
Wide operating temperature range IP178D LF (0°C to 70°C) IP178D LFI (-40°C to 85°C) IP178C pin to pin compatible Support 2k MAC address Support auto-polarity for 10 Mbps Support filter/forward special DA option Support broadcast storm protection Auto MDI-MDIX option Two queues per port for QoS purposes Support Port based QoS Support 802.1p & DiffServ based QoS QoS Port base 802.1p IP DiffServ IPV4/IPV6 TCP/UDP port number Pins configure ports priority (VIP port) Support max forwarding packet length 1552/1536 bytes option Support port mirror function Support two dynamic fiber ports for Hot Plug Built in linear regulator control circuit Support Lead Free package (Please refer to the Order Information) 0.16um Process
General Description
IP178D integrates an 8-port switch controller, SSRAM, and 8 10/100 Ethernet transceivers. Each of the transceivers complies with the IEEE 802.3, IEEE 802.3u, and IEEE 802.3x specifications. The transceivers are designed in DSP approach in 0.16um technology; they have high noise immunity and robust performance. IP178D supports a lot of QoS function, including 802.1p, DiffServ, TCP/UDP port number and High priority port. User could enable QoS function from Pin or EEPROM. IP178D also supports port mirror function for each port. User could monitor RX and TX port. There are two fiber ports, port 6 and port 7, could be enable and disable from pin.
1 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
Table of Contents
Features..................................................................................................................................................................................1 General Description...............................................................................................................................................................1 Table of Contents...................................................................................................................................................................2 Revision History.....................................................................................................................................................................4 The difference in pin definition between IP178C/IP178CH and IP178D ........................................................................5 Features comparison between IP178C and IP178D........................................................................................................6 1 Pin diagram....................................................................................................................................................................7 2 IP178D application diagram ........................................................................................................................................8 2.1 An 8 TP port switch application.............................................................................................. 8 2.2 An 8-port switch mixed with two fiber ports ........................................................................... 8 2.3 TCP/UDP QoS Switch for time-sensitive application from pin setting ................................... 9 2.4 Switch with VIP ports for specific users from Pin setting ....................................................... 9 2.5 A 8-port Switch with Port mirror capability setting from EEPROM....................................... 10 3 Pin description.............................................................................................................................................................11 3.1 Analog pins ...........................................................................................................................11 3.2 System clock & reset pins.................................................................................................... 12 3.3 EEPROM interface............................................................................................................... 13 3.4 Serial Management Interface............................................................................................... 13 3.5 Boundry scan & test mode................................................................................................... 14 3.6 LED interface (I)................................................................................................................... 15 3.7 LED interface (II).................................................................................................................. 16 3.8 Frame priority setting pins.................................................................................................... 17 3.9 Miscellaneous setting pins (I)............................................................................................... 18 3.10 Miscellaneous setting pins (II).............................................................................................. 19 3.11 Miscellaneous setting pins (III)............................................................................................. 20 3.12 Power & ground pins............................................................................................................ 21 4 Functional Description................................................................................................................................................22 4.1 LED display (normal operation) ........................................................................................... 22 4.2 Flow control.......................................................................................................................... 22 4.3 Broadcast storm protection .................................................................................................. 22 4.4 CoS ...................................................................................................................................... 23 4.4.1 Port base priority..................................................................................................... 23 4.4.2 VIP ports ................................................................................................................. 23 4.4.3 Frame base priority ................................................................................................. 24 4.4.3.1 VLAN tag and TCP/IP TOS ........................................................................... 24 4.4.3.2 IPv4/IPv6 DiffServ ......................................................................................... 25 4.4.3.3 TCP/UDP logical port priority ........................................................................ 26 4.5 Port Mirroring ....................................................................................................................... 26 4.6 Buffer Aging.......................................................................................................................... 26 4.7 Fiber port configuration ........................................................................................................ 27 4.8 Serial management interface ............................................................................................... 28 5 Register descriptions ..................................................................................................................................................29 5.1 Register map........................................................................................................................ 29 5.1.1 EEPROM map ........................................................................................................ 29 5.1.2 MII register map ...................................................................................................... 30 5.2 PHY registers ....................................................................................................................... 32 5.2.1 Basic MII registers of port 0 .................................................................................... 32 5.2.1.1 MII control registers (address 00) ................................................................. 32 5.2.1.2 MII status registers (address 01)................................................................... 33 5.2.1.3 PHY Identifier (address 02)........................................................................... 35 5.2.1.4 PHY Identifier (address 03)........................................................................... 35 5.2.1.5 Auto-Negotiation Advertisement registers (address 04) ............................... 36 5.2.1.6 Link partner ability registers (address 05)..................................................... 37
2 / 56 Copyright ? 2007, IC Plus Corp. December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
5.2.2 Basic MII registers of port 1-7 ................................................................................. 38 5.3 Switch control registers (I) ................................................................................................... 39 5.4 Switch control registers (II) .................................................................................................. 40 5.5 Switch control registers (III) ................................................................................................. 41 5.6 Test mode control registers.................................................................................................. 42 5.7 Port mirroring control registers............................................................................................. 43 5.8 Fiber duplex setting registers............................................................................................... 44 5.9 Backpressure setting registers............................................................................................. 44 5.10 TCP/UDP port priority registers ........................................................................................... 45 5.11 CoS control registers – port 0 .............................................................................................. 46 5.12 CoS control registers – port 1 .............................................................................................. 46 5.13 CoS control registers – port 2 .............................................................................................. 46 5.14 CoS control registers – port 3 .............................................................................................. 46 5.15 CoS control registers – port 4 .............................................................................................. 47 5.16 CoS control registers – port 5 .............................................................................................. 47 5.17 CoS control registers – port 6 .............................................................................................. 47 5.18 CoS control registers – port 7 .............................................................................................. 47 5.19 Switch control registers (IV) ................................................................................................. 48 5.20 Switch control registers (V) .................................................................................................. 50 Crystal Specifications..................................................................................................................................................51 Electrical Characteristics ............................................................................................................................................52 7.1 Absolute Maximum Rating ................................................................................................... 52 7.2 DC Characteristic................................................................................................................. 52 7.3 AC Timing............................................................................................................................. 53 7.3.1 Serial Management Imierface Timing ..................................................................... 53 7.3.2 EEPROM Timing..................................................................................................... 54 7.3.2.1 Data read cycle ............................................................................................. 54 7.3.2.2 Command cycle ............................................................................................ 54 7.4 Thermal Data ....................................................................................................................... 54 Order Information........................................................................................................................................................55 Package Detail ............................................................................................................................................................56
6 7
8 9
3 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
Revision History
Revision # IP178D-DS-R01 Initial release Change Description
4 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
The difference in pin definition between IP178C/IP178CH and IP178D
IP178C/IP178CH Pin 36 53 56 57 72 73 75 76 77 78 79 80 81 84 85 86 87 96 97 100 101 104
Function Configure Typ e Function
IP178D
Configure Type
NC(IP178C) FXSD6(IP178CH) TEST1 RXCLK GND(IP178C) FXSD7(IP178CH) SPEED_LED1 RMII_MII IPL SPEED_LED0 SCA_SEL RXDV/FDX_LED7 X_EN RXD3/FDX_LED6 AGING RXD2/FDX_LED5 BCSTF RXD1/FDX_LED4 FILTER_DA RXD0/FDX_LED3 VLAN_ON TXEN LED_SEL[1] TXD3 LOW_10M_DIS/ SCA_DIS TXD2/FDX_LED2 TXD1/FDX_LED1 TXD0/FDX_LED0 LINK_LED3 LINK_LED2 LINK_LED0 TXCLK SCL FX7_EN (for IP178CH only) FX7_HALF (for IP178CH only) APS_DIS FX6_HALF (for IP178CH only) FX6_EN (for IP178CH only) P6_7_HIGH LONG_PKT_DIS MII_MAC LED_SEL[0] EXTMII_EN IPL
FXSD6 TEST1 FXSD7 SPEED_LED1
REDUCE_IPG_DIS
HIGH_PRI[2]
IPL IPH
IPH TEST2
IPL IPL IPH IPH IPL IPL IPL IPH IPH IPH
IPL SPEED_LED0 IPH FDX_LED7 IPH FDX_LED6 IPL IPL FDX_LED5 FDX_LED4
PS_MODE_0_100 X_EN AGING BCSTF FILTER_DA HIGH_PRI[1] LED_SEL[1] LED_SEL[0]
IPL FDX_LED3 IPH IPH IPH LOW_10M_DIS IPL IPL IPL IPL IPL IPL IPH IPL SCL FDX_LED2 FDX_LED1 FDX_LED0 LINK_LED3 LINK_LED2 LINK_LED0
LPP_AGING_EN (Note1) FX_HALF7 APS_DIS FX_HALF6 PORT_MIRROR0_7 (Note1) HIGH_PRI[0] LONG_PKT_DIS
IPL IPL IPL IPL IPL IPL IPH IPL
Note1: FXx_EN not require in IP178D fiber design. Please check chapter 4.6 Fiber port configuration
5 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
Features comparison between IP178C and IP178D
Function Process Switch structure Port based priority 802.1p priority Support Fiber function VLAN IP DiffServ Priority SCA (Smart Cable Analysis) Port mirroring Pins configure for port-priority Reduce IPG function
TCP/UDP port number priority
IP178C 0.18 um 8 TP + 1* MII (MII related pins: 53, 72 & 104) Yes Yes X Port base and Tag base VLAN Yes Yes No No No No No
IP178D 0.16 um 8 TP Yes Yes 2 ports with FXSD No Yes No Yes Yes Yes Yes Yes
Fiber support
6 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
1 Pin diagram
7 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
2
2.1
IP178D application diagram
An 8 TP port switch application
Here shows the application diagram of 8-port switch.
IP178D
Switch engine
MAC0 MAC1 MAC2 MAC3 MAC4 MAC5 MAC6 MAC7
PHY 0
PHY 1
PHY 2
PHY 3
PHY 4
PHY 5
PHY 6
PHY 7
TP
2.2
An 8-port switch mixed with two fiber ports
IP178D
Switch engine
MAC0 MAC1 MAC2 MAC3 MAC4 MAC5 MAC6 MAC7
PHY 0
PHY 1
PHY 2
PHY 3
PHY 4
PHY 5
PHY 6
PHY 7
TP
Fiber MAU
8 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
2.3 TCP/UDP QoS Switch for time-sensitive application from pin setting
IP178D
High Priority Port 0
Low priority Port 1
Low priority Port 2
Low priority Port3
Low priority Port 4
Low priority Port 5
Low priority Port 6
Low priority Port 7
TP
Port 0 received packet with reserved TCP/UDP port number, port 0 will enable its ingress port as a high priority port for 300 seconds. If the other ports received packets with the same reserved port number, it also has the same behavior as port 0.
2.4
Switch with VIP ports for specific users from Pin setting
IP178D
VIP Port 0
VIP Port 1
VIP Port2
Port3
Port 4
VIP Port 5
VIP Port 6
VIP Port 7
TP
Pin 53 , 79, 100 0,0,1 0,1,0 0,1,1 1,0,1 1,1,0 1,1,1
High Priority Port (VIP port) 6, 7 5,6,7 7 0,1 0,1,2 0
9 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
2.5 A 8-port Switch with Port mirror capability setting from EEPROM
IP178D
Switch engine 24C01
MAC0 MAC1 MAC2 MAC3 MAC4 MAC5 MAC6 MAC7
PHY 0
PHY 1
PHY 2
PHY 3
PHY 4
PHY 5
PHY 6
PHY 7
TP
Port 7 RX/TX traffic
Port 7 RX/TX traffic WAN
Port 1 could mirror Port 7 RX/TX traffic via EEPROM setting.
Router
10 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3 Pin description
Description Input pin Output pin Input pin with internal pull low Input pin with internal pull high Type IPL1 IPH1 IPL2 IPH2 Description Input pin with internal pull low 22.8k ohm Input pin with internal pull high 22.8k ohm Input pin with internal pull low 92.6k ohm Input pin with internal pull high 113.8k ohm
Type I O IPL IPH
3.1
52
Analog pins
Label REG_OUT Type O Regulator output voltage The internal regulator uses pin 83 / pin 92 VCC_O as reference voltage to control external transistor to generate a voltage source between 1.80v ~ 2.05v. 17 BGRES I Band gap resister It is connected to GND through a 6.19k (1%) resistor in application circuit. Description
Pin No.
115, 116, 127, 126, 2, 3, 14, 13, 22, 23, 34, 33, 38, 39, 50, 49 119, 120, 123, 122, 6, 7, 10, 9, 26, 27, 30, 29, 42, 43, 46, 45 96
RXIP0~7 RXIM0~7
I
TP receive
TXOP0~7 TXOM0~7
O
TP transmit
FX_HALF6
IPL1, O
Port 6 fiber port half duplex setting pin 1: port 6 is half duplex in fiber mode 0: port 6 is full duplex in fiber mode
86
FX_HALF7
IPL1, O
Port 7 fiber port half duplex setting pin 1: port 7 is half duplex in fiber mode 0: port 7 is full duplex in fiber mode
36
FXSD6
I
Fiber signal detection of port 6 This pin is a direct input pin for fiber signal detection
57
FXSD7
I
Fiber signal detection of port 7 This pin is a direct input pin for fiber signal detection
11 / 56 December 23, 2008 IP178D-DS-R01
Copyright ? 2007, IC Plus Corp.

IP178D
Preliminary Data Sheet
3.2 System clock & reset pins
Label OSCI Type I Description 25MHz system clock It is recommended to connect OSCI and X2 to a 25MHz crystal. If the clock source is from another chip or oscillator, the clock should be active at least for 1ms before pin 64 RESETB de-asserted. Pin 55 X2 should be left open in this application. 55 X2 O Crystal pin A 25Mhz crystal can be connected to OSCI and X2. 64 RESETB I Reset It is a low active input pad with Schmitt trigger. The reset time must be hold for more than 1 ms. If an R/C reset circuit is used, the capacitor should be connected to VCC_O as shown in the figure.
VCC_O
Pin No. 54
R RESETB C
12 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.3 EEPROM interface
Label SDA Type IPH2, O Description EEPROM serial address/data I/O After reset, it is used as data pin SDA of EEPROM. After reading EEPROM, this pin becomes an input pin. 104 SCL IPL2, O EEPROM serial clock input After reset, it is used as clock pin SCL of EEPROM. After reading EEPROM, this pin becomes an input pin. Its period is longer than 10us. IP178D stops reading the rest data in EEPROM if the first two bytes in EEPROM aren’t 55AA.
Pin No. 105
3.4
103
Serial Management Interface
Label MDC Type IPL2 Description SMI management data clock Sourced continuously from the external device that needs to access the internal registers of IP178D. The external device uses SMI interface to access the internal registers of IP178D. IP178D doesn’t access the MII registers of external PHY. 102 MDIO IPH2 ,O SMI management data input/output A bi-directional multi-drop bus for accessing the internal registers.
13 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.5 Boundry scan & test mode
Label SCAN_CLK SCAN_EN Type IPL2 IPH2 Description Boundry scan clock input Boundry scan enable To enter the scan mode, pin 53 and 56 should be pulled low at the same time with SCAN_EN is enabled. Test mode pin 5 This pin is a speed LED of port 2 after reset. 70 T_MODE_SEL[4] IPL1, O IPL1, O IPL1, O IPL1, O IPL1, O Test mode pin 4 This pin is a speed LED of port 3 after reset. 69 T_MODE_SEL[3] Test mode pin 3 This pin is a speed LED of port 4 after reset. 68 T_MODE_SEL[2] Test mode pin 2 This pin is a speed LED of port after reset. 67 T_MODE_SEL[1] Test mode pin 1 This pin is a speed LED of port 6 after reset. 66 T_MODE_SEL[0] Test mode pin 0 This pin is a speed LED of port 7 after reset.
Pin No. 103 84
71
T_MODE_SEL[5]
IPL1, O
14 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.6 LED interface (I)
Label LINK_LED[7:0] Type O Description LINK LED The detail functions are illustrated in the following table. It should be connected to VCC_O through a LED and a resistor. Application circuit
VCC_O
Pin no. 89, 90, 91, 93, 96, 97, 99, 100
R
LINK_LED
66, 67, 68, 69, 70, 71, 72, 73 75, 76, 77, 78, 79, 85, 86, 87 80, 81
SPEED_LED[7:0]
O
SPEED LED The detail functions are illustrated in the following table. It should be connected to VCC_O through a LED and a resistor.
FDX_LED[7:0]
O
FDX LED The detail functions are illustrated in the following table. It should be connected to VCC_O through a LED and a resistor.
LED_SEL[1:0]
IPH2
LED function selection The data on these pins are latched at the end of reset to select LED modes. The default value is mode 3. The detail functions are illustrated in the following table.
LED_SEL[1:0] 00
LED mode Mode 0
LINK_LED[7:0] Off: link fail On: 10 Mbps link ok Flash: TX/RX Off: link fail On: link ok Flash: RX Off: link fail On: 10 Mbps link ok Flash: TX/RX Off: link fail On: link ok Flash: TX/RX
SPEED_LED[7:0] Off: link fail On: 100 Mbps link ok Flash: TX/RX Off: 10 Mbps On: 100 Mbps Off: link fail On: 100 Mbps link ok Flash: TX/RX Off: 10 Mbps On: 100 Mbps
FDX_LED[7:0] Off: half duplex On: full duplex Off: half duplex On: full duplex Flash: collision Off: half duplex On: full duplex Flash: collision Off: half duplex On: full duplex Flash: collision
01
Mode 1
10
Mode 2
11 (default)
Mode 3
15 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.7 LED interface (II)
Label BI_COLOR Type IPL2 Description Bi-color LED mode enable 1: Bi-color mode LED enabled. LED_LINK[7:0] and LED_SPEED[7:0] are used to drive dual color LED. The functions are defined in the following table. The behavior of FDX_LED[7:0] is the same as that in mode3 on the previous page. 0: Bi-color mode LED disabled.(default) Please refer to pin description of LED_SEL[1:0] for LED functions. This pin takes precedence of LED_SEL[1:0]. Application circuit
Pin no. 95
LINK_LED
LED 1 100Mbps LINK/ACT LED 2 10Mbps LINK/ACT
SPEED_LED
Bi-color LED definition Status Link off 100 Mbps link ok 100 Mbps link ok/ activity 10 Mbps link ok 10 Mbps link ok/ activity LINK_LED[7:0] 1 1 1 0 Clock SPEED_LED[7:0] 1 0 Clock 1 1 LED 1 Off On Flash Off Off LED 2 Off Off Off On Flash
16 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.8 Frame priority setting pins
Label HIGH_PRI[0] Type IPL1, O Description Port based priority setting, bit 0 1: enable 0: disabled (default) It is an input signal during reset and its value is latched at the end of reset. It acts as a link LED of port 0 after reset. VIP port setting as follow, pin 53, 79, 100 HIGH_PRI[2:0] 001 010 011 101 110 111 99 COS_EN IPL1, O Class of service enable Packets with high priority tag are handled as high priority packets if the function is enabled. 1: enable, 0: disabled (default) It is an input signal during reset and its value is latched at the end of reset. It acts as a link LED of port 1 after reset. 85 LPP_AGING_EN IPL1, O TCP/UDP logical port priority aging enable 0: disable TCP/UDP logical port priority aging function (default) 1: enable TCP/UDP logical port priority aging function This function is valid only if pin 99 COS_EN is pulled up, It will change the ingress port behavior as a high priority port after receives the pre-defined TCP/UDP logical port priority frame and hold the ingress port as high priority for 300 seconds. LPP_AGING_EN is full duplex LED of port 2 after reset. Port based priority setting, bit 1 For the port based priority setting, reference VIP ports setting as detail. It is an input signal during reset and its value is latched at the end of reset. This pin acts as a duplex LED of port 3 after reset. 53 HIGH_PRI[2] IPL1 Port based priority setting, bit 2 For the port based priority setting, reference VIP ports setting as detail. This pin also use as a test mode setting pin when the pin 84 SCAN_EN is enabled.
17 / 56 Copyright ? 2007, IC Plus Corp. December 23, 2008 IP178D-DS-R01
Pin no. 100
high priority port number 6, 7 5, 6, 7 7 0, 1 0, 1, 2 0
79
HIGH_PRI[1]
IPL1, O

IP178D
Preliminary Data Sheet
3.9 Miscellaneous setting pins (I)
Label LONG_PKT_DIS Type IPH2 Description Max packet size option 1: Drop packets with length longer than 1536 bytes (default) 0: Drop packets with length longer than 1552 bytes 97 PORT_MIRROR_0_7 IPL1, O Mirror port 0 traffic to port 7 When enabled, the traffic (RX path) to port 0 will mirror to port 7. 1: mirror port 0 RX traffic to port 7 0: disable mirror function (default) This pin is a link LED of port 2 after reset. 93 MODBCK IPH1, O Aggressive back off enable IP178D adopts modified (aggressive) back off algorithm if this function is enabled. The maximum back off period is limited to 8-slot time. It makes IP178D have higher transmission priority in a collision event. 1: aggressive mode enable (default), 0: standard back off This pin is a link LED of port 4 after reset. 91 BF_STM_EN IPL1, O Broadcast storm enable 1: enable 0: disable (default) A port begins to drop packets if it receives broadcast packets more than the threshold defined in MII register 31.9[15:14] BQ_STM_THR_SEL [1:0] or EEPROM register 83[7:6]. This pin is a link LED of port 5 after reset. 90 MDI_MDIX_EN IPH1, O MDI/MDI-X enable MDI/MDI-X auto cross over 1: enable (default) 0: disable It is an input signal during reset and its value is latched at the end of reset to set auto MDI/MDIX function. This pin is a link LED of port 6 after reset. 89 MLT3_DET IPL1, O Ability for detecting MLT3 (for 10 Mbps switch to 100 Mbps) 1: enable MLT3 detection ability 0: disable MLT3 detection ability (default) MLT3_DET is link LED of port 7 after reset.
Pin no. 101
18 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.10 Miscellaneous setting pins (II)
Label APS_DIS Type IPL1, O Description Disable advance power saving mode 1: disable advance power saving mode 0: enable advance power saving mode (default) APS_DIS is full duplex LED of port 0 after reset. 84 LOW_10M_DIS IPH2 LOW_10M_DIS 1: disable power saving mode. (default) 0: enable power saving mode 79
PORT_MIRROR0_7
Pin no. 87
IPL1, O
Mirror port 0 traffic to port 7 Mirror the ingress and egress traffic to port 7. To reduce the traffic congestion at port 7, do not use it as a normal operation port. 1: enable 0: disable (default) This pin is a duplex LED of port 3 after reset. Reserved address forward option Filter packets with specific DA (Destination Address) from 01:80:C2:00:00:02 to 01:80:C2:00:00:0F. Packets with specific DA equal to 01:80:C2:00:00:01 are always filtered regardless the setting of this pin. 1: filter 0: forward (default) This pin is a duplex LED of port 4 after reset.
78
FILTER_DA
IPL1, O
77
BCSTF
IPL1, O
Broadcast frame option 1: Packets with DA equal to FF:FF:FF:FF:FF:FF are handled as broadcast frame in broadcast protection function, 0: Packets with DA equal to FF:FF:FF:FF:FF:FF or multi-cast frames are handled as broadcast frame in broadcast protection function. This pin is a duplex LED of port 5 after reset.
76
AGING
IPH1, O
Aging enable 1: enable 300s aging timer (default) 0: disable aging function This pin is a duplex LED of port 6 after reset.
19 / 56 Copyright ? 2007, IC Plus Corp.
December 23, 2008 IP178D-DS-R01

IP178D
Preliminary Data Sheet
3.11 Miscellaneous setting pins (III)
Label X_EN Type IPH1, O Description Flow control enable 1: enable IEEE802.3x & back pressure (default) 0: disable IEEE802.3x & back pressure The function is valid only if pin 53 is pulled low. This pin is a duplex LED of port 7 after reset. 73 PS_MODE_0_100 IPL1, O Power saving mode 1: power saving mode for 0 to 100 mA 0: power saving mode for 40 to 100 mA (default) This pin is a speed LED of port 0 after reset. 72 REDUCE_IPG_DIS IPL1, O Reduce IPG function This function reduce the IPG by random from 0 ~ 20 PPM. 1: disable reduce IPG function 0: enable reduce IPG function This pin is a speed LED of port 1 after reset.
Pin no. 75
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December 23, 2008 IP178D-DS-R01

IC-HK_datasheet

Rev 21.11.01, Page 1/13 current of 100mA pulse current of 100mA Fig. 2: Signal patterns for Example 1 -pulse current of 100mA APPLICATION NOTES Setting the laser current When switching DC currents of up to 150mA or pulse currents of up to 700mA one channel is sufficient (Example 1). Input ENx of the unused channel should be jumpered to GND and pin AGNDx left open. Higher currents or several different current levels can be obtained by using both channels (Example 2 and 3).Example 1:Switching a current of 100mA 1. 100mA < 150mA | one channel 2. Switching on and off only | RK can be omitted (RK = 0S ) 3. As shown in Figure 1 (cf. data sheet, Figures 2..4), the required voltage V(CI) for RK = 0S is read off at I(LDK) = 100mA as V(CI) =1.75V With the circuit shown in Figure 3 and a voltage of 1.75V at pin CI the laser current can be switched between typically 0mA and 100mA by applying an appropriate pulse pattern to EN1.

英飞凌控制芯片-适合变频器

英飞凌MCU介绍英飞凌MCU包含8、16、32位处理器，其中16位XE167系列和32位TC11xx系列芯片在工业控制应用最为广泛。特别是32位TC11xx系列芯片在实现变流技术，特别是特殊工作环境的变流产品有一定的优势。相比TI的控制芯片，英飞凌的同类型产品配置相对高一些，片内资源更丰富，但横向产品线不如TI。其次，英飞凌芯片的供货周期应该不如TI紧张。

英飞凌XE166系列芯片 MCU and DSP in a Real Time Core Real Time Signal Controller XE166主要应用于电源、工业水泵、步进电机、空调压缩机与鼓风机等对象。主要指标：运算速度最高可达100MIPS，片内Flash从128KB到1600KB，内部RAM 从34 KB到138 KB，内部AD转换速度600ns，最高内置4个捕获单元，PWM输出单元2到4个。其中classic为5线JTAG设计，其余为2线JTAG设计。 XE166系列有四类产品（全为P/PG-LQFP封装）：各类参数：

英飞凌TC11xx系列芯片英飞凌TC11xx系列32位芯片主要应用于工业和其它各种市场。应用对象为高性能伺服驱动器、高性能逆变器控制（如可再生能源系统）、处于恶劣环境的太阳能和风力发电逆变器、机器人、移动控制器等。是适合用于变频器上的控制芯片。主要指标：该系列的芯片能实现多轴控制，能输出两对独立的三相互补控制PWM波形、能实现分别对两台电机控制、同时支持多种调制策略(SVPWM, DPWM, Soft-PWM, DTC)、可实现多电平和矩阵变换器控制、在矢量控制时其芯片资源占有率不到百分之十、其芯片最高主频可达180Mhz（最低80Mhz）、片内Flash最高达4M(最低1M)，内部RAM最高达224 KB（最低76KB）、片内包含AD和高速AD模块。该系列包含五个类的产品（全部为BGA封装）：

芯片数据手册Datasheet热门问题

芯片数据手册Datasheet热门问题 ?如何正确的阅读Datasheet？不仅仅是芯片，包括工具、设备几乎任何电子产品，都需要去阅读它的datasheet，除了包括最低、最高要求，特点，建议和用途及其兼容的设备等等，更重要的是原厂商以一个成功者的身份去告诉你一些注意事项。 Datasheet一般组成的字段：（LM317举例） ①日期：首先检查发布日期，是预备版还是修正版 ②厂商：检查厂商，因为相同型号不同厂商的器件，性能或许不同 ③描述（Description）：往往会告诉你一些一般地方没有提到的功能或者用法。比如：你可能需要保持一个特殊的引脚为低电平才能完成某个操作。 ④特点（Features）：告诉你常规特征。确认电器特征相应的条件 ⑤应用（Application）：通常简洁的告诉你该器件是否在你的应用领域；如果这个芯片有你需要的功能，它可以给予你很好的提示。但是这里给出的功能往往都是很一般（常用）的功能 ⑥封装图：不同的封装引脚的位置一般不同，但引脚的总是一般是相同的，需要注意不同位置的引脚及其每个引脚的功能 ⑦性能坐标图：通常描述电流测量与电压的变化曲线，通常会标明25℃（室温） ⑧电气特性表格：通常是芯片参数-条件-变化范围的表格，即相同参数条件不同，输出范围在Min-Typ-Max 之间 ?是不是所有芯片都有Datasheet？理论上所有芯片都有它对应的datasheet，但是有些芯片是属于定制器件，例如：手机、PC、PAD里面的芯片。往往原厂商只公开它的一般描述、一般特点、一般应用，少许的会公开参数，所以像这样的datasheet 我们正常是拿不到的，这就是为什么有时候一款芯片我们翻江倒海，翻山越岭也没找到的原因了，不过也有些芯片可以通过向原厂商提交申请，审核通过后会提供给你。 ?职业不同如何避轻就重去读Datasheet？当我们用到datasheet时，有时候没必要从头读到尾，那样会花费大量的时间。Datasheet中涉及到芯片的方方面面，硬件、软件、工艺、制程技术、封装等等，学会抓住关键字词，了解我们所需要的信息，比如：我们想了解AO4459这款P沟道场效应MOSFET ①如果咱们是做硬件，需主要关注Drain-Source Voltage（漏源电压）, Gate-Source Voltage（门源电压）, Continuous Drain Current（连续漏电流），Pulsed Drain Current（漏电流脉冲）等等，能够看懂热特性曲线图（TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS）；

Infineon_TLE4675-电源芯片

Data Sheet, Rev. 1.0, Sept. 2008 TLE4675 Low Drop Out Linear Voltage Regulator 5V Fixed Output Voltage Automotive Power

TLE4675 Table of Contents Table of Contents Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1Pin Assignment TLE4675D (PG-TO252-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2Pin Definitions and Functions TLE4675D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3Pin Assignment TLE4675G (PG-TO263-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4Pin Definitions and Functions TLE4675G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1Description Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2Electrical Characteristics Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3Typical Performance Characteristics Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1Electrical Characteristics Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2Typical Performance Characteristics Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1Description Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2Electrical Characteristics Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3Typical Performance Characteristics Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1PG-TO252-5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.2PG-TO263-5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

如何看datasheet+8页(绝对有用)

How to Read a Datasheet Prepared for the WIMS outreach program 5/6/02, D. Grover In order to use a PIC microcontroller, a flip-flop, a photodetector, or practically any electronic device, you need to consult a datasheet. This is the to. Where do you find datasheets? Nowadays you can find almost any datasheet on the internet, often in PDF (Acrobat) form. For example, the LM555 datasheet from National Semiconductor is on their website at https://www.360docs.net/doc/4314754114.html,.

LM555Timer General Description The LM555is a highly stable device for generating accurate time delays or oscillation.Additional terminals are provided for triggering or resetting if desired.In the time delay mode of operation,the time is precisely controlled by one external re-sistor and capacitor.For astable operation as an oscillator,the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor.The circuit may be triggered and reset on falling waveforms,and the output circuit can source or sink up to 200mA or drive TTL circuits. Features n Direct n Timing n Operates n Adjustable n Output n Output n Temperature n Normally n Available Applications n Precision n Pulse n Sequential DS007851-1 有时常规描述（General Description ）会给出一些其它地方没提到的特性或者用法。特性（确认电气特性所在的条件以及特殊情况。通常叫做等效原理图，该原理不是该芯片中必须的，但是该芯片将按照里面的来运作。它能帮助解释在数据手册中未被描述的行为。能把这个电路在面包板上搭出来吗？除非您知道那些并未给出参数的晶体管的参数。总会有一个日期。数据手册变动，尤其是预备版或者修正版，核对一下日期。

英飞凌各代IGBT模块技术详解

英飞凌各代IGBT模块技术详解 IGBT 是绝缘门极双极型晶体管（Isolated Gate Bipolar Transistor）的英文缩写。它是八十年代末，九十年代初迅速发展起来的新型复合器件。由于它将 MOSFET 和 GTR 的优点集于一身，既有输入阻抗高，速度快，热稳定性好，电压驱动（MOSFET 的优点，克服 GTR 缺点）；又具有通态压降低，可以向高电压、大电流方向发展（GTR 的优点，克服 MOSFET 的缺点）等综合优点，因此 IGBT 发展很快，在开关频率大于 1KHz，功率大于 5KW 的应用场合具有优势。随着以 MOSFET、IGBT 为代表的电压控制型器件的出现，电力电子技术便从低频迅速迈入了高频电力电子阶段，并使电力电子技术发展得更加丰富，同时为高效节能、省材、新能源、自动化及智能化提供了新的机遇。英飞凌／EUPEC IGBT 芯片发展经历了三代，下面将具体介绍。一、IGBT1－平面栅穿通（PT）型 IGBT （1988 1995）西门子第一代 IGBT 芯片也是采用平面栅、PT 型 IGBT 工艺，这是最初的 IGBT 概念原型产品。生产时间是 1990 年－ 1995 年。西门子第一代 IGBT 以后缀为“DN1” 来区分。如 BSM150GB120DN1。图 1.1 PT-IGBT 结构图 PT 型 IGBT 是在厚度约为 300－500μm 的硅衬底上外延生长有源层，在外延层上制作IGBT 元胞。PT-IGBT 具有类 GTR 特性，在向 1200V 以上高压方向发展时，遇到了高阻、

厚外延难度大、成本高、可靠性较低的障碍。因此，PT-IGBT 适合生产低压器件，600V 系列 IGBT 有优势。二、IGBT2－第二代平面栅 NPT-IGBT 西门子公司经过了潜心研究，于 1989 年在 IEEE 功率电子专家会议（PESC）上率先提出了 NPT－IGBT 概念。由于随着 IGBT 耐压的提高，如电压VCE≥1200V，要求 IGBT 承受耐压的基区厚度dB>100μm，在硅衬底上外延生长高阻厚外延的做法，不仅成本高，而且外延层的掺杂浓度和外延层的均匀性都难以保证。1995 年，西门子率先不用外延工艺，采用区熔单晶硅批量生产 NPT－IGBT 产品。西门子的 NPT-IGBT 在全电流工作区范围内具有饱和压降正温度系数，具有类 MOSFET 的输出特性。图 1.2 NPT-IGBT 结构图西门子／EUPEC IGBT2 最典型的代表是后缀为“DN2”系列。如 BSM200GB120DN2。“DN2”系列最佳适用频率为 15KHz－20KHz，饱和压降 VCE(sat)=2.5V。“DN2”系列几乎适用于所有的应用领域。西门子在“DN2”系列的基础上通过优化工艺，开发出“DLC”系列。“ DLC ” 系列是低饱和压降，（ VCE(sat)=2.1V ），最佳开关频率范围为 1KHz － 8KHz 。“DLC”系列是适用于变频器等频率较低的应用场合。后来 Infineon／EUPEC 又推出短拖尾电流、高频“KS4”系列。“KS4”系列是在“DN2”的基础上，开关频率得到进一步提高，最佳使用开关频率为 15KHz－30KHz。最适合于逆变焊机，UPS，通信电源，开关电源，感应加热等开关频率比较高（fK≥20KHz）的应用场合。在这些应用领域，将逐步取代“DN2”系列。EUPEC 用“KS4”芯片开发出H—桥（四单元）IGBT 模块，其特征是内部封装电感低，成本低，可直接焊在 PCB 版上（注：这种结构在变频器应用中早已成熟，并大量使用）。总之，EUPEC IGBT 模块中“DN2”、“DLC”、“KS4”采用 NPT 工艺，平面栅结构，是第二代 NPT-IGBT。

常用的十大电子元器件Datasheet

常用的十大电子元器件Datasheet 元器件数据表（datasheet）是电子工程师项目开发时经常使用到的手册。Datasheet（数据手册）包含了电子芯片的各项参数，电性参数，物理参数，甚至制造材料，使用建议等，一般由厂家编写，内容形式一般为说明文字，各种特性曲线，图表，数据表等。下面介绍一下常用的十大电子元件： 1、DS18B20温度传感器273W百度收录总数常用指数：★★★★★ DS18B20是Dallas公司生产的数字温度传感器，具有体积小、适用电压宽、经济灵活的特点。它内部使用了onboard专利技术，全部传感元件及转换电路集成在一个形如三极管的集成电路内。DS18B20有电源线、地线及数据线3根引脚线，工作电压范围为3～5.5 V ，支持单总线接口。免费下载：DS18B20 2、TL431可控精密稳压源244W 常用指数：★★★★ TL431是由德州仪器生产，所谓TL431就是一个有良好的热稳定性能的三端可调分流基准源。它的输出电压用两个电阻就可以任意地设置到从Vref(2.5V)到36V范围内的任何值(如图1)。该器件的典型动态阻抗为0.2Ω，在很多应用中可以用它代替齐纳二极管，例如，数字电压表，运放电路、可调压电源，开关电源等等。免费下载：TL431

LM358双运算放大器238W 常用指数：★★★★ LM358双运算放大器，适合于电源电压范围很宽的单电源使用，也适用于双电源工作模式，在推荐的工作条件下，电源电流与电源电压无关。它的使用范围包括传感放大器、直流增益模块和其他所有可用单电源供电的使用运算放大器的场合。免费下载：LM358 4、LM324四路运算放大器236W 常用指数：★★★★ LM324系列是低成本的四路运算放大器，具有真正的差分输入。在单电源应用中，它们与标准运算放大器类型相比具有几个明显的优势。该四路放大器可以工作于低至3.0 V或高达32 V的电源电压，静态电流是MC1741的五分之一左右（每个放大器）。共模输入范围包括负电源，因此在众多应用中无需外部偏置元器件。输出电压范围也包括负电源电压。免费下载：LM324 5、DAC0832数模转换芯片157W 常用指数：★★★ DAC0832是8分辨率的D/A转换集成芯片。与微处理器完全兼容。这个DA芯片以其价格低廉、接口简单、转换控制容易等优点，在单片机应用系统中得到广泛的应用。D/A转换器由8位输入锁存器、8位DAC寄存器、8位D/A转换电路及转换控制电路构成。免费下载：DAC0832

IP178D 芯片datasheet

关于英飞凌IGBT模块的选型

关于英飞凌IGBT模块的选型英飞凌IGBT模块的型号：电压规格：直流母线/电网电压 IGBT电压规格 300V DC (max. appr. 450V DC) 600 V 600V DC (max. appr. 900V DC) 1200 V 750V DC (max. appr. 1100V DC) 1700 V upt to 1300V DC controlled 2500 V 1500V DC (max. appr. 2100V DC) 3.3 kV (or2x 1700 V in series/3-level) up to 2500V DC controlled 4.5 kV 3000V DC (max. ca. 4500V DC) 6.5 kV (or2 x 3.3 kV in series/3-level) 2.3kV AC (≈3.3kV DC) 同上 4.16kV AC (≈ 5.9kV DC) 6.5 kV in series/3-level 6.6kV AC (≈9.4kV DC) multi-level

Datasheet RBSOA：宇宙射线会导致IGBT/FWD的失效，失效率（FIT）和直流母线电压有关、海拔高度、结温有关。

Example: 1700V IGBT Module FIT vsDC-link Voltage 宇宙射线，FIT随海拔高度而倍增。电流规格：

电路形式：形式越完整，性价比越高，功率密度也越高；并联的优点：功率密度低，基板温度（壳温）波动小模块封装： Thermal Simulation Results

ALLDATASHEET

ALLDATASHEET是全球电子元器件数据手册库，在这里你可以搜索到近两千万个电子元器件型号的数据。万联芯城是国内知名的电子元器件采购网，专为客户提供一站式电子元器件配单服务，所售电子元器件均为原装现货，满足客户所有物料需求。点击进入万联芯城点击进入万联芯城

ALLDATASHEET是全球电子元器件数据手册库，提供了近2000万个元器件型号的PDF数据手册，声称“如果在本站没有找到，那么别的地方不可能再有”。ALLDATASHEET强大的资源搜集能力让它成为电子工程师的必备网站，在这里他们可以找到他们想要的一切资料，并完成他们的研发。 ALLDATASHEET每一份数据手册对应的型号出自其原厂，不管是固件工程师、硬件研发人员亦或者板子维修员，想要用最快、最省时间的方法去了解一个芯片，那么，无疑是从ALLDATASHEET去寻找。ALLDATASHEET内的芯片手册，会因为从事的行业不同，而关注不同的点。当然，如果你还没正式工作，只是一名学生的话，这本科技英语非常的适合你阅读。一般ALLDATASHEET会先从芯片特性到应用场合，最后到内部框架去了解。当然，这里所指的了解是宏观的，对于芯片这种注重细节的物件，微观上才是让我们兴奋的点。芯片参数、管脚定义、内部寄存器任何一个都要研究透彻。连手册中的注意部分都不要放过。我更偏向于将你们所称谓的ALLDATASHEET当作是一个说明书来读，一般的芯片指导书太过拗口，而说明书为了让使用者看懂，除了专业词汇，都尽量的使用了通俗易懂的语句。尽管如此，想要看懂一个元

器件厂商所写的数据手册，首先你还是要具备一定的英语、电气技术(电子技术、电气)、微机原理技能。一个不懂OC的人是无法看懂数据手册的。假设，你在犹豫入手某一块MOS管芯片，你在ALLDATASHEET下载好对应的数据手册后，首先，要浏览的是简介!很多人以为简介只是介绍厂家信息及芯片数据，从简介中你能够知道该芯片功能及应用范围，包括输入输出的电流电压、功率大小、工作温度等。MOS管芯片一般涉及电源及驱动，也就是电气特性，你需要从手册中了解这方面的信息，看是否符合你所使用的范围，这些在ALLDATASHEET网站中都能帮到你。

NK510超外差接收芯片Datasheet

NK51 产品特征 ● 300MHz 到440MHz 的频率范围 ● 工作电压：2.2V-3.6V ● 接受灵敏度高：-110dBm ● 数据传输速率达10kbps （固定模式） ● 低功耗 ? 315MHz 下，最大工作电流2mA 433MHZ 下，最大工作电流2.5mA ? 关闭时的电流为0.9uA ? 扫描操作时（10：1任务周期操作）电流为300uA ● 唤醒输出标记用来启动解码器和微处理器 ● 天线处的射频辐射非常低 ● 集成度高，外部器件需求少应用领域 ● 汽车远程无钥匙进入（RKE ） ● 远程控制 ● 远程风扇和电灯控制 ● 车库门和门禁控制 0是一个ASK/OOK （开关键控）的单晶片射频接收集成电路设备。它是一个真正的“从天线接收到数据输出”的单片电路。所有的射频和中频的调谐都在集成电路里完成，这样可以无须手动调整并且降低成本。实现了一个高度可靠且低成本的解决方案。是一个采用16引脚封装且功能齐全的芯片，A/B/C/DL 采用了8引脚封装，功能稍有减少。提供了两种附加的功能，（1）一个关闭引脚，在任务周期操作时可以用来关闭设备；（2）一个唤醒输出引脚，当接收到射频信号时，它可以提供一个输出标记。这些特点使得可以用在低功耗的应用上，比如RKE 和远程控制。上提供了所有的中频滤波和数据解调滤波器，所以，不需要外部的滤波器了。四个解调滤波器的带宽可以由用户从外部控制。提供了两种工作模式：固定模式（FIX ）和扫描模式（SWP ）。在固定模式中，用作传统的超外差接收器。在扫描模式下，在一个较宽的射频范围内进行扫描。固定模式提供了更有选择性和针对性的工作模式，并且使得可以与低成本，精确度较低的发射器一起使用。 NK51 0 NK51 0NK51 0NK51 0NK51 0NK51 0NK51 0NK51 0NK51 0NK51 0

降压稳压芯片LSP5502DATASHEET

PIN ASSIGNMENT SS EN COMP FB BS IN SW GND SOP-8L PIN DESCRIPTION Name No. Description BS 1 Bootstrap. This pin acts as the positive rail for the high-side switch’s gate driver. Connect a 0.01uF capacitor between BS and SW. IN 2 Input Supply. Bypass this pin to G with a low ESR capacitor. See Input Capacitor in the Application Information section. SW 3 Switch Output. Connect this pin to the switching end of the inductor. GND 4 Ground. FB 5 Feedback Input. The voltage at this pin is regulated to 0.925V. Connect to the resistor divider between output and ground to set output voltage. COMP 6 Compensation Pin. See Stability Compensation in the Application Information section. EN 7 Enable Input. When higher than 2.5V, this pin turns the IC on. When lower than 1.3V, this pin turns the IC off. Output voltage is discharged when the IC is off. This pin should not be left open. SS 8 Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 15ms. To disable the soft-start feature, leave SS unconnected. TYPICAL APPLICATION Distributed Power Systems Networking Systems FPGA, DSP, ASIC Power Supplies Green Electronics/ Appliances Notebook Computers GENERAL DESCRIPTION The LSP5502 is a monolithic synchronous buck regulator. The device integrates 120m ? MOSFETS that provide 2A continuous load current over a wide operating input voltage of 4.5V to 27V. Current mode control provides fast transient response and cycle-by-cycle current limit. An adjustable soft-start prevents inrush current at turn on. In shutdown mode, the supply current drops below 1μA. This device, available in an 8-pin SOP package,provides a very compact system solution with minimal reliance on external components. FEATURES 2A Output Current Wide 4.5V to 27V Operating Input Range Integrated 120m ? Power MOSFET Switches Output Adjustable from 0.925V to 24V Up to 96% Efficiency Programmable Soft-Start Stable with Low ESR Ceramic Output Capacitors Fixed 400KHz Frequency Cycle-by-Cycle Over Current Protection Input Under Voltage Lockout 8-Pin SOP Package

UC3863 datasheet 芯片资料

UC1861-1868UC2861-2868UC3861-3868 FEATURES ?Controls Zero Current Switched (ZCS)or Zero Voltage Switched (ZVS)Quasi-Resonant Converters ?Zero-Crossing Terminated One-Shot Timer ?Precision 1%, Soft-Started 5V Reference ?Programmable Restart Delay Following Fault ?Voltage-Controlled Oscillator (VCO) with Programmable Minimum and Maximum Frequencies from 10kHz to 1MHz ?Low Start-Up Current (150μA typical) ?Dual 1 Amp Peak FET Drivers ?UVLO Option for Off-Line or DC/DC Applications DESCRIPTION The UC1861-1868family of ICs is optimized for the control of Zero Current Switched and Zero Voltage Switched quasi-resonant converters.Differ-ences between members of this device family result from the various com-binations of UVLO thresholds and output options.Additionally,the one-shot pulse steering logic is configured to program either on-time for ZCS systems (UC1865-1868),or off-time for ZVS applications (UC1861-1864).The primary control blocks implemented include an error amplifier to com-pensate the overall system loop and to drive a voltage controlled oscillator (VCO),featuring programmable minimum and maximum frequencies.Trig-gered by the VCO,the one-shot generates pulses of a programmed maxi-mum width,which can be modulated by the Zero Detection comparator.This circuit facilitates “true”zero current or voltage switching over various line,load,and temperature changes,and is also able to accommodate the resonant components' initial tolerances. Under-Voltage Lockout is incorporated to facilitate safe starts upon power-up.The supply current during the under-voltage lockout period is typically less than 150μA,and the outputs are actively forced to the low state. (continued)BLOCK DIAGRAM Resonant-Mode Power Supply Controllers Device 18611862186318641865186618671868UVLO 16.5/10.516.5/10.5360143601416.5/10.516.5/10.53601436014Outputs Alternating Parallel Alternating Parallel Alternating Parallel Alternating Parallel “Fixed” Off Time Off Time Off Time Off Time On Time On Time On Time On Time