第十三章数模混合IP

《SoC设计方法与实现》
郭炜 郭筝 谢憬
第十三章
数模混合IP的设计与集成
Outlines
• Mixed-signal design or IP in SoC • Mixed-signal design flow • The mixed-signal design key for SoC • The Mixed-signal verification in SoC
VDAC
2
2R
DN 2
2R
D N 3 DN 4
2R
D3
……
V
) N 2 0D 1 N 2 1D
R R R 2R 2R
D2
• Newton Division • R-2R network
VDAC
2 2 2 ND 1 2 1 ND ( FERV
end of conversion
The General Structure of SAR ADC
dout_reg[5:0] VDDD VSSD pd
soc_digatal clk comp_sar soc reset eoc soc_analog
Pat Generator
pat_start
Control Logic
ADC General Usage
• To convert the analog voltage or
current value into digital codes • For battery power capacitance detection • For key-board press detection • Etc.
May enlarge the chip size Increase process complexity Noise isolation carefully
Mixed-signal design for SoC
• The normal designdesign or IP in SoC The mixed-signal or IP

• SDF from PT • Post simulation in VCS, etc.
Parasitic resistance and capacitance value Parasitic resistance and capacitance location Cell level, cell view
2R
D1
2R
D0
SA ADC Specification
• Successive approximation algorithm • 6 bits converter data output • Two analog input selection • Low power with power down switch • Internal reference voltage generator • The flags of start of conversion and
Advantages:

Limits:


Enlarge the system size, not chip size More bad effect from parasitic in PCB between two parts More difficulties in the consideration on IO pads, driving and load
Schematic Design & Hspice Netlist Simulation Digital Design Flow Layout & Verification
Layout Integration
Post Simulation in Transistor Level
How SA ADC Function?
• Compare MSB first, then down to LSB • Example: 3-bit Successive approximation
Key Algorithm Implementation
VREF N ( D N 1 2 N 1 R D N 2 2 N 2 R 2 R D1 2 R D0 R)
limited area specific pin direction assignment Power ground ring
ADC Digital Part Layout Result
Parasitic Extraction
• For post simulation with SDF file • SPEF files generated
ADC Digital Part Backend Design
• Synthesis with Design Compiler • Floorplan

• CTS • Routing • LVS & DRC • Final netlist generated, Verilog gate
level view
Analog Design
• Making the circuit
schematics • Standard alone simulation with netlist written in Spice with Hspice to check the function and performance
The General Structure of SAR ADC
dout_reg[5:0] VDDD VSSD pd
soc_digatal clk comp_sar soc reset eoc soc_analog
Pat Generator
pat_start
Control Logic
ims
SAR
B5~~B0 D5~~D0
• Some function cannot be implemented by
ONLY digital principle!!!
vi (t )
PD LF VCO
vo (t )
Porgrammable Devider
The conventional mixed-signal design operation
Conventional Mixed Signal Design Approach
Whole-chip Specification
Digital and Analog Module Definition Digital Sub-module Definition Analog Blocks Definition

• The parts’ respective function

PLL ADC
Digital: Controlling logic and simple algorithm Analog: Communicating with external analog signal and dealing with the voltage outside the digital value margin
ADC Analog Part Design
• Blocks Definition





Analog Input Mux Analog voltage input selection Sample-hold Analog sampling and voltage holding Reference Operator Standard reference voltage generator, bandgap bias generator for PMOS DAC Digital to analog converter, R-2R resistance network Comparator Comparing the sampled VIN with Vref from DAC
Agenda
• Mixed-signal design or IP in SoC • Mixed-signal design flow • The mixed-signal design key for SoC • The Mixed-signal verification in SoC

A 6-bit SA ADC Design
ims
SAR
B5~~B0 D5~~D0
6 Bit Shifter
comp
Level Shift
comp D5~~D0 VREF
Comparator
DAC_vref VIN_Sampled
DAC
Reference Operator
Smaple-Hold
VIN soc_analog
Analog Input Mux
Mixed-signal design for SoC
• Digital and analog parts integrated in
ONE chip • Benefits:


• Limits:

Reduce the system size Reduce the consideration on parasitic on PCB Reduce the IO driving currents and parasitic loads
Agenda
• Mixed-signal design or IP in SoC • Mixed-signal design flow • The mixed-signal design key for SoC • The Mixed-signal verification in SoC