PowerCompiler_2010

Gate-level Power Optimization Clock Gating
Synopsys 10-I-061-SG-007© 2005 Synopsys, Inc. All Rights Reserved
6
Unit Objectives
After completing this unit, you should be able to
Isht Iintsw
N
Isht Isw
Cint
Gnd N
Out

Internal power (dynamic):

Ileak
Ileak
Cload
Gnd

Leakage power (static):

Vdd
In
Out
Cload
Gnd
Internal power != Short Circuit Power

Recognize power information in library Evaluate the quality of a library Calculate power manually at gate-level
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Low Power Methodology

Modeling:
} pin(clk) { …... internal_power() { rise_power(trans_time) { values( “0.55, 0.6, 0.7”); } } .........
Unit
Templates
Internal Power Tables
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Leakage Power In Library

Unit of C, V The “nom_voltage” used as default voltage “power_supply” defines multiple voltages used in the library Input pin capacitance is part of the driving cell’s output load “output_signal_level” specifies voltage used for computing switching power
Cell
4 toggles 40ns


Toggle rate (Tr) is Toggles / time Dynamic power equals to energy times toggle rate P(dyn) = E(toggle) * Tr Power analysis needs toggle on every node

The infrastructure for power management Library models for ASIC design Provides visibility into power consumption Required at all levels of abstraction Based on scenario simulation Reduces power consumption at all levels of abstraction
Vdd2
Default leakage
leakage_power() { power_level } leakage_power() { power_level VDD2 ; value : 6.332 ; } leakage_power() { power_level VDD1 ; when : "!A1 A2" ; value : 4.792 ; } leakage_power() { power_level VDD2 ; when : “!A1 A2" ; value : 5.176 ; } VDD1 ; value : 3.459 ;
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Calculate Cell Power

Switch Power:

Dependent on output load and input transition Pre-processed by characterization tools Stored in library power lookup tables SDPD (state dependent path dependent) Pre-processed by characterization tools Stored in library SD (state dependent)
library (power) { ...... leakage_power_unit : 1pW; default_cell_leakage_power : k_volt_cell_leakage_power : k_temp_cell_leakage_power : k_process_cell_leakage_power ....... cell (AN2) { area : 2.0; cell_leakage_power : 0.5678; leakage_power() { when : "!A & !B" ; value : 0.0175811 ; } leakage_power() { when : "!A & B" ; value : 0.0184178 ; }
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Toggle Rate Based Average Power Analysis

Digital circuit consumes dynamic energy E(toggle) for each toggle 4 toggles consumes energy E(dyn) = E(toggle) * 4
3
Agenda
DAY 1
1 2 3 4 5
Power Modeling Design-Compiler Overview Power Analysis
Gate-level Power Optimization Clock Gating
Synopsys 10-I-061-BSG-007
© 2005 Synopsys, Inc. All Rights Reserved
Power Compiler
Synopsys Customer Education Services
© 2010 Synopsys, Inc. All Rights Reserved Synopsys 10-I-061-BSG-007
1
Workshop Goal
Acquire basic skills to analyze and optimize for power using Synopsys Power Compiler.
4
Icons Used In This Workshop
Hint, tip or suggestion Additional information
Caution or warning
5
Agenda
DAY 1
1 2 3 4 5
Power Modeling Design-Compiler Overview Power Analysis
2
Workshop Prerequisites

Understanding of digital IC design Working knowledge of Design Compiler Knowledge of Verilog simulation Familiar with LINUX environment



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Internal Power In Library
library (power) { ........ voltage_unit : “1V” capacitive_load_unit(1,pf); ........ power_lut_template(load_trans) { variable_1 : total_output_net_capacitance; variable_2 : input_transition_time; index_1 ( “0.1, 5.0, 6.0”); index_2 ( “0.1, 3.0, 7.0, 15.0, 20.0”); } power_lut_template(load_only) { variable_1 : total_output_net_capacitance; index_1 ( “0.0, 5.0, 10.0”); } power_lut_template(trans_time) { variable_1 : input_transition_time; index_1 ( “0.0, 3.0, 20.0”); }
values ("1.934150, 2.148130"); } } internal_power() { power_level : VDD2 ; power (power_rl) { values ("1.032871, 0.823947");
States must be identical for different rails

Analysis:


Optimization:

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Power Model
CMOS cell power model

Vdd P In Vdd P
Switch power (dynamic):

Charging output load Short circuit; Charging internal load Stable state