ds_m368l6423bt1

< page 8, 9>
13. Changed AC parameters as follows. Parameter tDQSQ tDV from +/- 0.5(PC266), +/- 0.6(PC200) +/- 0.35tCK to +0.5(PC266), +0.6(PC200) Removed Comments
Revision 1.0 December. 2001
Rev. 1.0 Dec. 2001
M368L6423BT1
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Revision 0.7 (October. 2000)
1.Added DC target spec values. 2.Deleted tDAL in AC parameter X.
184pin Unbuffered DDR SDRAM MODULE
Revision 0.8 (November. 2000)
tPRE *1 tRPST tHZQ
*1 *1 *1
: Changed description method for the same functionality. This means no difference from the previous version. From tDQCK To tAC
< Page 5>
9. Changed Power & DC operating condition. From Min
1.15 V REF+0.18 -0.3 -5 -15.2 15.2
Parameter
I/O Reference voltage Input logic high voltage Input logic low voltage Input leakage current Output High Current (V OUT = 1.95V) Output Low Current (V OUT = 0.35V)
Revision 0.5 (April. 2000)
1. Changed from A-die to B-die.
Revision 0.6 (June. 2000)
1. Changed PCB version from T0 to T1.
Rev. 1.0 Dec. 2001
M368L6423BT1
M368L6423BT1
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM 64-bit Non-ECC/Parity
3.Changed the following AC parameter symbol Output data access time from CK/CK
Revision 0.2 (Sept. 1999)
1. Changed the odering information. 1-1. Exclude KM mark. From KMM368... 1-2. PCB Revison From - Blank: 1st generation -A : 2nd generation -B : 2nd generation Example:KMM368L6423AT 1-3. Modified binning policy From - 0 (100Mhz/200Mbps@CL=2) - Z (133Mhz/266Mbps@CL=2) - Y (133Mhz/266Mbps@CL=2.5)
14. Added AC parameters as follows
Parameter Symbol -A2(PC266@CL=2) Min tHPmin -0.75ns tCLmin or tCHmin 0.9 0.4 Max -B0(PC266@CL=2.5) Min tHPmin -0.75ns tCLmin or tCHmin 0.9 0.4 Max -A0(PC200@CL=2) Min tHPmin -1.0ns tCLmin or tCHmin 0.9 0.4 Max -
*1
To. -0 +/- 1ns +/- 1ns +/- 0.75ns 0.75 ns -Z +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -Y +/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/- 0.75ns -0 +/- 0.8ns +/- 0.8ns +/- 0.6ns 0.6 ns 1tCK 0.9/1.1 tCK 0.4/0.6 tCK +/-0.8ns
Symbol
V REF V IH(DC) V IL (DC) II IO H IOL
To Max
1.35 V DDQ +0.3 V REF-0.18 5
Min
0.49*VDDQ V REF+0.15 -0.3 -2 -16.8 16.8
Max
0.51*VDDQ V DDQ +0.3 V REF-0.15 2
tHP tQCS tDQCH tQCSW tQCHW tQCHWI
-
-
-
1.1
0.6 4.0
1.1
0.6 4.0
1.1
0.6 4.0
1 1.5tCK
1.25ns 1.25ns
0.5tCK 1.5tCK
1.25ns 1.25ns
0.5tCK 1.5tCK
< Page 12> 15.Changed from 1450mil to 1250mil in Package dimension.
+/- 0.75ns +/- 0.75ns +/- 0.5ns 0.5 ns 2.5tCK-tDQSS 1tCK +/- 0.75ns tCK/2 +/- 0.75ns tCK/2 +/- 0.75ns
2.5tCK-tDQSS 1tCK +/- 1ns tCK/2 +/- 1ns tCK/2 +/- 1ns
< Page 6 > 10. Added Overshoot/Undershoot spec . Vih(max) = 4.2V, the overshoot voltage duration is ≤ 3ns at VDD. . Vil(min) =- 1.5V, the overshoot voltage duration is ≤ 3ns at VSS. < Page 6,7 > 11.Changed AC operating conditions as follows. Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) 0.7 From Min VREF + 0.35 VREF - 0.35 VDDQ+0.6 0.62 Max Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 To Max
Revision 0.1 (Aug. 1999)
1. Modified binning policy From To -Z (133Mhz) -Z (133Mhz/266Mbps@CL=2) -8 (125Mhz) -Y (133Mhz/266Mbps@CL=2.5) -0 (100Mhz) -0 (100Mhz/200Mbps@CL=2) 2.Modified the following AC spec values From. -Z tAC tDQSCK tDQSQ tDS/tDH tCDLR
Rev. 1.0 Dec. 2001
M368L6423BT1
< Page 7 >
184pin Unbuffered DDR SDRAM MODULE
12. Changed Input/Output capacitance as follows. Parameter Input capacitance(A 0 ~ A 12, BA 0 ~ BA 1 ,RAS,CAS, W E ) Input capacitance(CKE 0, CKE 1) Input capacitance( CS 0,CS 1 ) Input capacitance( CLK 0 , CLK 1, CLK 2) Data & DQS input/output capacitance(DQ 0~DQ63 ) Input capacitance(DM 0~DM 8) Symbol CIN1 CIN2 CIN3 CIN4 C OUT CIN5 From Min Max 90 62 55 38 16 16 Min 65 42 42 27 10 10 To Max 81 50 50 34 13 13