wiznet-W5500 中文数据手册

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利用W5500实现继电器远程控制

利用W5500实现继电器远程控制作者：罗萍来源：《物联网技术》2016年第05期摘要：文中提出了采用单片机STC15F2K60S2和以太网控制芯片W5500的继电器远程控制方案，并给出了各模块的详细电路图以及单片机主程序流程图。

该方案工作可靠、网络安全性高、性价比高，在智能楼宇、智能家居等领域有着良好的应用前景。

关键词：远程控制；W5500；单片机；继电器中图分类号：TP39 文献标识码：A 文章编号：2095-1302（2016）05-00-040 引言继电器远程控制的实现不仅方便了操作并且提高了效率。

只要有网络的地方就可以对继电器进行控制，再由继电器控制其他设备，从而实现设备的远程控制。

通过使用以太网控制芯片W5500，利用TCP协议，便可实现继电器的远程控制。

1 系统总体结构系统总体结构如图1所示。

计算机作为客户端，W5500作为服务器，利用TCP协议实现客户端到服务器的连接。

计算机端使用广州致远电子有限公司开发的免费软件“TCP&UDP测试工具”发送继电器控制命令；控制命令经网络传送到W5500；单片机通过读取W5500的接收数据存储器接收控制命令，并根据命令对继电器进行开关控制。

系统所需的主要工作包括W5500网络控制模块电路的设计、单片机及继电器控制模块电路的设计和单片机控制程序的设计。

图1 系统总体结构2 硬件设计2.1 W5500网络控制模块系统以W5500芯片为核心组成网络控制模块，采用TCP协议与计算机端进行通信，接收计算机端发送来的继电器控制命令。

2.1.1 W5500简介由于OSI（Open System Interconnection，开放式系统互联）七层协议的网络体系结构模型与TCP/IP四层协议的网络体系结构模型都有各自的优缺点，因此在分析、研究计算机网络时往往采用Andrew S.Tanenbaum教授建议的综合以上两种模型优点的五层协议的网络体系结构模型，它包括物理层、数据链路层、网络层、传输层以及应用层。

W5500问题集锦

W5500问题集锦(一)发布时间：2013-11-27 阅读次数：1445 字体大小: 【小】【中】【大】在”WIZnet杯”以太网技术竞赛中，有很多参赛者在使用中对W5500有各种各样的疑问，对于这款WIZnet新推出的以太网芯片，使用中大家是不是也一样存在以下问题呢？来看一看：1.W5500不支持自动极性变换，有点失望……答：其实，只要对方支持极性变换就可以实现，现在的设备不支持极性变换的很少的。

你要是碰到个别老设备连不上，再换交叉线也不迟。

基本上2000年以后的设备都没问题的啦~原帖来自：9MCU2.W5500+STM32F0无法通信问题描述1：我现在做毕设，老师推荐买了W5500这款芯片，与STM32F0进行通信。

但是根据收集到的资料，修改的例程找不到问题所在。

对于网络这部分，本人小白一个，附上程序，希望大家指导一下！谢谢!答1：先附上W5500的例程问题描述2：如果ping 不通，TCP连接不能建立是代码的问题吗？loopback的程序步骤是怎样的答2：W5500 若想Ping通的话需要保证以下2点：1）物理信道通信正常：初步判定Link 灯及状态灯指示正常。

2）配置了W5500的IP，网关，子网掩码，MAC地址这些特殊寄存器由于W5500内部硬件逻辑电路实现了ARP协议。

所以，一旦收到ping包请求的话，会自动回复。

以上的设置不过是为了保证基本信道及通讯能够建立的而已。

反向而言，如果Ping不通，也可以先从这两方面着手。

原帖来自：9MCU3.W5500没指明接收缓冲数据格式，和W5100一样？问题描述：习惯码字和调试分离，虽然待会调试就知道了，也不妨提出来沟通下。

答：注意SPI帧的不同。

W5100：W5500：原帖来自：9MCU4.关于w5500程序的几个问题问题描述：有几个关于w5500程序的问题想请教大家：void Reset_W5500(void){WIZ_RESET_0; //低电平Delay_us(50); //这个的时间如果设为500us，貌似指示灯就全暗了？？WIZ_RESET_1;Delay_ms(200);}while(( (getPHYCFGR()) & PHYCFGR_LNK_ON) == PHYCFGR_LNK_OFF); //PHYCFGR_LNK_OFF是0×00，PHYCFGR_LNK_ON是0×01。

YIXIN_W5500模块用户手册 V2

User ManualYIXIN_W5500模块用户手册全硬件TCP/IP协议以太网模块目录一、YIXIN_W5500以太网模块简介 (1)二、YIXIN_W5500模块排针功能表 (1)三、W5500芯片资源介绍 (2)四、电脑调试软件安装 (3)五、调式方法 (5)1.YIXIN_W5500模块接线方法 (5)2.W5500客户端模式测试 (5)3.W5500服务端模式测试 (12)4.W5500 UDP模式测试 (15)模块购买链接：/item.htm?spm=a1z10.1.w4004-7343112040.8.6OZKhY&id= 40933615687一、YIXIN_W5500以太网模块简介YIXIN_W5500以太网模块是一款基于WIZnet W5500芯片的以太网模块，是一款性能出色、性价比高的以太网模块。

模块集成硬件化TCP/IP协议；内部具有32K字节存储器作为TX/RX缓存；支持10/100Mbps的网络传输速率；支持8个独立端口同时运行；同时模块还支持3.3V或者5V电源供电，当5V供电时还可以输出3.3V的电压，方便用户在不同的单片机系统中使用；模块与单片机系统的通讯方式是简单、方便的SPI总线通信。

W5500的具体性能参数请下文的“W5500芯片资料介绍”。

YIXIN_W5500以太网模块的实物图如图1.1所示：图1.1 YIXIN_W5500模块实物图二、YIXIN_W5500模块排针功能表表2.1 YIXIN_W5500模块排针功能说明注1：W5500的工作电压是3.3V，但I/O口可以承受5V电压。

注2：YIXIN_W5500模块有两种供电方式，即为3.3V供电或者5V供电，当使用5V供电时，“3.3V”引脚将会有3.3V的电压输出。

三、W5500芯片资源介绍W5500芯片是一款采用全硬件TCP/IP协议栈的嵌入式以太网控制器，它能使嵌入式系统通过SPI（串行外设接口）接口轻松地连接到网络。

w5500带协议栈以太网芯片手册

W5500 DatasheetVersion 1.0.1http://www.wiznet.co.kr© Copyright 2013 WIZnet Co., Ltd. All rights reserved.W5500The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that provides easier Internet connection to embedded systems. W5500 enables users to have the Internet connectivity in their applications just by using the single chip in which TCP/IP stack, 10/100 Ethernet MAC and PHY embedded.WIZnet…s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE protocols. W5500 embeds the 32Kbyte internal memory buffer for the Ethernet packet processing. If you use W5500, you can implement the Ethernet application just by adding the simple socket program. It‟s faster and easier way rather than using any other Embedded Ethernet solution. Users can use 8 independent hardware sockets simultaneously.SPI (Serial Peripheral Interface) is provided for easy integration with the external MCU. The W5500‟s SPI supports 80 MHz speed and new efficient SPI protocol for the high speed network communication. In order to reduce power consumption of the system, W5500 provides WOL (Wake on LAN) and power down mode.Features-Supports Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE-Supports 8 independent sockets simultaneously-Supports Power down mode-Supports Wake on LAN over UDP-Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)-Internal 32Kbytes Memory for TX/RX Buffers-10BaseT/100BaseTX Ethernet PHY embedded-Supports Auto Negotiation (Full and half duplex, 10 and 100-based )-Not supports IP Fragmentation- 3.3V operation with 5V I/O signal tolerance-LED outputs (Full/Half duplex, Link, Speed, Active)-48 Pin LQFP Lead-Free Package (7x7mm, 0.5mm pitch)2 / 65W5500 Datasheet Version1.0.1 (Sept 2013)Target ApplicationsW5500 is suitable for the following embedded applications:-Home Network Devices: Set-T op Boxes, PVRs, Digital Media Adapters-Serial-to-Ethernet: Access Controls, LED displays, Wireless AP relays, etc.-Parallel-to-Ethernet: POS / Mini Printers, Copiers-USB-to-Ethernet: Storage Devices, Network Printers-GPIO-to-Ethernet: Home Network Sensors-Security Systems: DVRs, Network Cameras, Kiosks-Factory and Building Automations-Medical Monitoring Equipment-Embedded ServersW5500 Datasheet Version1.0.1 (Sept 2013) 3 / 65Block Diagram4 / 65W5500 Datasheet Version1.0.1 (Sept 2013)Table of Contents1Pin Assignment (7)1.1Pin Descriptions (7)2HOST Interface (12)2.1SPI Operation Mode (13)2.2SPI Frame (14)2.2.1Address Phase (14)2.2.2Control Phase (15)2.2.3Data Phase (17)2.3Variable Length Data Mode (VDM) (17)2.3.1Write Access in VDM (18)2.3.2Read Access in VDM (21)2.4Fixed Length Data Mode (FDM) (24)2.4.1Write Access in FDM (25)2.4.2Read Access in FDM (26)3Register and Memory Organization (27)3.1Common Register Block (29)3.2Socket Register Block (30)3.3Memory (31)4Register Descriptions (32)4.1Common Registers (32)4.2Socket Registers (44)5Electrical Specifications (59)5.1Absolute Maximum Ratings (59)5.2Absolute Maximum Ratings (Electrical Sensitivity) (59)5.3DC Characteristics (60)5.4POWER DISSIPATION (61)5.5AC Characteristics (61)5.5.1Reset Timing (61)5.5.2Wake up Time (61)5.5.3Crystal Characteristics (61)5.5.4SPI Timing (62)5.5.5Transformer Characteristics (63)5.5.6MDIX (63)6Package Descriptions (64)Document History Information (65)W5500 Datasheet Version1.0.1 (Sept 2013) 5 / 65Table of FiguresFigure 1. W5500 Pin Layout (7)Figure 2. External reference resistor (11)Figure 3. Crystal reference schematic (11)Figure 4. Variable Length Data Mode (SCSn controlled by the host) (12)Figure 5. Fixed Length Data Mode (SCSn is always connected by Ground) (12)Figure 6. SPI Mode 0 & 3 (13)Figure 7. SPI Frame Format (14)Figure 8. Write SPI Frame in VDM mode (18)Figure 9. SIMR Register Write in VDM Mode (19)Figure 10. 5 Byte Data Write at 1th Socket‟s TX Buffer Block 0x0040 in VDM mode.. 20 Figure 11. Read SPI Frame in VDM mode (21)Figure 12. S7_SR Read in VDM Mode (22)Figure 13. 5 Byte Data Read at Socket 3 RX Buffer Block 0x0100 in VDM mode (23)Figure 14. 1 Byte Data Write SPI Frame in FDM mode (25)Figure 15. 2 Bytes Data Write SPI Frame in FDM mode (25)Figure 16. 4 Bytes Data Write SPI Frame in FDM mode (25)Figure 17. 1 Byte Data Read SPI Frame in FDM mode (26)Figure 18. 2 Bytes Data Read SPI Frame in FDM mode (26)Figure 19. 4 Bytes Data Read SPI Frame in FDM mode (26)Figure 20. Register & Memory Organization (28)Figure 21. INTLEVEL Timing (34)Figure 22. Reset Timing (61)Figure 23. SPI Timing (62)Figure 24. Transformer Type (63)Figure 25. Package Dimensions (64)6 / 65W5500 Datasheet Version1.0.1 (Sept 2013)W5500 Datasheet Version1.0.1 (Sept 2013)7 / 65Pin Assignment1Figure 1. W5500 Pin Layout1.1 Pin DescriptionsTable 1. Pin Type NotationTXN TXP AGND AVDD RXN RXP DNC AVDD AGND EXRES1AVDD NC123456789101112363534333231302928272625W5500N CA G N DA V D DA G N DA V D DV B GA G N DT O C A PA V D D1V 2OR S V DS P D L E D MOSI MISO SCLK SCSn XO XI/CLKIN GND VDD ACTLED DUPLED LINKLEDINTn A G N DN CN CP M O D E 0P M O D E 1P M O D E 2R S V DR S V DR S V DR S V DR S V D R S T n 13141516171819202122232448474645444342414039383748LQFPTable 2. W5500 Pin Description1Internal Bias after hardware reset8 / 65W5500 Datasheet Version1.0.1 (Sept 2013)W5500 Datasheet Version1.0.1 (Sept 2013) 9 / 6510 / 65W5500 Datasheet Version1.0.1 (Sept 2013)The 12.4KΩ(1%) Resistor should be connected between EXRES1 pin and analog ground (AGND) as below.Figure 2. External reference resistorThe crystal reference schematic is shown as below.Figure 3. Crystal reference schematicW5500 Datasheet Version1.0.1 (Sept 2013) 11 / 652HOST InterfaceW5500 provides SPI (Serial Peripheral Interface) Bus Interface with 4 signals (SCSn,SCLK, MOSI, MISO) for external HOST interface, and operates as a SPI Slave.The W5500 SPI can be connected to MCU as shown in Figure 4 and Figure 5according to its operation mode (Variable Length Data / Fixed Length Data Mode)which will be explained in Chapter 2.3 and Chapter 2.4.In Figure 4, SPI Bus can be shared with other SPI Devices. Since the SPI Bus isdedicated to W5500, SPI Bus cannot be shared with other SPI Devices. It is shown inFigure 5.At the Variable Length Data mode (as shown in Figure 4), it is possible to share theSPI Bus with other SPI devices. However, at the Fixed Length Data mode (as shown inFigure 5), the SPI Bus is dedicated to W5500 and can‟t be shared with other devices.Figure 4. Variable Length Data Mode (SCSn controlled by the host)Figure 5. Fixed Length Data Mode (SCSn is always connected by Ground)The SPI protocol defines four modes for its operation (Mode 0, 1, 2, 3).Each modediffers according to the SCLK polarity and phase. The only difference between SPIMode 0 and SPI Mode 3 is the polarity of the SCLK signal at the inactive state.With SPI Mode 0 and 3, data is always latched in on the rising edge of SCLK andalways output on the falling edge of SCLK.W5500 Datasheet Version1.0.1 (Sept 2013)13 / 65The W5500 supports SPI Mode 0 and Mode 3. Both MOSI and MISO signals use transfer sequence from Most Significant Bit (MSB) to Least Significant Bit (LSB) when MOSI signal transmits and MISO signal receives. MOSI & MISO signals always transmit or receive in sequence from the Most Significant Bit (MSB) to Least Significant Bit (LSB).Figure 6. SPI Mode 0 & 32.1 SPI Operation ModeW5500 is controlled by SPI Frame (Refer to the Chapter 2.2 SPI Frame) which communicates with the External Host. W5500 SPI Frame consists 3 phases, Address Phase, Control Phase and Data Phase.Address Phase specifies 16 bits Offset Address for W5500 Register or TX/RX Memory. Control Phase specifies the block to which Offset (set by Address Phase) belongs, and specifies Read/Write Access Mode and SPI Operation Mode (Variable Length Data / Fixed Length Data Mode).And Data Phase specifies random length (N-bytes, 1 ≤ N) Data or 1 byte, 2 bytes and 4 bytes Data.If SPI Operation Mode is set as Variable Length Data Mode (VDM), SPI Bus Signal SCSn must be controlled by the External Host with SPI Frame step.At the Variable Length Data Mode, SCSn Control Start (Assert (High-to-Low)) informs W5500 of SPI Frame Start (Address Phase), and SCSn Control End (De-assert (Low-to-High) informs W5500 of SPI Frame End (Data Phase End of random N byte).SCLKMISO/MOSISamplingTogglingMode 3 : SCLK idle level highSCLK MISO/MOSI SamplingTogglingMode 0 : SCLK idle level low2.2 SPI FrameW5500 SPI Frame consists of 16bits Offset Address in Address Phase, 8bits Control Phase and N bytes Data Phase as shown in Figure 7.The 8bits Control Phase is reconfigured with Block Select bits (BSB[4:0]), Read/Write Access Mode bit (RWB) and SPI Operation Mode (OM[1:0]).Block Select bits select the block to which the Offset Address belongs.Figure 7. SPI Frame FormatW5500 supports Sequential Data Read/Write. It processes the data from the base (the Offset Address which is set for 2/4/N byte Sequential data processing) and the next data by increasing the Offset Address (auto increment addressing) by 1.2.2.1 Address PhaseThis Address Phase specifies the 16 bits Offset Address for the W5500 Registers and TX/RX Buffer Blocks.The 16-bit Offset Address value is transferred from MSB to LSB sequentially . The SPI frame with 2/4/N byte data phase supports the Sequential Data Read/Write in which Offset address automatically increases by 1 every 1 byte data.Select Bits ModeW2.2.2Control PhaseThe Control Phase specifies the Block to which the Offset Address (set by AddressPhase) belongs, the Read/Write Access Mode and the SPI Operation Mode.7 6 5 4 3 2 1 0W5500 Datasheet Version1.0.1 (Sept 2013) 15 / 652.2.3Data PhaseWith the Control Phase set by the SPI Operation Mode Bits OM[1:0], the Data Phaseis set by two types of length, one type is the N-Bytes length (VDM mode) and theother type is 1/2/4 Bytes (FDM mode).At this time, 1 byte data is transferred through MOSI or MISO signal from MSB toLSB sequentially.2.3Variable Length Data Mode (VDM)In VDM mode, the SPI Frame Data Phase Length is determined by SCSn Control ofthe External Host. That means that the Data Phase Length can have random value(Any length from 1 Byte to N Bytes) according to the SCSn Control.The OM[1:0] of the Control Phase should be …00‟ value in VDM mode.W5500 Datasheet Version1.0.1 (Sept 2013) 17 / 652.3.1Write Access in VDMFigure 8. Write SPI Frame in VDM modeFigure 8 shows the SPI Frame when the external host accesses W5500 for writing. In VDM mode, the RWB signal is …1‟ (Write), OM[1:0] is …00‟ in SPI Frame Control Phase.At this time the External Host assert (High-to-Low) SCSn signal before transmitting SPI Frame.Then the Host transmits SPI Frame ‟s all bits to W5500 through MOSI signal. All bits are synchronized with the falling edge of the SCLK.After finishing the SPI Frame transmit, the Host deasserts SCSn signal (Low-to-High).When SCSn is Low and the Data Phase continues, the Sequential Data Write can be supported.SCSnMOSI SCLK MOSI MISOSCSnSCLKW5500 Datasheet Version1.0.1 (Sept 2013)19 / 651 Byte WRITE Access ExampleWhen the Host writes Data 0xAA to …Socket Interrupt Mask Register (SIMR) of Common Register Block by using VDM mode, the data is written with the SPI Frame below.The External Host asserts (High-to-Low) SCSn before transmitting SPI Frame, then the Host transmits 1 bit with synchronizing the T oggle SCLK. The External Host de-asserts (Low-to-High) the SCSn at the end of SPI Frame transmit. (Refer to the Figure 9)Figure 9. SIMR Register Write in VDM ModeSCSnN-Bytes WRITE Access ExampleWhen the Host writes 5 Bytes Data (0x11, 0x22, 0x33, 0x44, 0x55) to Socket 1‟s TX Buffer Block 0x0040 Address by using VDM mode, 5 bytes data are written with the SPI Frame below.The N-Bytes Write Access is shown in Figure 10.The 5bytes of Data (0x11,0x22, 0x33, 0x44, 0x55) are written sequentially to Socket 1‟s Tx Buffer Block Address 0x0040 ~ 0x0044.The External Host asserts (High-to-Low) SCSn before transmitting SPI Frame. The External Host de-asserts (Low-to-High) the SCSn at the end of SPI Frame transmit.Figure 10. 5 Byte Data Write at 1th Socket ‟s TX Buffer Block 0x0040 in VDM modeSCSnSCSnW5500 Datasheet Version1.0.1 (Sept 2013)21 / 652.3.2Read Access in VDMFigure 11. Read SPI Frame in VDM modeFigure 11 shows the SPI Frame when external host accesses W5500 for reading In VDM mode, the RWB signal is …0‟ (Write), OM[1:0] is …00‟ in SPI Frame Control Phase.At this time the External Host assert (High-to-Low) SCSn signal before transmitting SPI Frame.Then the Host transmits Address and Control Phase all bits to W5500 through MOSI signal. All bits are synchronized with the falling edge of the SCLK.Then the Host receives all bits of Data Phase with synchronizing the rising edge of Sampling SCLK through MISO signal.After finishing the Data Phase receive, the Host deasserts SCSn signal (Low-to-High).When SCSn is Low and the Data Phase continues to receive, the Sequential Data Read can be supported.MOSI MISOSCSnSCLKSCSnMOSI MISOSCLK1 Byte READ Access ExampleWhen the Host reads the …Socket Status Register(S7_SR) of the Socket 7‟s Register Block by using VDM mode, the data is read with the SPI Frame below. Let ‟s S7_SR to …SOCK_ESTABLISHED (0x17)‟.The External Host asserts (High-to-Low) SCSn signal before transmitting SPI Frame, then the Host transmits Address and Control Phase to W5500 through the MOSI signal. Then the Host receives Data Phase from the MISO signal.After finishing the Data Phase receives, the Host deasserts SCSn signal (Low-to-High). (Refer to the Figure 12.)Figure 12. S7_SR Read in VDM ModeSCSnW5500 Datasheet Version1.0.1 (Sept 2013)23 / 65N-Bytes Read Access ExampleWhen the Host reads 5 Bytes Data (0xAA, 0xBB, 0xCC, 0xDD, 0xEE) from the Socket 3‟s RX Buffer Block 0x0100 Address by using VDM mode, 5 bytes data are read with the SPI Frame as below.The N-Bytes Read Access is shown in Figure 13.The 5 bytes of Data (0xAA, 0xBB, 0xCC, 0xDD, 0xEE) are read sequentially from the Socket 3‟s Rx Buffer Block Address 0x0100 ~ 0x0104.The External Host asserts (High-to-Low) SCSn before transmitting SPI Frame. The External Host de-asserts (Low-to-High) the SCSn at the end of the SPI Frame Data Phase.Figure 13. 5 Byte Data Read at Socket 3 RX Buffer Block 0x0100 in VDM modeSCSnSCSn2.4Fixed Length Data Mode (FDM)The FDM mode can be used when the External Host cannot control SCSn signal.The SCSn signal should be tied to Low (Always connected to GND) and it is notpossible to share the SPI Bus with other SPI Devices. (Refer to the Figure 5.)In VDM mode, Data Phase length is controlled by SCSn control.But in FDM mode, Data Phase length is controlled by OM[1:0] value (…01‟ / …10‟ / …11‟)which is the SPI Operation Mode Bits of the Control Phase.As the SPI Frame of FDM mode is the same as SPI Frame of VDM mode (1Byte, 2Bytes, 4 Bytes SPI Frame) except for the SCSn signal control and OM[1:0] setting, thedetail about FDM mode is not described in this section.It is not recommended to use the FDM mode unless you are in inevitable status. Inaddition, we use only 1/2/4 Bytes SPI Frame, as described in …Chapter 2.4.1‟&…Chapter 2.4.2‟. Using SPI Frame with other length of Data will cause malfunction ofW5500.2.4.1Write Access in FDM1 Bytes WRITE AccessFigure 14. 1 Byte Data Write SPI Frame in FDM mode2 Bytes WRITE AccessFigure 15. 2 Bytes Data Write SPI Frame in FDM mode4 Bytes WRITE AccessFigure 16. 4 Bytes Data Write SPI Frame in FDM modeW5500 Datasheet Version1.0.1 (Sept 2013) 25 / 652.4.2Read Access in FDM1 Byte READ AccessFigure 17. 1 Byte Data Read SPI Frame in FDM mode2 Bytes READ AccessFigure 18. 2 Bytes Data Read SPI Frame in FDM mode4 Bytes READ AccessFigure 19. 4 Bytes Data Read SPI Frame in FDM mode3Register and Memory OrganizationW5500 has one Common Register Block, eight Socket Register Blocks, and TX/RXBuffer Blocks allocated to each Socket. Each block is selected by the BSB[4:0](BlockSelect Bit) of SPI Frame. Figure 20 shows the selected block by the BSB[4:0] and theavailable offset address range of Socket TX/RX Buffer Blocks. Each Socket‟s TX BufferBlock exists in one 16KB TX memory physically and is initially allocated with 2KB.Also, Each Socket‟s RX Buffer Block exists in one 16KB RX Memory physically and isinitially allocated with 2KB.Regardless of the allocated size of each Socket TX/RX Buffer, it can be accessiblewithin the 16 bits offset address range (From 0x0000 to 0xFFFF).Refer to …Chapter 3.3‟ for more information about 16KB TX/RX Memoryorganization and access method.W5500 Datasheet Version1.0.1 (Sept 2013) 27 / 65Figure 20. Register & Memory OrganizationBlock Select BitsBlocksPhysical 16KB RX Memory16bit Offset AddressValid Range11111 (0x1F)11110 (0x1E)11101 (0x1E)11100 (0x1C)11011 (0x1B)11010 (0x1A)11001 (0x19)11000 (0x18)10111 (0x17)10110 (0x16)10101 (0x15)10011 (0x13)10010 (0x12)10001 (0x11)01000 (0x10)01111 (0x0F)01110 (0x0E)01101 (0x0D)01100 (0x0C)01011 (0x0B)01010 (0x0A)01001 (0x09)01000 (0x08)00111 (0x07)00110 (0x06)00101 (0x05)00011 (0x03)00010 (0x02)00001 (0x01)00000 (0x00)00100 (0x04)10100 (0x14)0x00000x3FFFSocket 0TX Bufer (2KB)Socket 1TX Buffer (2KB)Socket 2TX Buffer (2KB)Socket 3TX Buffer (2KB)Socket 4TX Buffer (2KB)Socket 5TX Buffer (2KB)Socket 6TX Buffer (2KB)Socket 7TX Buffer (2KB)0x0000Socket 0RX Buffer (2KB)Socket 1RX Buffer (2KB)Socket 2RX Buffer (2KB)Socket 3RX Buffer (2KB)Socket 4RX Buffer (2KB)Socket 5RX Buffer (2KB)Socket 6RX Buffer (2KB)Socket 7 RX Buffer (2KB)Physical 16KB TX Memory3.1Common Register BlockCommon Register Block configures the general information of W5500 such as IP andMAC address. This block can be selected by the BSB[4:0] value of SPI Frame. <T able3> defines the offset address of registers in this block. Refer to …Chapter 4.1‟formore details about each register.Table 3. Offset Address for Common RegisterW5500 Datasheet Version1.0.1 (Sept 2013) 29 / 653.2Socket Register BlockW5500 supports 8 Sockets for communication channel. Each Socket is controlled by Socket nRegister Block(when 0≤n≤7). The n value of Socket n Register can be selected by BSB[4:0] ofSPI Frame. <Table 4> defines the 16bits Offset Address of registers in Socket n Register Block.Refer to …Chapter 4.2‟ for more details about each register.Table 4. Offset Address in Socket n Register Block (0≤n≤7)3.3MemoryW5500 has one 16KB TX memory for Socket n TX Buffer Blocks and one 16KB RXmemory for Socket n RX buffer Blocks.16KB TX memory is initially allocated in 2KB size for each Socket TX Buffer Block(2KB X 8 = 16KB). The initial allocated 2KB size of Socket n TX Buffer can be re-allocated by using …Socket n TX Buffer Size Register (Sn_TXBUF_SIZE)‟.Once all Sn_TXBUF_SIZE registers have been configured, Socket TX Buffer is allocatedwith the configured size of 16KB TX Memory and is assigned sequentially from Socket0 to Socket 7. Its physical memory address is automatically determined in 16KB TXmemory. Therefore, the total sum of Sn_TXBUF_SIZE should be not exceed 16 in caseof error in data transmission.The 16KB RX memory allocation method is the same as the 16KB TX memoryallocation method. 16KB RX memory is initially allocated into 2KB size for eachSocket RX Buffer Block (2KB X 8 = 16KB). The initial allocated 2KB size of Socket n RXBuffer can be re-allocated by using …Socket n RX Buffer Size Register(Sn_RXBUF_SIZE)‟.When all Sn_RXBUF_SIZE registers have been configured, the Socket RX Buffer isallocated with the configured size in 16KB RX Memory and is assigned sequentiallyfrom Socket 0 to Socket 7. The physical memory address of the Socket RX Buffer isautomatically determined in 16KB RX memory. Therefore, the total sum ofSn_RXBUF_SIZE should not exceed 16, data reception error will occur if exceeded.For 16KB TX/RX memory allocation, refer to Sn_TXBUF_SIZE & Sn_RXBUF_SIZE in…Chapter 4.2‟.The Socket n TX Buffer Block allocated in 16KB TX memory is buffer for saving datato be transmitted by host. The 16bits Offset Address of Socket n TX Buffer Block has64KB address space ranged from 0x0000 to 0xFFFF, and it is configured withreference to …Socket n TX Write Pointer Register (Sn_TX_WR)‟ & …Socket n TX ReadPointer Register(Sn_RX_RD)‟. However, the 16bits Offset Address automaticallyconverts into the physical address to be accessible in 16KB TX memory such as Figure20. Refer to …Chapter 4.2‟ for Sn_TX_WR & Sn_TX_RD.The Socket n RX Buffer Block allocated in 16KB RX memory is buffer for saving thereceived data through the Ethernet. The 16bits Offset Address of Socket n RX BufferBlock has 64KB address space ranged from 0x0000 to 0xFFFF, and it is configured withreference to …Socket n RX RD Pointer Register (Sn_RX_RD)‟& …Socket n RX WritePointer Register (Sn_RX_WR)‟. However, the 16bits Offset Address automaticallyconverts into the physical address to be accessible in 16KB RX memory such as Figure20. Refer to …Chapter 4.2‟ for Sn_RX_RD & Sn_RX_WR.4Register Descriptions4.1Common RegistersMR (Mode Register) [R/W] [0x0000] [0x00]2MR is used for S/W reset, ping block mode and PPPoE mode.7 6 5 4 3 2 1 02Register Notation : [Read/Write] [Address] [Reset value]GAR (Gateway IP Address Register) [R/W] [0x0001 – 0x0004] [0x00]GAR configures the default gateway address.Ex)In case of “192.168.0.1”0x0001 0x0002 0x0003 0x0004SUBR (Subnet Mask Register) [R/W] [0x0005 – 0x0008] [0x00]SUBR configures the subnet mask address.Ex)In case of “255.255.255.0”0x0005 0x0006 0x0007 0x0008SHAR (Source Hardware Address Register) [R/W] [0x0009 – 0x000E] [0x00] SHAR configures the source hardware address.Ex)In case of “00.08.DC.01.02.03”0x0009 0x000A 0x000B 0x000C 0x000D 0x000ESIPR (Source IP Address Register) [R/W] [0x000F – 0x0012] [0x00]SIPR configures the source IP address.Ex)In case of “192.168.0.2”0x000F 0x0010 0x0011 0x0012INTLEVEL (Interrupt Low Level Timer Register) [R/W] [0x0013 – 0x0014] [0x0000]INTLEVEL configures the Interrupt Assert Wait Time (I AWT ). When the next interrupt occurs, Interrupt PIN (INTn ) will assert to low after INTLEVEL time.Figure 21. INTLEVEL Timinga. When Timeout Interrupt of Socket 0 is occurred, S0_IR[3] & SIR[0] bit set as …1‟ and then INTn PIN is asserted to low.b. When the connection interrupt of Socket 1 is occurred before the previous interrupt processing is not completed, S1_IR[0] & SIR[1] bits set as …1‟ and INTn PIN is still low.c. If the host processed the previous interrupt completely by clearing the S0_IR[3] bit, INTn PIN is de-asserted to high but S1_IR[0] & SIR[1] is still set as …1‟.d. Although S1_IR[0] & SIR[1] bit is set as …1‟, the INTn can‟t be asserted to low during INTLEVEL time. After the INTLEVEL time expires, the INTn will be asserted to low.PLL_CLKSIR S0_IR S1_IRINTnIR (Interrupt Register) [R/W] [0x0015] [0x00]IR indicates the interrupt status. Each bit of IR can be cleared when the host writes …1‟ value to each bit. If IR is not equal to …0x00‟, INTn PIN is asserted low until it is …0x00‟.7 6 5 4 3 2 1 0IMR (Interrupt Mask Register) [R/W][0x0016][0x00]IMR is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. Whena bit of IMR is …1‟ and the corresponding bit of IR is …1‟, an interrupt will be issued.In other words, if a bit of IMR is …0‟, an interrupt will not be issued even if the corresponding bit of IR is …1‟.7 6 5 4 3 2 1 0SIR (Socket Interrupt Register) [R/W] [0x0017] [0x00]SIR indicates the interrupt status of Socket. Each bit of SIR be still …1‟ until Sn_IR is cleared by the host. If Sn_IR is not equal to …0x00‟, the n-th bit of SIR is …1‟ and INTn PIN is asserted until SIR is …0x00‟.7 6 5 4 3 2 1 0SIMR (Socket Interrupt Mask Register) [R/W] [0x0018] [0x00]Each bit of SIMR corresponds to each bit of SIR. When a bit of SIMR is …1‟ and the corresponding bit of SIR is …1‟, Interrupt will be issued. In other words, if a bit of SIMR is …0‟, an interrupt will be not issued even if the corresponding bit of SIR is …1‟.7 6 5 4 3 2 1 0RTR (Retry Time-value Register) [R/W] [0x0019 – 0x001A] [0x07D0]RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is …0x07D0‟ or …2000‟. And so the default timeout period is 200ms(100us X 2000).During the time configured by RTR, W5500 waits for the peer response to the packet that is transmitted by Sn_CR(CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5500 retransmits the packet or issues timeout.Ex) When timeout-period is set as 400ms, RTR = (400ms / 1ms) X 10 = 4000(0x0FA0)0x0019 0x001ARCR (Retry Count Register) [R/W] [0x001B] [0x08]RCR configures the number of time of retransmission. When retransmission occurs as many as …RCR+1‟, Timeout interrupt is issued (Sn_IR[TIMEOUT] = …1‟).Ex) RCR = 0x00070x001BThe timeout of W5500 can be configurable with RTR and RCR. W5500 has two kind timeout such as Address Resolution Protocol (ARP) and TCP retransmission.At the ARP (Refer to RFC 826, /rfc.html) retransmission timeout, W5500 automatically sends ARP-request to the peer‟s IP address in order to acquire MAC address information (used for communication of IP, UDP, or TCP). While waiting for ARP-response from the peer, if there is no response during the configured RTR time, a temporary timeout is occurred and ARP-request is retransmitted. It is repeated as many as …RCR + 1‟ times. Even after the ARP-request retransmissions are repeated as …RCR+1‟ and there is no response to the ARP-request, the final timeout is occurred and Sn_IR(TIMEOUT) becomes …1‟. The time of final timeout (ARP TO) of ARP-request is as below.At the TCP packet retransmission timeout, W5500 transmits TCP packets (SYN, FIN, RST, DATA packets) and waits for the acknowledgement (ACK) during the configured RTR time and RCR. If there is no ACK from the peer, a temporary timeout occurs andthe TCP pac ket is retransmitted. The retransmission is repeated as many as …RCR+1‟.Even after TCP retransmission is repeated as …RCR+1‟ and there is no response to the TCP retransmission, the final timeout is occurred and Sn_IR(TIMEOUT) becomes …1‟.The time of final timeout (TCPTO) of TCP retransmission is as below.Ex) When RTR = 2000(0x07D0), RCR = 8(0x0008),ARP TO = 2000 X 0.1ms X 9 = 1800ms = 1.8sTCP TO = (0x07D0+0x0FA0+0x1F40+0x3E80+0x7D00+0xFA00+0xFA00+0xFA00+0xFA00) X 0.1ms = (2000 + 4000 + 8000 + 16000 + 32000 + ((8 - 4) X 64000)) X 0.1ms= 318000 X 0.1ms = 31.8sPTIMER (PPP Link Control Protocol Request Timer Register) [R/W] [0x001C] [0x0028] PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.Ex) in case that PTIMER is 200,200 * 25(ms) = 5000(ms) = 5 secondsPMAGIC (PPP Link Control Protocol Magic number Register) [R/W] [0x001D] [0x00] PMAGIC configures the 4bytes magic number to be used in LCP echo request.Ex) PMAGIC = 0x010x001DLCP Magic number = 0x01010101。

W5500网络扩展板教程

以太网在各个领域和行业有着非常广泛和深入的应用，这主要源于以太网的高度灵活性和较易实现的特点。

因为以太网具有组网简单，成本低廉，兼容性优秀，连接可靠，以及拓扑调整方便的优点，在作为智能家居，物联网或者无线传感网络的网关方面有其他的网络技术所不具备的优势，从而得到大力的发展和应用。

本文将详细介绍如何使嵌入式系统接入到以太网，如何采用硬件协议栈的方式使您的方案或应用快速高效的连接到互联网，如何实现TCP/IP的通信，以及如何实现上层应用层协议等等。

第1章以太网模型以太网的实现采用层次结构的概念，每一层都有自己的功能，就像建筑物一样，每一层都靠下一层支持，每一层也都为上一层功能的实现打好基础。

实际上，用户接触到的只是最上面的一层，根本感觉不到底层的存在。

要理解以太网，必须从最下层开始，自下而上理解每一层的功能。

1.1五层结构以太网模型有不同的分层方式，ISO（国际标准组织）提出OSI七层网络模型，自上而下分别为：应用层、表示层、会话层、传输层、网络层、数据链路层、物理层。

OSI七层网络模型主要是为了解决异种网络互联时所遇到的兼容性问题。

它的最大优点是将服务、接口和协议这三个概念明确地区分开来，也使网络的不同功能模块承担起不同的职责。

由于互联网网络体系结构以TCP/IP协议为核心，因而基于TCP/IP的参考模型将以太网可以分成四层，自上而下分别为：应用层、传输层、网络互联层、网络接口层。

根据我自己的理解，把以太网分成五层比较容易解释。

这五层结构不仅符合OSI结构强调的不同层次承担不同职责的特点，同时也符合TCP/IP协议参考模型协议之间相互支撑、相互调用的逻辑关系。

图1-1-1以太网五层模型如上图所示，最底下的一层叫做“物理层”，也叫“PHY层”，最上面的一层叫做“应用层”，中间的三层（自下而上）分别是“链路层”，也叫“MAC层”、“网络层”和“传输层”。

越下面的层，越靠近硬件；越上面的层，越靠近用户。

W5500以太网芯片及模块使用

W5500以太网芯片及模块使用
一、模块介绍
是以太网转spi接口的，模块上有3个led和一个复位按钮，灯的含义是：
LINKLED
网络连接指示灯（Link LED）
显示当前连接状态：
低电平：连接建立；
高电平：未连接；
DUPLED
全/半双工指示灯（Duplex LED）
显示当前连接的双工状态：
低电平：全双工状态；
高电平：半双工状态；
ACTLED
活动状态指示灯（Active LED）
显示数据收/发活动时，物理介质子层的载波侦听活动情
况：
低电平：有物理介质子层的载波侦听信号；
高电平：无物理介质子层的载波侦听信号；
但貌似配置成全双工100M的速度也没什么增加，哪里出问题了呢？我现在使用18M的spi，使用wiz官方loopback软件测试速度为5Mb/s左右，好慢啊(/ □ \)
二、模块驱动
注意：在官网上有人共享了github的库函数驱动，不过是C99标准的，这一段Keil的c编译器支持好像有问题，而且对于是库函数很
致命，使用寄存器则无所谓
比如：ctlsocket和ctlwizchip函数的参数会因C99和C89的强转void类型定义不同，使其失效。

eg：0x0000不会错，0x0010可能会篡改成0x4e3c。

W5500问题集锦解读

你要是碰到个别老设备连不上，再换交叉线也不迟。

基本上2000年以后的设备都没问题的啦~原帖来自：9MCU2.W5500+STM32F0无法通信问题描述1：我现在做毕设，老师推荐买了W5500这款芯片，与STM32F0进行通信。

但是根据收集到的资料，修改的例程找不到问题所在。

2）配置了W5500的IP，网关，子网掩码，MAC地址这些特殊寄存器由于W5500内部硬件逻辑电路实现了ARP协议。

所以，一旦收到ping包请求的话，会自动回复。

以上的设置不过是为了保证基本信道及通讯能够建立的而已。

反向而言，如果Ping不通，也可以先从这两方面着手。

原帖来自：9MCU3.W5500没指明接收缓冲数据格式，和W5100一样？问题描述：习惯码字和调试分离，虽然待会调试就知道了，也不妨提出来沟通下。

答：注意SPI帧的不同。

w5500引脚图及引脚说明

w5500引脚图及引脚说明W5500是WIZnet推出的高性能以太网接口芯片系列之一，内部集成全硬件TCP/IP协议栈+MAC+PHY。

全硬件协议栈技术采用硬件逻辑门电路实现复杂的TCP/IP协议簇，其应用具有简单快速、可靠性高、安全性好等显著优势；内部集成MAC和PHY 工艺，使得单片机接入以太网方案的硬件设计更为简捷和高效。

W5500 是一款全硬件TCP/IP 嵌入式以太网控制器，为嵌入式系统提供了更加简易的互联网连接方案。

W5500 集成了TCP/IP 协议栈，10/100M 以太网数据链路层（MAC）及物理层（PHY），使得用户使用单芯片就能够在他们的应用中拓展网络连接。

久经市场考验的WIZnet 全硬件TCP/IP 协议栈支持TCP，UDP，IPv4，ICMP，ARP，IGMP 以及PPPoE 协议。

W5500 内嵌32K 字节片上缓存以供以太网包处理。

如果你使用W5500，你只需要一些简单的Socket 编程就能实现以太网应用。

这将会比其他嵌入式以太网方案更加快捷、简便。

用户可以同时使用8 个硬件Socket 独立通讯。

W5500 提供了SPI（外设串行接口）从而能够更加容易与外设MCU 整合。

而且，W5500 的使用了新的高效SPI 协议支持80MHz 速率，从而能够更好的实现高速网络通讯。

为了减少系统能耗，W5500 提供了网络唤醒模式（WOL）及掉电模式供客户选择使用。

w5500芯片特点全硬件TCP/IP协议栈- 支持TCP，UDP，ICMP，IPv4，ARP，IGMP，PPPoE协议- 硬件协议栈不受网络攻击，安全稳定8个独立的硬件Socket，各路通信互不影响32bytes片上缓存供TCP/IP包处理集成802.3以太网MAC集成10BaseT / 100Base-T以太网PHY主机接口：SPI高速串行外设接口（最高80Mhz ）低功耗，工作温度40℃左右支持嵌入式操作系统：Linux RTOS。

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高性能以太网芯片W5500 数据手册W5500 是一款全硬件TCP/IP 嵌入式以太网控制器，为嵌入式系统提供了更加简易的互联网连接方案。

W5500 集成了TCP/IP 协议栈，10/100M 以太网数据链路层（MAC）及物理层（PHY），使得用户使用单芯片就能够在他们的应用中拓展网络连接。

久经市场考验的WIZnet 全硬件TCP/IP 协议栈支持TCP,UDP,IPv4,ICMP,ARP,IGMP 以及PPPoE 协议。

W5500 内嵌32K 字节片上缓存以供以太网包处理。

如果你使用W5500，你只需要一些简单的Socket 编程就能实现以太网应用。

这将会比其他嵌入式以太网方案更加快捷、简便。

用户可以同时使用8 个硬件Socket 独立通讯。

W5500 提供了SPI（外设串行接口）从而能够更加容易与外设MCU 整合。

而且，W5500 的使用了新的高效SPI 协议支持80MHz 速率，从而能够更好的实现高速网络通讯。

为了减少系统能耗，W5500 提供了网络唤醒模式（WOL）及掉电模式供客户选择使用。

特点∙支持硬件TCP/IP 协议：TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE∙支持8 个独立端口（Socket）同时通讯∙支持掉电模式∙支持网络唤醒∙支持高速串行外设接口（SPI 模式0，3）∙内部32K 字节收发缓存∙内嵌10BaseT/100BaseTX 以太网物理层（PHY）∙支持自动协商（10/100-Based 全双工/半双工）∙不支持IP 分片∙ 3.3V 工作电压，I/O 信号口5V 耐压；∙LED 状态显示（全双工/半双工，网络连接，网络速度，活动状态）∙48 引脚LQFP 无铅封装（7x7mm, 0.5mm 间距）目标应用W5500 适合于以下嵌入式应用：∙家庭网络设备: 机顶盒、个人录像机、数码媒体适配器∙串行转以太网: 门禁控制、LED 显示屏、无线AP 继电器等∙并行转以太网: POS/微型打印机、复印机∙USB 转以太网: 存储设备、网络打印机∙GPIO 转以太网: 家庭网络传感器∙安全系统: 数字录像机、网络摄像机、信息亭∙工厂和楼宇自动化控制系统∙医疗监测设备∙嵌入式服务器1 引脚分配图1 W5500 引脚分布1.1 引脚描述表格 1 引脚类型标记表格 2 W5500 引脚描述在EXRES1 引脚和模拟地之间需要接一个12. 4KΩ，精度 1 %的电阻。

如下图所示:图 2 外部参考电阻晶振参考周边电路如下图所示：图3 晶振参考电路2 主机接口W5500 提供了SPI（串行外部接口）作为外设主机接口，共有SCSn, SCLK, MOSI, MISO 4 路信号，且作为SPI 从机工作。

W5500 与MCU 的连接方式如图4 和图5 所示。

根据其工作模式（可变数据长度模式/固定数据长度模式）将分别在第 2.3 章节和 2.4 章节做解释说明。

如图4 所示，可以与其他SPI 设备共用SPI 接口在可变数据长度模式中（如图4 所示），W5500 可以与其他SPI 设备共用SPI 接口。

但是一旦将SPI 接口指定给W5500 之后，则不能再与其他SPI 设备共用，如图5 所示。

在可变数据长度模式（如图 4 所示），W5500 可以与其他SPI 设备共用SPI 接口。

然而，在固定数据长度模式（如图 5 所示），SPI 将指定给W5500，不能与其他SPI 设备共享。

图4 可变数据长度模式（SCSn 受主机控制）图 5 固定数据长度模式（SCSn 保持接地）SPI 协议定义了四种工作模式（模式0，1，2，3）。

每种模式的区别是根据SCLK 的极性及相位不同定义的。

SPI 的模式0 和模式 3 唯一不同的就是在非活动状态下，SCLK 信号的极性。

SPI 的模式0 和3，数据都是在SCLK 的上升沿锁存，在下降沿输出。

W5500 支持SPI 模式0 及模式3.MOSI 和MISO 信号无论是接收或发送，均遵从从最高标志位（MSB）到最低标志位（LSB）的传输序列。

图 6 SPI 模式0&32.1 SPI 工作模式W5500 与外设主机的通讯受SPI 数据帧控制（参考第2.2 章节SPI 数据帧）。

W5500 的帧分为3 段：地址段，控制段，数据段。

地址段为W5500 寄存器或TX/RX 内存指定了16 位的偏移地址。

控制段指定了地址段设定的偏移区域的归属，读/写访问模式以及SPI 工作模式（可变长度模式/固定长度模式）。

数据段可以设定为任意长度（N-字节，1≤N）或者是固定的长度：1 字节，2 字节或 4 字节；如果SPI 工作模式设置为可变数据长度模式（VDM），SPI 的SCSn 信号需要由外部主机通过SPI 帧控制。

在可变数据长度模式下，SCSn 控制SPI 帧的开始和停止：SCSn 信号拉低（高电平到低电平），即代表W5500 的SPI 帧开始（地址段）；SCSn 信号拉高（低电平到高电平），即代表W5500 的SPI 帧结束（数据段的随机N字节数据结尾）；2.2 SPI 数据帧W5500 的SPI 数据帧包括了16 位地址段的偏移地址，8 位控制段和N 字节数据段。

如图7 所示。

8 位控制段可以通过修改区域选择位(BSB[4:0])，读/写访问模式位(RWB)以及SPI工作模式位(OM[1:0])来重新定义。

区域选择位选择了归属于偏移地址的区域。

图7 SPI 数据帧格式W5500 支持数据的连续读/写。

其流程为数据从（2/4/N 字节连续数据的）偏移地址的基址开始传输，偏移地址会（自增寻址）加 1 传输接下来的数据。

2.2.1 地址段地址段为W5500 的寄存器或TX/RX 缓存区指定了16 位的偏移地址。

这16 位偏移地址的值来自于从最高标志位到最低标志位的顺序传输。

SPI 数据帧的数据段（2/4/N 字节）通过偏移地址自增（每传输1 字节偏移地址加1）支持连续数据读/写。

2.2.2 控制段控制段指定了地址段设定的偏移区域的归属，读/写访问模式以及SPI 工作模式。

表格3 SPI 数据帧控制段对应位的说明2.2.3 数据段在SPI 工作模式位OM[1:0]设定了控制端之后，数据段被设定为 2 种长度类型：1 种为可变的N 字节长度（可变数据长度模式），另以一种为确定的1/2/4 字节长度（固定数据长度模式）。

此时，1 字节数据从最大标志位到最小标志位，通过MOSI 或者MISO 信号传输。

2.3 可变数据长度模式在VDM 模式下，SPI 数据帧的长度被外设主机控制的SCSn 所定义。

这就意味着数据段长度根据SCSn 的控制，可以是一个随机值（从1 字节到N 字节任何长度均可）。

在VDM 模式下，M[1:0]位必须为‘00’。

2.3.1 写访问——VDM 模式图8 在VDM 模式下读SPI 数据帧图8 显示的是在外部主机控制W5500 读操作时的SPI 数据帧。

在VDM 模式下，SPI 数据帧的控制段：读写控制位（RWB）为‘1’，工作模式位为’00’。

此时外设主机在传输SPI 数据帧之前，须拉低SCSn 信号引脚。

然后主机通过MOSI 将SPI 数据帧的所有位传输给W5500 ，并在SCLK 的下降沿同步。

在完成SPI 数据帧的传输后，主机拉高SCSn 信号（低电平到高电平）。

当SCSn 保持低电平且数据段持续传输，即可实现连续数据写入。

1 字节数据写访问示例当主机在VDM 模式下，向通用寄存器区域中的Socket 中断屏蔽寄存器写入数据‘0xAA’时，SPI 数据帧的写操作如下所示：Offset Address = 0×0018BSB[4:0] = ‘00000’ RWB = ‘1’ OM[1:0]= ‘00’1st Data = 0xAA在传输SPI 数据帧之前，外设主机须拉低SCSn，然后主机在时钟（SCLK）跳变时同步传输1 位数据。

在SPI 数据帧传输完毕后，外设主机拉高SCSn。

（参考图9）图9 VDM 模式下，SIMR 寄存器写操作N 字节写访问示例当主机在VDM 模式下，向通用寄存器区域中的Socket 中断屏蔽寄存器写入5 字节数据时（0×11, 0×22, 0×33, 0×44, 0×55），SPI 数据帧的写操作如下所示：N 字节的写访问如图10 所示。

5 字节的数据被连续地写入Socket 1 的写缓存地址：0×0040 – 0×0044。

在SPI 数据帧传输时，外设主机拉低SCSn（高电平到低电平）。

在SPI 数据帧传输完毕时，外设主机拉高SCSn（低电平到高电平）。

图10 在VDM 模式下，向Socket1 的发送缓存区0×0040 中写入5 字节数据2.3.2 读访问——VDM 模式图11 在VDM 模式下读SPI 数据帧图11 显示的是当外设主机访问W5500 做读访问时，SPI 的数据帧格式。

在VDM 模式下，读/写访问位（RWB）为‘0’（读模式），SPI 数据帧控制段的工作模式位（OM[1:0]）为‘00’。

与此同时，在SPI 数据帧传输之前，外设主机拉低SCSn（高电平到低电平）。

然后主机通过MOSI 将地址及控制段的所有位传输给W5500.所有为将在SCLK 的下降沿同步。

之后在同步采样时钟（SCLK）的上升沿，主机通过MISO 接收到所有数据位。

在接收完所有数据后，主机拉高SCSn（低电平到高电平）。

当SCSn 保持低电平且数据段持续传输，即可实现连续数据读取。

1 字节数据读访问示例在VDM 模式下，当主机读取Socket 7 寄存器区的Socket 状态寄存器(S7_SR),SPI 数据帧的数据读取如下所示。

我们让S7_SR 设置为Socket 建立模式下（0×17）。

在SPI 数据帧传输之前，外设主机拉低SCSn（高电平到低电平）。

然后外设主机通过M OSI 传输地址段和控制段给W5500.然后主机通过MISO 接收到接收完的数据。

在完成数据段的接收后，主机拉高SCSn（低电平到高电平）。

（参考图12）图12 在VDM 模式下读S7_SRN 字节读访问示例在VDM 模式下，当从Socket3 的地址为 0×0100 的读取缓存中读取 5 字节的数据（0xAA, 0xBB, 0xCC, 0xDD,0xEE）。

这5 个字节数据的读访问SPI 数据帧如下所示。

N 字节读访问如图13 所示。

从Socket 3 的接收缓存（地址0×0100 – 0×0104），连续地读取这5 字节的数据（0xAA,0xBB, 0xCC, 0xDD, 0xEE）。