MAX6419UK36中文资料
K4M64163PK-RE90中文资料

Unit V V °C W mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial)
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Pin Function System Clock Chip Select Clock Enable
Address Bank Select Address Row Address Strobe Column Address Strobe
Write Enable Data Input/Output Mask
111MHz(CL=3)*1, 66MHz(CL2)
MAX4053CSE+中文资料

MAX4053CSE+中文资料General DescriptionThe MAX4051/MAX4052/MAX4053 and MAX4051A/MAX4052A/MAX4053A are low-voltage, CMOS analog ICs configured as an 8-channel multiplexer (MAX4051/A),two 4-channel multiplexers (MAX4052/A), and three sin-gle-pole/double-throw (SPDT) switches (MAX4053/A).The A-suffix parts are fully characterized for on-resistance match, on-resistance flatness, and low leakage.These CMOS devices can operate continuously with dual power supplies ranging from ±2.7V to ±8V or a single supply between +2.7V and +16V. Each switch can handle rail-to-rail analog signals. The off-leakage current is only 0.1nA at +25°C or 5nA at +85°C (MAX4051A/MAX4052A/MAX4053A).All digital inputs have 0.8V to 2.4V logic thresholds,ensuring TTL/CMOS-logic compatibility when using ±5V or a single +5V supply.________________________ApplicationsBattery-Operated Equipment Audio and Video Signal Routing Low-Voltage Data-Acquisition Systems Communications Circuits____________________________FeaturesPin Compatible with Industry-Standard74HC4051/74HC4052/74HC4053?Guaranteed On-Resistance:100?with ±5V SuppliesGuaranteed Match Between Channels:6?(MAX4051A–MAX4053A)12?(MAX4051–MAX4053)?Guaranteed Low Off-Leakage Currents:0.1nA at +25°C (MAX4051A–MAX4053A)1nA at +25°C (MAX4051–MAX4053)?Guaranteed Low On-Leakage Currents:0.1nA at +25°C (MAX4051A–MAX4053A)1nA at +25°C (MAX4051–MAX4053)?Single-Supply Operation from +2.0V to +16V Dual-Supply Operation from ±2.7V to ±8V ?TTL/CMOS-Logic Compatible ?Low Distortion: < 0.04% (600?)?Low Crosstalk: < -90dB (50?)?High Off-Isolation: < -90dB (50?)MAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________ Maxim Integrated Products1___________________________________PinConfigurations/Functional Diagrams19-0463; Rev 2; 10/05Ordering Information continued at end of data sheet.For pricing, delivery, and ordering information,pleasecontact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .M A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 2___________________________________________________________________ ____________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Voltages Referenced to GNDV+........................................................................-0.3V to +17V V-..........................................................................+0.3V to -17V V+ toV-................................................................-0.3V to +17V Voltage into Any Terminal (Note 1)..........(V- - 2V) to (V+ + 2V)or 30mA (whichever occurs first)Continuous Current into Any Terminal..............................±30mA Peak Current, NO or COM(pulsed at 1ms, 10% duty cycle).................................±100mAContinuous Power Dissipation (T A = +70°C)Plastic DIP (derate 10.53m W/°C above +70°C)............842mW Narrow SO (derate 8.70mW/°C above +70°C)..............696mW QSOP (derate 8.00mW/°C above +70°C).....................640mW CERDIP (derate 10.00mW/°C above +70°C)................800mW Operating Temperature RangesMAX405_C_ E/MAX405_AC_E.............................0°C to +70°C MAX405_E_ E/MAX405_AE_E...........................-40°C to +85°C MAX405_MJE/MAX405_AMJE........................-55°C to +125°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CNote 1:Signals on any terminal exceeding V+ or V- are clamped by internal diodes. Limit forward-diode current to maximumcurrent rating.ELECTRICAL CHARACTERISTICS—Dual Supplies (continued) MAX4051/A, MAX4052/A, MAX4053/A Low-Voltage, CMOS Analog Multiplexers/Switches(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T A= T MIN to T MAX, unless otherwise noted. Typical values are at T A= +25°C.)M A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 4___________________________________________________________________ ____________________Note 2:The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.Note 3:?R ON = R ON(MAX)- R ON(MIN).Note 4:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over thespecified analog signal ranges; i.e., V NO = 3V to 0V and 0V to -3V.Note 5:Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation atT A = +25°C.Note 6:Guaranteed by design, not production tested.ELECTRICAL CHARACTERISTICS—Dual Supplies (continued) (V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.) ELECTRICAL CHARACTERISTICS—Single +5V SupplyMAX4051/A, MAX4052/A, MAX4053/A Low-Voltage, CMOS Analog Multiplexers/Switches(V+ = +4.5V to +5.5V, V- = 0V, T A= T MIN to T MAX, unless otherwise noted. Typical values are at T A= +25°C.)M A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 6___________________________________________________________________ ____________________ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)(V+ = +4.5V to +5.5V, V- = 0V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)Note 2:The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.Note 3:?R ON = R ON(MAX)- R ON(MIN).Note 4:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over thespecified analog signal ranges; i.e., V NO = 3V to 0V and 0V to -3V.Note 5:Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation atT A = +25°C.Note 6:Guaranteed by design, not production tested.ELECTRICAL CHARACTERISTICS—Single +3V SupplyMAX4051/A, MAX4052/A, MAX4053/A Low-Voltage, CMOS Analog Multiplexers/Switches(V+ = +3.0V to +3.6V, V- = 0V, T A= T MIN to T MAX, unless otherwise noted. Typical values are at T A= +25°C.)M A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 8_______________________________________________________________________________________ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)(V+ = +3.0V to +3.6V, V- = 0V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)Note 2:The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.Note 3:?R ON = R ON(MAX)- R ON(MIN).Note 4:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over thespecified analog signal ranges; i.e., V NO = 3V to 0V and 0V to -3V.Note 5:Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation atT A = +25°C.Note 6:Guaranteed by design, not production tested.MAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________ _______________________911030-5-31ON-RESISTANCE vs. V COM(DUAL SUPPLIES)5090V COM (V)R O N (?)-13701004080605-40-22411030-5-31ON-RESISTANCE vs. V COM AND TEMPERATURE (DUAL SUPPLIES) 5090V COM (V)R O N (?)-137********605-40-2243005002ON-RESISTANCE vs. V COM (SINGLE SUPPLY)100200V COM (V)R O N (?) 4150250275225 7517512515318002ON-RESISTANCE vs. V COMAND TEMPERATURE (SINGLE SUPPLY) 100V COM (V)R O N (?)4601401601208040153-5-31CHARGE INJECTION vs. V COM-55V COM (V)Q j (p C )-135-40-2240.1OFF-LEAKAGE vs.TEMPERATURE 1000TEMPERATURE (°C)O F F -L E A K A G E (p A )101100-5012525-25075501000.1ON-LEAKAGE vs.TEMPERATURE100010,000TEMPERATURE (°C)O N -L E A K A G E (p A )101100-5012525-25075501000.1SUPPLY CURRENT vs.TEMPERATURE10TEMPERATURE (°C)I +, I - (n A )1-5012525-2507550100__________________________________________Typical Operating Characteristics(V+ = +5V, V- = -5V, GND = 0V, T A = +25°C, unlessotherwise noted.)M A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 10________________________________________________________________ __________________________________________________Typical Operating Characteristics (continued)(V+ = +5V, V- = -5V, GND = 0V, T A = +25°C, unless otherwise noted.)_____________________________________________________________Pi n Descriptions67————31, 2, 4, 5——Note:NO, NC, and COM pins are identical and interchangeable. Any may be considered an input or output; signals pass equallywell in both directions.67123515NO0B–NO3B ———MAX4052/MAX4052AMAX4053/MAX4053A0.01101001k10kTOTAL HARMONIC DISTORTIONvs. FREQUENCY0.1FREQUENCY (Hz)T H D (%)110100PIN0-10-900.010.1110100300FREQUENCY RESPONSE-80-70FREQUENCY (MHz)L O S S (d B )P H A S E (D E G R E E S )-50-60-40-20-3050-40-35-30-20-25-15-5-10INSERTION LOSS50? IN/OUT OFF-ISOLATIONON PHASE__________Applications InformationPower-Supply ConsiderationsOverviewThe MAX4051/MAX4052/MAX4053 and MAX4051A/MAX4052A/MAX4053A construction is typical of most CMOS analog switches. They have three supply pins:V+, V-,and GND. V+ and V- are used to drive the inter-nal CMOS switches and set the limits of the analog volt-age on any switch. Reverse ESD-protection diodes are internally connected between each analog signal pin and both V+ and V-. If any analog signal exceeds V+ or V-, one of these diodes will conduct. During normal operation, these (and other) reverse-biased ESD diodes leak, forming the only current drawn from V+ or V-.Virtually all the analog leakage current comes from the ESD diodes. Although the ESD diodes on a given signal pin are identical, and therefore fairly well balanced,they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins consti-tutes the analog signal path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage cur-rents of either the same or opposite polarity.There is no connection between the analog signal paths and GND.MAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________ ______________________11Table 1. Truth Table/Switch ProgrammingX = Don’t care * ADDC not present on MAX4052.Note:NO and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally wellin either direction.M A X 4051/A , M A X 4052/A , M A X 4053/AV+ and G ND power the internal logic and logic-level translators, and set both the input and output logic lim-its. The logic-level translators convert the logic levels into switched V+ and V- signals to drive the gates of the analog signals. This drive signal is the only connec-tion between the logic supplies (and signals) and the analog supplies. V+ and V- have ESD-protection diodes to GND.The logic-level thresholds are TTL/CMOS compatible when V+ is +5V. As V+ rises, the threshold increases slightly, so when V+ reaches +12V, the threshold is about 3.1V; above the TTL-guaranteed high-level mini-mum of 2.8V, but still compatible with CMOS outputs.Bipolar SuppliesThe se devices operate with bipolar supplies between ±3.0V and ±8V. The V+ and V- supplies need not be symmetrical, buttheir sum cannot exceed the absolute maximum rating of +17V.Single SupplyThese devices operate from a single supply between +3V and +16V when V- is connected to GND. All of the bipolar precautions must be observed. At room temper-ature, they actually “work” with a single supply at near or below +1.7V, although as supply voltage decreases,switch on-resistance and switching times become very high.Overvoltage ProtectionProper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maxi-mum ratings, because stresses beyond the listed rat-ings can cause permanent damage to the devices.Always sequence V+ on first, then V-, followed by the logic inputs (NO) and by COM. If power-supply sequencing is not possible, add two small signal diodes (D1, D2) in series with the supply pins for overvoltage protection (Figure 1).Adding diodes reduces the analog signal range to one diode drop below V+ and one diode drop above V-, but does not affect the devices’ low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between V+ and V-should not exceed 17V. These protection diodes are not recommended when using a single supply if signal levels must extend to ground.High-Frequency PerformanceIn 50?systems, signal response is reasonably flat up to 50MHz (see Typical Operating Characteristics ).Above 20MHz, the on response has several minor peaks which are highly layout dependent. The problem is not turning the switch on, but turning it off. The off-state switch acts like a capacitor, and passes higherfrequencies with less attenuation. At 10MHz, off isola-tion is about -45dB in 50?systems, becoming worse (approximately 20dB per decade) as frequency increases. Higher circuit impedances also make off iso-lation worse. Adjacent channel attenuation is about 3dB above that of a bare IC socket, and is entirely due to capacitive coupling.Low-Voltage, CMOS Analog Multiplexers/Switches 12__________________________________________________________________ ____________________Figure 1. Overvoltage Protection Using External Blocking DiodesMAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________ ______________________13Figure 2. Address Transition Time______________________________________________T est Circuits/Timing DiagramsFigure 3. Enable Switching TimeM A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 14__________________________________________________________________ ____________________MAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________ ______________________15Figure 4. Break-Before-Make Interval Figure 5. Charge InjectionM A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/Switches 16________________________________________________________________ ______________________Figure 6. Off-Isolation, On-Loss, and CrosstalkFigure 7. NO/COM CapacitanceMAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches________________________________________________________________ ______________________17Chip InformationTRANSISTOR COUNT: 161SUBSTRATE CONNECTED TO V+.___________________________________________Ordering Information (continued)M A X 4051/A , M A X 4052/A , M A X 4053/ALow-Voltage, CMOS Analog Multiplexers/SwitchesPackage Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale,CA 94086 (408) 737-7600___________________19?2005 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outlineinformation,go to /packages .) MAX4051/A, MAX4052/A, MAX4053/ALow-Voltage, CMOS AnalogMultiplexers/Switches。
MAX195中文资料

MAX195BCWE MAX195ACDE MAX195BC/D MAX195BEPE MAX195BEWE MAX195AEDE MAX195AMDE MAX195BMDE
* Dice are specified at TA = +25°C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883.
Σ
CALIBRATION DACs SAR 2 CLK SCLK CONV BP/UP/SHDN CS RESET 3 9 1 8 10 CONTROL LOGIC
COMPARATOR
4 6 11 16 14 15
VDDD DGND VSSD VDDA AGND VSSA
MAX195
13 AIN 12 REF 11 VSSD 10 RESET 9 CONV
DYNAMIC PERFORMANCE (fs = 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1) Signal-to-Noise plus Distortion Ratio (Note 2) Total Harmonic Distortion (up to the 5th harmonic) (Note 2) Peak Spurious Noise (Note 2) Conversion Time Clock Frequency (Notes 3, 4) Serial Clock Frequency tCONV fCLK fSCLK SINAD THD TA = +25°C TA = +25°C TA = +25°C 16 (tCLK) 9.4 1.7 5 87 90 -97 -90 -90 dB dB dB µs MHz MHz
MAX1000 用户手册

MAX-1000 矩阵系统用户手册HONEYWELL Co,. Ltd.目录1.综述1.1 简介1.2 CCTV键盘1.3 模拟操作面板1.4 其它设备1.5 本手册所作的前提假定1.6 本手册所用的惯例击键数字范围注意要点监示器信息1.7 厂商联络方式1.8 商标注明2 启动2.1 输入你的选择号码,怎样和为什么?2.2 监示器选择2.3 摄像机选择2.4 PTZ摄像机控制2.5 VCR选择2.6 CCTV键盘控制VCR2.7 摄像机录像2.8 辅助装置和复用器3 扫描序列的使用3.1 什么是扫描序列?什么是扫描序列3.2 启动扫描序列3.3 中止扫描序列3.4 暂停扫描序列3.5 产生新的扫描序列3.6 扫描序列的编辑用新的摄像机选择进行替换删除该摄像机选择插入新的摄像机选择3.7 改变停顿周期3.8 为一个摄像机增加停顿4 宏语言的使用4.1 什么是宏程序?齐投摄像机选择摄像机漫游自动控制4.2 宏语言的执行4.3 产生一个新的宏程序4.4 宏程序的删除4.5 我能编辑一个宏程序吗?5 警报管理5.1 什么是警报?5.2 外部警报输入5.3 摄像机故障警报视频丢失低电平视频5.4 PTZ解码箱故障警报5.5 PTZ解码箱防拆警报5.6 VCR警报5.7 其它装置警报5.8 警报堆栈5.9 在警报堆栈上移位5.10 清除警报6 键盘的其它功能6.1 快速摄像机选择6.2 设置摄像机视场(PTZ预置位) 6.3 调用摄像机视场(PTZ预置位) 6.4 摄像机PTZ复位6.5 选择代用摄像机6.6 隐藏显示的字符6.7 显示SMARTEXTTM7 菜单系统7.1 什么是菜单系统?访问菜单系统退出菜单系统7.2 从菜单上选择移动菜单进入窗口7.3 键盘操作员登记7.4 键盘操作员注销7.5 激活/中止视频输入中止一个摄像机激活一个摄像机7.6 锁定/释放视频输入控制锁定一个PTZ摄像机释放一个PTZ摄像机锁定/释放一个PTZ摄像机7.7 锁定/释放视频输出选项锁定视频输出选项释放视频输出选项锁定/释放视频输出选项7.8 中止/激活警报输入中止警报输入激活警报输入9.3 字符显示定时9.4 监示器黑屏9.5 黑屏暂停9.6 监示器访问9.7 操作员对系统的访问9.8 操作员的级别划分9.9 CCTV键盘定时9.1 0 自动注销9.11 摄像机故障检测视频丢失低电平视频1 0 排除提示10.1 摄像机选择第一章概述1.1简介MAX一1000 CCTV管理系统是一个强功能的计算机控制视频切换矩阵。
EN29LV641L-90WIP资料

This Data Sheet may be revised by subsequent versions ©2005 Eon Silicon Solution, Inc., or modifications due to changes in technical specifications.1FEATURES• Single power supply operation- Full voltage range: 2.7 to 3.6 volts for read, erase and program operations• Low power cons umption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- Less than 1 µA current in standby or automatic sleep mode.• JEDEC standards compatible- Pinout and software compatible with single-power supply Flash standard• Manufactured on 0.18 m process technology• Flexible Sector Architecture:- One hundred and twenty-eight 32K-Word sectors.• Minimum 100K program/erase endurance cycles.• High performance for program and erase - Word program time: 8µs typical - Sector Erase time: 500ms typical - Chip Erase time: 64s typical • Package Options- 48-pin TSOP- 63 ball 11mm x 12mm FBGASoftware features: • Sector Group Protection- Provide locking of sectors to prevent program or erase operations within individual sectors - Additionally, temporary Sector GroupUnprotect allows code changes in previously protected sectors. • Standard DATA# polling and toggle bits feature• Unlock Bypass Program command supported • Sector Erase Suspend / Resume modes: Read and program another Sector during Sector Erase Suspend Mode• Support JEDEC Common Flash Interface (CFI).Hardware features: • RESET# hardware reset pin- Hardware method to reset the device to read mode. • WP# input pin- Write Protect (WP#) function allowsprotection of first or last 32K-word sector, regardless of previous sector protect status • ACC input pin- Acceleration (ACC) function provides accelerated program times for higher throughput for manufacturing.GENERAL DESCRIPTIONThe EN29LV641H/L / EN29LV640U is a 64-Megabit (4,194,304x16), electrically erasable, read/write non-volatile flash memory. Any word can be programmed typically in 8µs. This device is entirely command set compatible with the JEDEC single-power-supply Flash standard.The EN29LV641H/L / EN29LV640U is designed to allow either single Sector or full Chip erase operation, where each Sector Group can be protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV641H/L EN29LV640U 64 Megabit (4096K x 16-bit) Flash Memory, CMOS 3.0 Volt-only Uniform Sector Flash MemoryPRODUCT SELECTOR GUIDEProduct Number EN29LV641H/L / EN29LV640URegulated Voltage Range: V CC=3.0 – 3.6 V 70R Speed OptionFull Voltage Range: V CC=2.7 – 3.6 V 90 Max Access Time (ns) 70 90Max CE# Access Time (ns) 70 90Max OE# Access Time (ns) 30 35BLOCK DIAGRAMCONNECTION DIAGRAMSNote: No RY/BY# pin for TSOP package , V IO should be tied directly to VCC. Note: No WP# pin for FBGA package V IO should be tied directly to VCC.TABLE 1. PIN DESCRIPTIONLOGIC DIAGRAMDQ15 – DQ0A21 – A0Note: WP# pins are for EN29LV641H/L only.RY/BY# is available for EN29LV640U only.Pin Name Function A21-A0 22 Address inputs DQ15-DQ0 16 Data Inputs/Outputs CE# Chip Enable Input OE# Output Enable Input WE# Write Enable InputWP#Hardware Write Protect InputACC Acceleration Input RY/BY# Ready/Busy status output RESET# Hardware Reset Input Pin V cc Supply Voltage (2.7-3.6V)V IO Output Buffer Power Supply this pinshould be tied directly to VCC V ss GroundNCNot Connected to anythingORDERING INFORMATIONEN29LV641 H 90 T I P PACKAGING CONTENT (Blank) = Conventional P = Pb FreeTEMPERATURE RANGE I = Industrial (-40°C to +85°C) C = Commercial (0°C to +70°C) PACKAGET = 48-pin TSOPW= 63-Ball Fine Pitch Ball Grid Array (FBGA) 0.80mm pitch, 11mm x 12mm packageSPEED OPTIONSee Product Selector Guide and Valid Combinations SECTOR for WRITE PROTECT (WP#=0) H = highest address sector protected L = lowest address sector protectedBASE PART NUMBEREN29LV641 / EN29LV640U 64 Megabit(4M x 16-Bit) Uniform Sector Flash Optional Data I/O voltage3V Read, Erase and ProgramPRODUCT SELECTOR GUIDEValid Combinations for TSOP Packages Vcc EN29LV641H 90 EN29LV641L 90 V cc = 2.7V-3.6VEN29LV641H 70R, EN29LV641L 70RTI, TCV cc = 3.0V-3.6VValid Combinations for FBGA Packages Vcc EN29LV640U 90 V cc = 2.7V-3.6V EN29LV640U 70RWI, WCV cc = 3.0V-3.6VTable 2. Sector (Group) Address Tables Sector GroupProtect/UnprotectSector Address Range for Sector EraseSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA0 0 0 0 0 0 0 0 000000–007FFFSA1 0 0 0 0 0 0 1 008000–00FFFFSA2 0 0 0 0 0 1 0 010000–017FFFSG0 00000SA3 0 0 0 0 0 1 1 018000–01FFFFSA4 0 0 0 0 1 0 0 020000–027FFFSA5 0 0 0 0 1 0 1 028000–02FFFFSA6 0 0 0 0 1 1 0 030000–037FFF SG100001SA7 0 0 0 0 1 1 1 038000–03FFFFSA8 0 0 0 1 0 0 0 040000–047FFFSA9 0 0 0 1 0 0 1 048000–04FFFFSA10 0 0 0 1 0 1 0 050000–057FFF SG200010SA11 0 0 0 1 0 1 1 058000–05FFFFSA12 0 0 0 1 1 0 0 060000–067FFFSA13 0 0 0 1 1 0 1 068000–06FFFFSA14 0 0 0 1 1 1 0 070000–077FFF SG300011SA15 0 0 0 1 1 1 1 078000–07FFFFSA16 0 0 1 0 0 0 0 080000–087FFFSA17 0 0 1 0 0 0 1 088000–08FFFFSA18 0 0 1 0 0 1 0 090000–097FFF SG4 00100SA19 0 0 1 0 0 1 1 098000–09FFFFSA20 0 0 1 0 1 0 0 0A0000–0A7FFFSA21 0 0 1 0 1 0 1 0A8000–0AFFFFSA22 0 0 1 0 1 1 0 0B0000–0B7FFF SG5 00101SA23 0 0 1 0 1 1 1 0B8000–0BFFFFSA24 0 0 1 1 0 0 0 0C0000–0C7FFFSA25 0 0 1 1 0 0 1 0C8000–0CFFFFSA26 0 0 1 1 0 1 0 0D0000–0D7FFF SG6 00110SA27 0 0 1 1 0 1 1 0D8000–0DFFFFSA28 0 0 1 1 1 0 0 0E0000–0E7FFFSA29 0 0 1 1 1 0 1 0E8000–0EFFFFSA30 0 0 1 1 1 1 0 0F0000–0F7FFF SG700111SA31 0 0 1 1 1 1 1 0F8000–0FFFFFSector Group A21-A17 Sector A21 A20A19A18A17A16A15Address Range(hexadecimal) SA32 0 1 0 0 0 0 0 100000–107FFFSA33 0 1 0 0 0 0 1 108000–10FFFFSA34 0 1 0 0 0 1 0 110000–117FFFSG8 01000SA35 0 1 0 0 0 1 1 118000–11FFFFSA36 0 1 0 0 1 0 0 120000–127FFFSA37 0 1 0 0 1 0 1 128000–12FFFFSA38 0 1 0 0 1 1 0 130000–137FFF SG9 01001SA39 0 1 0 0 1 1 1 138000–13FFFFSA40 0 1 0 1 0 0 0 140000–147FFFSA41 0 1 0 1 0 0 1 148000–14FFFFSA42 0 1 0 1 0 1 0 150000–157FFF SG10 01010SA43 0 1 0 1 0 1 1 158000–15FFFFSA44 0 1 0 1 1 0 0 160000–167FFFSA45 0 1 0 1 1 0 1 168000–16FFFFSA46 0 1 0 1 1 1 0 170000–177FFF SG11 01011SA47 0 1 0 1 1 1 1 178000–17FFFFSA48 0 1 1 0 0 0 0 180000–187FFFSA49 0 1 1 0 0 0 1 188000–18FFFFSA50 0 1 1 0 0 1 0 190000–197FFF SG12 01100SA51 0 1 1 0 0 1 1 198000–19FFFFSA52 0 1 1 0 1 0 0 1A0000–1A7FFFSA53 0 1 1 0 1 0 1 1A8000–1AFFFFSA54 0 1 1 0 1 1 0 1B0000–1B7FFF SG13 01101SA55 0 1 1 0 1 1 1 1B8000–1BFFFFSA56 0 1 1 1 0 0 0 1C0000–1C7FFFSA57 0 1 1 1 0 0 1 1C8000–1CFFFFSA58 0 1 1 1 0 1 0 1D0000–1D7FFF SG14 01110SA59 0 1 1 1 0 1 1 1D8000–1DFFFFSA60 0 1 1 1 1 0 0 1E0000–1E7FFFSA61 0 1 1 1 1 0 1 1E8000–1EFFFFSA62 0 1 1 1 1 1 0 1F0000–1F7FFF SG15 01111SA63 0 1 1 1 1 1 1 1F8000–1FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA64 1 0 0 0 0 0 0 200000–207FFFSA65 1 0 0 0 0 0 1 208000–20FFFFSA66 1 0 0 0 0 1 0 210000–217FFFSG16 10000SA67 1 0 0 0 0 1 1 218000–21FFFFSA68 1 0 0 0 1 0 0 220000–227FFFSA69 1 0 0 0 1 0 1 228000–22FFFFSA70 1 0 0 0 1 1 0 230000–237FFF SG1710001SA71 1 0 0 0 1 1 1 238000–23FFFFSA72 1 0 0 1 0 0 0 240000–247FFFSA73 1 0 0 1 0 0 1 248000–24FFFFSA74 1 0 0 1 0 1 0 250000–257FFF SG1810010SA75 1 0 0 1 0 1 1 258000–25FFFFSA76 1 0 0 1 1 0 0 260000–267FFFSA77 1 0 0 1 1 0 1 268000–26FFFFSA78 1 0 0 1 1 1 0 270000–277FFF SG1910011SA79 1 0 0 1 1 1 1 278000–27FFFFSA80 1 0 1 0 0 0 0 280000–287FFFSA81 1 0 1 0 0 0 1 288000–28FFFFSA82 1 0 1 0 0 1 0 290000–297FFF SG2010100SA83 1 0 1 0 0 1 1 298000–29FFFFSA84 1 0 1 0 1 0 0 2A0000–2A7FFFSA85 1 0 1 0 1 0 1 2A8000–2AFFFFSA86 1 0 1 0 1 1 0 2B0000–2B7FFF SG2110101SA87 1 0 1 0 1 1 1 2B8000–2BFFFFSA88 1 0 1 1 0 0 0 2C0000–2C7FFFSA89 1 0 1 1 0 0 1 2C8000–2CFFFFSA90 1 0 1 1 0 1 0 2D0000–2D7FFF SG2210110SA91 1 0 1 1 0 1 1 2D8000–2DFFFFSA92 1 0 1 1 1 0 0 2E0000–2E7FFFSA93 1 0 1 1 1 0 1 2E8000–2EFFFFSA94 1 0 1 1 1 1 0 2F0000–2F7FFF SG2310111SA95 1 0 1 1 1 1 1 2F8000–2FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA96 1 1 0 0 0 0 0 300000–307FFFSA97 1 1 0 0 0 0 1 308000–30FFFFSA98 1 1 0 0 0 1 0 310000–317FFFSG24 11000SA99 1 1 0 0 0 1 1 318000–31FFFFSA100 1 1 0 0 1 0 0 320000–327FFFSA101 1 1 0 0 1 0 1 328000–32FFFFSA102 1 1 0 0 1 1 0 330000–337FFF SG25 11001SA103 1 1 0 0 1 1 1 338000–33FFFFSA104 1 1 0 1 0 0 0 340000–347FFFSA105 1 1 0 1 0 0 1 348000–34FFFFSA106 1 1 0 1 0 1 0 350000–357FFF SG26 11010SA107 1 1 0 1 0 1 1 358000–35FFFFSA108 1 1 0 1 1 0 0 360000–367FFFSA109 1 1 0 1 1 0 1 368000–36FFFFSA110 1 1 0 1 1 1 0 370000–377FFF SG27 11011SA111 1 1 0 1 1 1 1 378000–37FFFFSA112 1 1 1 0 0 0 0 380000–387FFFSA113 1 1 1 0 0 0 1 388000–38FFFFSA114 1 1 1 0 0 1 0 390000–397FFF SG28 11100SA115 1 1 1 0 0 1 1 398000–39FFFFSA116 1 1 1 0 1 0 0 3A0000–3A7FFFSA117 1 1 1 0 1 0 1 3A8000–3AFFFFSA118 1 1 1 0 1 1 0 3B0000–3B7FFF SG29 11101SA119 1 1 1 0 1 1 1 3B8000–3BFFFFSA120 1 1 1 1 0 0 0 3C0000–3C7FFFSA121 1 1 1 1 0 0 1 3C8000–3CFFFFSA122 1 1 1 1 0 1 0 3D0000–3D7FFF SG30 11110SA123 1 1 1 1 0 1 1 3D8000–3DFFFFSA124 1 1 1 1 1 0 0 3E0000–3E7FFFSA125 1 1 1 1 1 0 1 3E8000–3EFFFFSA126 1 1 1 1 1 1 0 3F0000–3F7FFF SG31 11111SA127 1 1 1 1 1 1 1 3F8000–3FFFFF Note: The sizes of all sectors are 32K-word.USER MODE DEFINITIONSTABLE 3. BUS OPERATIONSOperation CE#OE#WE#RESET#WP# ACCA21-A0DQ15-DQ0 Read LLHHXXA IN D OUT Write LHLH(Note1)XA IN(Note 3)Accelerated Program L H L H (Note1)V HH A IN(Note 3)CMOS Standby V cc±0.3V X X V cc±0.3VX H X High-ZTTLStandby HXX H X H X High-Z OutputDisableLHH H X X X High-Z HardwareReset X X X L X X X High-ZSector Group Protect L H L V ID H XSA,A6=L,A1=H,A0=L(Note 3)Sector Group Unprotect L H L V ID H XSA,A6=H,A1=H,A0=L(Note 3)TemporarySector GroupUnprotectX X X V ID H X A IN(Note 3)L=logic low= V IL, H=Logic High= V IH, V ID= V HH = 11 ± 0.5V = 10.5 11.5V, X=Don’t Care (eitherL or H, but not floating!), SA=Sector Addresses (A21-A15), D IN=Data In, D OUT=Data Out,A IN=Address InNotes:1. If the system asserts V IL on the WP# pin, the device disables program and erase functions inthe first or last sector independent of whether those sectors were protected or unprotected; ifthe system asserts V IH on the WP# pin, the device reverts to whether the first or last sector waspreviously protected or unprotected. If ACC = V HH, all sectors will be unprotected.2. Please refer to “Sector Group Protection & Unprotection”, Flowchart 6a and Flowchart 6b.3. D IN or D OUT as required by command sequence, data polling, or sector protect algorithm.Read ModeThe device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithmAfter the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Sector Erase Suspend mode, the system may once again read arraydata with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the “Reset Command” for additional details.Output Disable ModeWhen the OE# pin is at a logic high level (V IH), the output from the device is disabled. The output pins are placed in a high impedance state.Standby ModeThe device has a CMOS-compatible standby mode, which reduces the c urrent to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC c urrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.Automatic Sleep ModeThe device has an automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.Writing Command SequencesTo write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to V IL, and OE# to V IH.The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four.The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the “Command Definitions” for all the available commands.Autoselect Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID(10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode. Note that a Reset command is required to return to read mode when the device is in the autoselect mode.TABLE 4. Autoselect Codes (Using High Voltage, V ID )L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector AddressesNote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh.2. A9 = V ID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command AutoselectMode.ACC: Accelerated Program OperationThe device offers accelerated program operation which enables the programming in higher speed. When ACC is raised to V HH , the memory automatically enters the Unlock Bypass mode (please refer to “Command Definitions”), temporarily unprotects every protected sector groups , and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When ACC returns to V IH or V IL , normal operation resumes. The transitions from V IH or V IL to V HH and from V HH to V IH or V IL must be slower than t VHH , see Figure 5.Note that the ACC pin must not be left floating or unconnected. In addition, ACC pin must not be at V HH for operations other than accelerated program. It could cause the device to be damaged. Never raise this pin to V HH from any mode except Read mode; otherwise the memory may be left in an indeterminate state.A 0.1µF capacitor should be connected between the ACC pin and the V SS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program.RESET#: Hardware ResetWhen RESET# is driven low for t RP , all output pins are tristates. All commands written in the internal state machine are reset to reading array data.Please refer to timing diagram for RESET# pin in “AC Characteristics”.Sector Group Protection & UnprotectionThe hardware sector group protection feature disables both program and erase operations in any sector group. The hardware chip unprotection feature re-enables both program and erase operations in previouslyDescription CE# OE# WE# A21toA15 A14 to A10A92A8A7A6A5 to A2A1 A0 DQ15 to DQ0H1XX1Ch Manufacturer ID: Eon L L H X X V IDLX L XL LXX7FhAutoselect Device ID L L H X X V IDX X L X L H 22D7h Sector Protection VerificationL L H SA X V IDX X L X H LXX01h(Protected)XX00h(Unprotected)protected sector group. A sector group consists of four adjacent sectors that would be protected at the same time. Please see Table 2 which show the organization of sector groups.There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 6a and 6b for the algorithm and Figure 11 for the timings.When doing Sector Group Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle.The second method is for programming equipment. This method requires V ID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document, the Datasheet Supplement of EN29LV641H/L / EN29LV640U, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.WP#: Write ProtectThe Write Protect function provides a hardware method to protect the first or last sector against erase and program without using V ID.When WP# is Low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in “Sector Group Protection & Unprotection”, Program and Erase operations in these sectors are ignored.When WP# is High, the device reverts to the previous protection status of the first or last sector. Program and Erase operations can now modify the data in those sectors unless the sector is protected using Sector Group Protection.Note that the WP# pin must not be left floating or unconnected.Temporary Sector Group UnprotectThis feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Group Unprotect mode is activated by setting the RESET# pin to V I D. During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. Once V I D is removed from the RESET# pin, all the previously protected sector groups are protected again. See accompanying flowchart and timing diagrams in Figure 10 for more details.StartReset#=V ID(note 1) Perform Erase or ProgramOperationsRESET#=V IH Temporary Sector Group Unprotect Completed (note 2)Notes:1. All protected sector groups are unprotected. (If WP#=V IL, the first or last sector will remain protected.)2. Previously protected sector groups are protected again.COMMON FLASH INTERFACE (CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data.The system can read CFI information at the addresses given in Tables 5-8.The upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAddresses Data Description10h 11h 12h 0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 0002h0000hPrimary OEM Command Set15h 16h 0040h0000hAddress for Primary Extended Table17h 18h 0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 0000h0000hAddress for Alternate OEM Extended Table (00h = none exists)Table 6. System Interface StringAddresses Data Description1Bh 0027h Vcc Min (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Ch 0036h Vcc Max (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Dh 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 0003h Typical timeout per single byte/word write 2NµS20h 0000h Typical timeout for Min, size buffer write 2NµS (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)23h 0005h Max. timeout for byte/word write 2N times typical24h 0000h Max. timeout for buffer write 2N times typical25h 0002h Max. timeout per individual block erase 2N times typical26h 0000h Max timeout for full chip erase 2N times typical (00h = not supported) Table 7. Device Geometry DefinitionAddresses Data Description27h 0017h Device Size = 2Nbytes 28h 29h 0001h0000h Flash Device Interface description (refer to CFI publication 100)2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100) 31h 32h 33h 34h 007Eh 0000h0000h 0001h Erase Block Region 2 Information35h 36h 37h 38h 0000h 0000h0000h 0000hErase Block Region 3 Information39h3Ah3Bh3Ch0000h 0000h 0000h 0000h Erase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAddresses Data Description40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII45h 0004hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0004hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00A5hMinimum ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 4Eh 00B5hMaximum ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV4Fh 00XXh 00h = Uniform Sector DevicesHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen V CC is less than V LKO, the device does not accept any write cycles. This protects data during V CC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than V LKO.Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE# = V IL, CE# = V IH, or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = V IL, WE#= V IL and OE# = V IH, the device will not accept commands on the rising edge of WE#.COMMAND DEFINITIONSThe operations of the device are selected by one or more commands written into the command register. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV641H/L / EN29LV640U Command DefinitionsBus Cycles (Note 1-2)1stCycle 2ndCycle3rdCycle4thCycle5thCycle6thCycleCommand Sequence C y c l e sRead (Note 3)1RA RD Reset 1xxx F0 Manufacturer ID 4555 AA 2AA 55 55590000 1007F 1CDevice ID 4555 AA 2AA 55 55590 X01 22D7 A u t o s e l e c tSector Protect Verify (Note 4)4555 AA 2AA 55 55590(SA)X02XX00 XX01Program 4555 AA 2AA 55 555A0 PA PD Unlock Bypass 3555 AA 2AA 55 55520 Unlock Bypass Program2XXX A0 PA PD Unlock Bypass Reset 2XXX90XXX00Chip Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 55510Sector Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 SA 30 Sector Erase Suspend 1BA B0 Sector Erase Resume 1BA 30 CFI Query 15598Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified (in Autoselect mode).Address bits A21-A15 uniquely select any Sector.Notes:1. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.2. Unless otherwise noted, address bits A21-A15 are don’t cares.3. No unlock or command cycles required when device is in read mode.4. The data is 00h for an unprotected sector group and 01h for a protected sector group.。
BC-4000中文版(详细)

BC-4000系列
用户手册
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3.2 标签菜单 ........................................................................................................................................... 15 3.2.1 标签打印设定 ............................................................................................................................. 15 3.2.2 标签格式编辑 ............................................................................................................................. 18
第4章登录模式
4.1 进入/退出登录模式 .............................................................................................. 42
MAX4310中文资料

General Description
The MAX4310–MAX4315 single-supply mux-amps combine high-speed operation, low-glitch switching, and excellent video specifications. The six products in this family are differentiated by the number of multiplexer inputs and the gain configuration. The MAX4310/MAX4311/MAX4312 integrate 2-/4-/8-channel multiplexers, respectively, with an adjustable gain amplifier optimized for unity-gain stability. The MAX4313/MAX4314/MAX4315 integrate 2-/4-/8-channel multiplexers, respectively, with a +2V/V fixed-gain amplifier. All devices have 40ns channel switching time and low 10mVp-p switching transients, making them ideal for video-switching applications. They operate from a single +4V to +10.5V supply, or from dual supplies of ±2V to ±5.25V, and they feature Rail-to-Rail® outputs and an input common-mode voltage range that extends to the negative supply rail.
MAX4090中文资料

MIN TYP MAX
2.7
5.5
6.5
10
6.5
10
0.15
1
0.27 0.38 0.47
VCLP
1.45
22.5
35
3
1.9
2
2.1
60
80
2.55
2.7
4.3
4.6
VCLP 0.47
45
85
40
85
110
VCC x 0.3
VCC x 0.7
0.003
1
4
2
UNITS V
mA
µA V V µA MΩ V/V dB
Note 1: VCLP is the input clamp voltage as defined in the DC Electrical Characteristics table.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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General DescriptionThe MAX6412–MAX6420 low-power microprocessor supervisor circuits monitor system voltages from 1.6V to 5V. These devices are designed to assert a reset signal whenever the V CC supply voltage or RESET IN falls below its reset threshold or the manual reset input is asserted.The reset output remains asserted for the reset timeout period after V CC and RESET IN rise above the reset threshold and the manual reset input is deasserted. The reset timeout is externally set by a capacitor to provide more flexibility.The MAX6412/MAX6413/MAX6414 feature fixed thresholds from 1.575V to 5V in approximately 100mV increments and a manual reset input. The MAX6415/MAX6416/MAX6417are offered with an adjustable reset input that can monitor voltages down to 1.26V and the MAX6418/MAX6419/MAX6420 are offered with one fixed input and one adjustable input to monitor dual-voltage systems.The MAX6412/MAX6415/MAX6418 have an active-low,push-pull reset output. The MAX6413/MAX6416/MAX6419 have an active-high, push-pull reset output and the MAX6414/MAX6417/MAX6420 have an active-low, open-drain reset output. All of these devices are offered in a SOT23-5 package and are fully specified from -40°C to +125°C.ApplicationsAutomotive Medical Equipment Intelligent Instruments Portable EquipmentBattery-Powered Computers/Controllers Embedded Controllers Critical µP Monitoring Set-Top Boxes ComputersFeatures♦Monitor System Voltages from 1.6V to 5V ♦Capacitor-Adjustable Reset Timeout Period ♦Manual Reset Input (MAX6412/MAX6413/MAX6414)♦Adjustable Reset Input Option (MAX6415–MAX6420)♦Dual-Voltage Monitoring(MAX6418/MAX6419/MAX6420)♦Low Quiescent Current (1.7µA, typ)♦3 RESET Output OptionsPush-Pull RESET Push-Pull RESET Open-Drain RESET♦Guaranteed Reset Valid to V CC = 1V ♦Power-Supply Transient Immunity ♦Small SOT23-5 PackagesMAX6412–MAX6420Low-Power, Single/Dual-Voltage µP Reset Circuits with Capacitor-Adjustable Reset Timeout Delay________________________________________________________________Maxim Integrated Products1Ordering InformationPin Configuration19-2336; Rev 2; 12/05For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Typical Operating Circuit appears at end of data sheet.Selector Guide appears at end of data sheet.Note: The MAX6412/MAX6413/MAX6414 and MAX6418/MAX6419/MAX6420 are available with factory-set V CC reset thresholds from 1.575V to 5.0V in approximately 0.1V incre-ments. Insert the desired nominal reset threshold suffix (from Table 1) into the blanks following the letters UK. There are 33standard versions with a required order increment of 2500pieces. Sample stock is generally held on standard versions only (see Standard Versions Table). Required order increment is 10,000 pieces for nonstandard versions. Contact factory for availability. All devices are available in tape-and-reel only. Devices are available in both leaded and lead-free packaging.Specify lead-free by replacing “-T” with “+T” when ordering.M A X 6412–M A X 6420with Capacitor-Adjustable Reset Timeout Delay2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V CC = 1V to 5.5V, T A = T MIN to T MAX , unless otherwise specified. Typical values are at V CC = 5V and T A = +25°C.) (Note 1)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.All Voltages Referenced to GNDV CC ........................................................................-0.3V to +6.0V SRT, MR , RESET IN....................................-0.3V to (V CC + 0.3V)RESET, RESET (Push-Pull).........................-0.3V to (V CC + 0.3V)RESET (Open-Drain).............................................-0.3V to +6.0V Input Current (All Pins).....................................................±20mA Output Current (RESET , RESET)......................................±20mAContinuous Power Dissipation (T A = +70°C)5-Pin SOT23-5 (derate 7.1mW/°C above +70°C)........571mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX6412–MAX6420with Capacitor-Adjustable Reset Timeout Delay_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)(V CC = 1V to 5.5V, T A = T MIN to T MAX , unless otherwise specified. Typical values are at V CC = 5V and T A = +25°C.) (Note 1)Typical Operating Characteristics(V CC = 5V, C SRT = 1500pF, T A = +25°C, unless otherwise noted.)432100312456SUPPLY CURRENT vs.SUPPLY VOLTAGESUPPLY VOLTAGE (V)S U P P L Y C U R R E N T (µA )01.00.52.01.53.02.53.5-5025-255075100125SUPPLY CURRENT vs.TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (µA )0.1110010100010,0000.0010.10.011101001000RESET TIMEOUT PERIOD vs. C SRTM A X 6412-20 t o c 03C SRT (nF)R E S E T T I M E O U T P E R I O D (m s )M A X 6412–M A X 6420with Capacitor-Adjustable Reset Timeout Delay4_______________________________________________________________________________________4.054.104.204.154.254.30-50-25255075100125RESET TIMEOUT PERIOD vs. TEMPERATURETEMPERATURE (°C)R E S E T T I M E O U T P E R I O D (m s )RESET TIMEOUT PERIOD vs. TEMPERATURE200250350300500550450400600R E S E T T I M E O U T P E R I O D (µs )-5025-255075100125TEMPERATURE (°C)1.2501.2601.2551.2701.2651.2751.280-502550-2575100125RESET IN THRESHOLD VOLTAGEvs. TEMPERATUREM A X 6412-20 t o c 06TEMPERATURE (°C)R E S E T I N T H R E S H O L D V O L T A G E (V)05025100751501251754002006008001000MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVERESET THRESHOLD OVERDRIVE (mV)T R A N S I E N T D U R A T I O N (µs )Typical Operating Characteristics (continued)(V CC = 5V, C SRT = 1500pF, T A = +25°C, unless otherwise noted.)Detailed DescriptionThe MAX6412–MAX6420 low-power microprocessor (µP) supervisory circuits provide maximum adjustability for supply-voltage monitoring and reset functionality. In addition, the MAX6412–MAX6420 reset timeout period is adjustable using an external capacitor.The MAX6412/MAX6413/MAX6414 have factory-trimmed reset threshold voltages in approximately 100mV increments from 1.575V to 5.0V with a manual reset input. The MAX6415/MAX6416/MAX6417 contain a reset threshold that can be adjusted to any voltage above 1.26V using external resistors. The MAX6418/MAX6419/MAX6420 offer both a factory-trimmed reset threshold and an adjustable reset threshold input for dual-voltage monitoring.A reset signal is asserted when V CC and/or RESET IN falls below the preset values or when MR is asserted.The reset remains asserted for an externally pro-grammed interval after V CC and/or RESET IN has risen above the reset threshold or MR is deasserted.Reset OutputThe reset output is typically connected to the reset input of a µP. A µP’s reset input starts or restarts the µPin a known state. The MAX6412–MAX6420 µP supervi-sory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions (see Typical Operating Circuit ). F or the MAX6413, MAX6416, and MAX6419, RESET changes from low to high whenever V CC or RESET IN drops below the reset threshold voltages. Once RESET IN and V CC exceed their respective reset threshold volt-age(s), RESET remains high for the reset timeout period,then goes low.On power-up, once V CC reaches 1V, RESET is guaran-teed to be a logic high. For applications requiring valid reset logic when V CC is less than 1V, see the section Ensuring a Valid RESET/RESET Output Down to V CC = 0.The active-low RESET output of the remaining supervi-sors is the inverse of the MAX6413, MAX6416, and MAX6419 active-high RESET output and is guaranteed valid for V CC ≥1V.Reset ThresholdThe MAX6415–MAX6420 monitor the voltage on RESET IN with an external resistor voltage-divider (F igure 1).MAX6412–MAX6420with Capacitor-Adjustable Reset Timeout Delay_______________________________________________________________________________________5Pin DescriptionM A X 6412–M A X 6420Use the following formula to calculate the externally monitored voltage (V MON_TH ):V MON_TH = V RST ✕(R1 + R2)/R2where V MON_TH is the desired reset threshold voltage and V RST is the reset input threshold (1.26V). Resistors R1 and R2 can have very high values to minimize cur-rent consumption due to low leakage currents. Set R2to some conveniently high value (1M Ω, for example)and calculate R1 based on the desired monitored volt-age, using the following formula:R1 = R2 x (V MON_TH /V RST - 1) (Ω)Manual Reset Input(MAX6412/MAX6413/MAX6414)Many µP based products require manual reset capabil-ity, allowing the operator, a technician, or external logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low and for the reset timeout period after MR returns high.The MR has an internal 20k Ωpullup resistor so it can be left open if not used. Connect a normally open momentary switch from MR to ground to create a man-ual reset function (external debounce circuitry is not required for long reset timeout periods).A manual reset option can easily be implemented with the MAX6415–MAX6420 by connecting a normally open momentary switch in parallel with R2 (Figure 2). When the switch is closed, the voltage on RESET IN goes to zero,initiating a reset. Similar to the MAX6412/MAX6413/MAX6414 manual reset, reset remains asserted while the switch is closed and for the reset timeout period after the switch is opened.Monitoring Voltages Other than V CC(MAX6415/MAX6416/MAX6417)The MAX6415/MAX6416/MAX6417 contain an adjustable reset threshold input. These devices can be used to monitor voltages other than V CC . Calculate V MON_TH as shown in the Reset Threshold section. (See Figure 3.)with Capacitor-Adjustable Reset Timeout Delay6_______________________________________________________________________________________Figure 1. Calculating the Monitored Threshold Voltage (V MON_TH )MAX6415–MAX6420Figure 3. Monitoring External VoltagesDual-Voltage Monitoring(MAX6418/MAX6419/MAX6420) The MAX6418/MAX6419/MAX6420 contain both facto-ry-trimmed threshold voltages and an adjustable reset threshold input, allowing the monitoring of two voltages, V CC and V MON_TH(see F igure 4). Reset is asserted when either of the voltages falls below its respective threshold voltage.Application InformationSelecting a Reset Capacitor The reset timeout period is adjustable to accommodate a variety of µP applications. Adjust the reset timeout period (t RP) by connecting a capacitor (C SRT) between SRT and ground. Calculate the reset timeout capacitor as follows:C SRT= (t RP- 275µs) / (2.73 ✕106)where t RP is in seconds and C SRT is in Farads The reset delay time is set by a current/capacitor-con-trolled ramp compared to an internal 0.65V reference.An internal 240nA ramp current source charges the external capacitor. The charge to the capacitor is cleared when a reset condition is detected. Once thereset condition is removed, the voltage on the capacitor ramps according to the formula: dV/dt = I/C. The C SRT capacitor must ramp to 0.65V to deassert the reset.C SRT must be a low-leakage (<10nA) type capacitor, ceramic is recommended.Operating as a Voltage DetectorThe MAX6412–MAX6420 can be operated in a voltage detector mode by floating the SRT pin. The reset delaytimes for V CC rising above or falling below the thresholdare not significantly different. The reset output is deasserted smoothly without false pulses.MAX6412–MAX6420with Capacitor-Adjustable Reset Timeout Delay _______________________________________________________________________________________7M A X 6412–M A X 6420Interfacing to Other Voltages for LogicCompatibilityThe open-drain outputs of the MAX6414/MAX6417/MAX6420 can be used to interface to µPs with other logic levels. As shown in Figure 5, the open-drain out-put can be connected to voltages from 0 to 5.5V. This allows for easy logic compatibility to various micro-processors.Negative-Going V CC TransientsIn addition to issuing a reset to the µP during power-up,power-down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going transients (glitches). The Maximum Transient Duration vs.Reset Threshold Overdrive graph in the Typical Operating Characteristics shows this relationship.The area below the curve of the graph is the region in which these devices typically do not generate a reset pulse. This graph was generated using a negative-going pulse applied to V CC , starting above the actual reset threshold (V TH ) and ending below it by the magni-tude indicated (reset-threshold overdrive). As the mag-nitude of the transient decreases (farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a V CC transient that goes 100mV below the reset threshold and lasts 50µs or less will not cause a reset pulse to be issued.Ensuring a Valid RESET or RESETDown to V CC = 0When V CC falls below 1V, RESET /RESET current sink-ing (sourcing) capabilities decline drastically. In the case of the MAX6412, MAX6415, and MAX6418, high-impedance CMOS-logic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most µPs and other circuitry do not operate with V CC below 1V.In those applications where RESET must be valid down to 0, adding a pulldown resistor between RESET and ground sinks any stray leakage currents, holding RESET low (Figure 6). The value of the pulldown resis-tor is not critical; 100k Ωis large enough not to load RESET and small enough to pull RESET to ground. For applications using the MAX6413, MAX6416, and MAX6419, a 100k Ωpullup resistor between RESET and V CC will hold RESET high when V CC falls below 1V (Figure 7). Open-drain RESET versions are not recom-mended for applications requiring valid logic for V CC down to 0.with Capacitor-Adjustable Reset Timeout Delay8_______________________________________________________________________________________Figure 5. MAX6414/MAX6417/MAX6420 Open-Drain RESETOutput Allows use with Multiple SuppliesFigure 6. Ensuring RESET Valid to V CC= 0Figure 7. Ensuring RESET Valid to V CC = 0Layout ConsiderationSRT is a precise current source. When developing the layout for the application, be careful to minimize board capacitance and leakage currents around this pin.Traces connected to SRT should be kept as short as possible. Traces carrying high-speed digital signals and traces with large voltage potentials should be rout-ed as far from SRT as possible. Leakage current and stray capacitance (e.g., a scope probe) at this pin could cause errors in the reset timeout period. When evaluating these parts, use clean prototype boards to ensure accurate reset periods.RESET IN is a high-impedance input, which is typically driven by a high-impedance resistor-divider network (e.g., 1M Ωto 10M Ω). Minimize coupling to transient sig-nals by keeping the connections to this input short. Any DC leakage current at RESET IN (e.g., a scope probe)causes errors in the programmed reset threshold.Chip InformationTRANSISTOR COUNT: 325PROCESS: BiCMOSMAX6412–MAX6420with Capacitor-Adjustable Reset Timeout Delay_______________________________________________________________________________________9Table 1. Reset Voltages Suffix TableM A X 6412–M A X 6420with Capacitor-Adjustable Reset Timeout Delay10______________________________________________________________________________________Contact factory for availability of nonstandard versions.MAX6412–MAX6420with Capacitor-Adjustable Reset Timeout Delay______________________________________________________________________________________11Typical Operating CircuitM A X 6412–M A X 6420with Capacitor-Adjustable Reset Timeout DelayMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.12____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2005 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products, Inc.S O T -23 5L .E PSPackage Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)。