通信工程专业英语论文
介绍通信工程专业英语作文
Introduction to Communication EngineeringCommunication Engineering is a vibrant and rapidly evolving field that deals with the transmission of information across various mediums, from wired connections to wireless networks. It encompasses a wide range of technologies and systems, including telephones, radios, televisions, satellites, and the internet, all essential components of modern society.The core of communication engineering lies in understanding the principles of signal processing and information theory. This involves the study of analog and digital signals, modulation techniques, coding and decoding methods, and the design of efficient communication systems. Additionally, communication engineers must stay abreast of emerging technologies such as 5G, the Internet of Things (IoT), and satellite communications, which are revolutionizing the way we connect and interact.A degree in communication engineering opens up a plethora of career opportunities. Graduates can find employment in telecommunications companies, network infrastructure providers, broadcasting organizations, or even in research and development roles within the industry. Moreover, with the increasing demand for high-speed and reliable communication systems, the job prospects in this field are expected to grow significantly in the coming years.In conclusion, Communication Engineering is a fascinating and challenging field that plays a pivotal role in connecting people and driving technological advancements. It requires a blend of theoretical knowledge, practical skills, and a keen interest in staying updated with the latest trends and developments.通信工程专业介绍通信工程专业是一个充满活力和快速发展的领域，涉及信息在各种媒介中的传输，从有线连接到无线网络。
通信工程英语专业论文
On the deployment of VoIP in Ethernet networks:methodology and case studyKhaled Salah, Department of Information and Computer Science, King Fahd University of Petroleum and Minerals, P.O. Box 5066, Dhahran 31261, Saudi Arabia Received 25 May 2004; revised 3 June 2005; accepted 3 June 2005. Available online 1 July 2005.AbstractDeploying IP telephony or voice over IP (V oIP) is a major and challenging task for data network researchers and designers. This paper outlines guidelines and a step-by-step methodology on how V oIP can be deployed successfully. The methodology can be used to assess the support and readiness of an existing network. Prior to the purchase and deployment of V oIP equipment, the methodology predicts the number of V oIP calls that can be sustained by an existing network while satisfying QoS requirements of all network services and leaving adequate capacity for future growth. As a case study, we apply the methodology steps on a typical network of a small enterprise. We utilize both analysis and simulation to investigate throughput and delay bounds. Our analysis is based on queuing theory, and OPNET is used for simulation. Results obtained from analysis and simulation are in line and give a close match. In addition, the paper discusses many design and engineering issues. These issues include characteristics of V oIP traffic and QoS requirements, V oIP flow and call distribution, defining future growth capacity, and measurement and impact of background traffic.Keywords: Network Design，Network Management，V oIP，Performance Evaluation，Analysis，Simulation，OPNET1 IntroductionThese days a massive deployment of V oIP is taking place over data networks. Most of these networks are Ethernet based and running IP protocol. Many network managers are finding it very attractive and cost effective to merge and unify voice and data networks into one. It is easier to run, manage, and maintain. However, one has to keep in mind that IP networks are best-effort networks that were designed for non-real time applications. On the other hand, V oIP requires timely packet delivery with low latency, jitter, packet loss, and sufficient bandwidth. To achieve this goal, an efficient deployment of V oIP must ensure these real-time traffic requirements can be guaranteed over new or existing IP networks. When deploying a new network service such as V oIP over existing network, many network architects, managers, planners, designers, and engineers are faced with common strategic, and sometimes challenging, questions. What are the QoS requirements for V oIP? How will the new V oIP load impact the QoS for currently running network services and applications? Will my existing network support V oIP and satisfy the standardized QoS requirements? If so, how many V oIP calls can the network support before upgrading prematurely any part of the existing network hardware? These challenging questions have led to the development of some commercial tools for testing the performance of multimedia applications in data networks. A list of the available commercial tools that support V oIP is listed in [1,2]. For the most part, these tools use two common approaches in assessing the deployment of V oIP into the existing network. One approach is based on first performing network measurements and then predicting the network readiness for supporting V oIP. The prediction of the network readiness is based on assessing the health of network elements. The second approach is based on injecting real V oIP traffic into existing network and measuring the resulting delay, jitter, and loss. Other than the cost associated with the commercial tools, none of the commercial tools offer a comprehensive approach for successful V oIP deployment. I n particular, none gives any prediction for the total number of calls that can be supported by the network taking into account important design and engineering factors. These factors include V oIP flow and call distribution, future growth capacity, performance thresholds, impact of V oIP on existing network services and applications, and impact backgroundtraffic on V oIP. This paper attempts to address those important factors and layout a comprehensive methodology for a successful deployment of any multimedia application such as V oIP and video conferencing. However, the paper focuses on V oIP as the new service of interest to be deployed. The paper also contains many useful engineering and design guidelines, and discusses many practical issues pertaining to the deployment of V oIP. These issues include characteristics of V oIP traffic and QoS requirements, V oIP flow and call distribution, defining future growth capacity, and measurement and impact of background traffic. As a case study, we illustrate how our approach and guidelines can be applied to a typical network of a small enterprise. The rest of the paper is organized as follows. Section 2 presents a typical network topology of a small enterprise to be used as a case study for deploying V oIP. Section 3 outlines practical eight-step methodology to deploy successfully V oIP in data networks. Each step is described in considerable detail. Section 4 describes important design and engineering decisions to be made based on the analytic and simulation studies. Section 5 concludes the study and identifies future work.2 Existing networkFig. 1 illustrates a typical network topology for a small enterprise residing in ahigh-rise building. The network shown is realistic and used as a case study only; however, our work presented in this paper can be adopted easily for larger and general networks by following the same principles, guidelines, and concepts laid out in this paper. The network is Ethernet-based and has two Layer-2 Ethernet switches connected by a router. The router is Cisco 2621, and the switches are 3Com Superstack 3300. Switch 1 connects Floors 1 and 2 and two servers; while Switch 2 connects Floor 3 and four servers. Each floor LAN is basically a shared Ethernet connecting employee PCs with workgroup and printer servers. The network makes use of VLANs in order to isolate broadcast and multicast traffic. A total of five LANs exist. All VLANs are port based. Switch 1 is configured such that it has three VLANs. VLAN1 includes the database and file servers. VLAN2 includes Floor 1. VLAN3 includes Floor2. On the other hand, Switch 2 is configured to have two VLANs. VLAN4 includes the servers for E-mail, HTTP, Web and cache proxy, and firewall. VLAN5 includes Floor 3. All the links are switched Ethernet 100 Mbps full duplex except for the links for Floors 1–3 which are shared Ethernet 100 Mbps half duplex.3 Step-by-step methodologyFig. 2 shows a flowchart of a methodology of eight steps for a successful V oIP deployment. The first four steps are independent and can be performed in parallel. Before embarking on the analysis and simulation study, in Steps 6 and 7, Step 5 must be carried out which requires any early and necessary redimensioning or modifications to the existing network. As shown, both Steps 6 and 7 can be done in parallel. The final step is pilot deployment.3.1. VoIP traffic characteristics, requirements, and assumptionsFor introducing a new network service such as V oIP, one has to characterize first the nature of its traffic, QoS requirements, and any additional components or devices. For simplicity, we assume a point-to-point conversation for all V oIP calls with no call conferencing. For deploying V oIP, a gatekeeper or Call Manager node has to be added to the network [3,4,5]. The gatekeeper node handles signaling for establishing, terminating, and authorizing connections of all V oIP calls. Also a V oIP gateway is required to handle external calls. A V oIP gateway is responsible for converting V oIP calls to/from the Public Switched Telephone Network (PSTN). As an engineering and design issue, the placement of these nodes in the network becomes crucial. We will tackle this issue in design step 5. Other hardware requirements include a V oIP client terminal, which can be a separate V oIP device, i.e. IP phones, or a typical PC or workstation that is V oIP-enabled. A V oIP-enabled workstation runs V oIP software such as IP Soft Phones .Fig. 3 identifies the end-to-end V oIP components from sender to receiver [9]. The first component is the encoder which periodically samples the original voice signal and assigns a fixed number of bits to each sample, creating a constant bit rate stream. The traditional sample-based encoder G.711 uses Pulse Code Modulation(PCM) to generate 8-bit samples every 0.125 ms, leading to a data rate of 64 kbps . The packetizer follows the encoder and encapsulates a certain number of speech samples into packets and adds the RTP, UDP, IP, and Ethernet headers. The voice packets travel through the data network. An important component at the receiving end, is the playback buffer whose purpose is to absorb variations or jitter in delay and provide a smooth playout. Then packets are delivered to the depacketizer and eventually to the decoder which reconstructs the original voice signal. We will follow the widely adopted recommendations of H.323, G.711, and G.714 standards for V oIP QoS requirements.Table 1 compares some commonly used ITU-T standard codecs and the amount of one-way delay that they impose. To account for upper limits and to meet desirable quality requirement according to ITU recommendation P.800, we will adopt G.711u codec standards for the required delay and bandwidth. G.711u yields around 4.4 MOS rating. MOS, Mean Opinion Score, is a commonly used V oIP performance metric given in a scale of 1–5, with 5 is the best. However, with little compromise to quality, it is possible to implement different ITU-T codecs that yield much less required bandwidth per call and relatively a bit higher, but acceptable, end-to-end delay. This can be accomplished by applying compression, silence suppression, packet loss concealment, queue management techniques, and encapsulating more than one voice packet into a single Ethernet frame.3.1.1. End-to-end delay for a single voice packetFig. 3 illustrates the sources of delay for a typical voice packet. The end-to-end delay is sometimes referred to by M2E or Mouth-to-Ear delay. G.714 imposes a maximum total one-way packet delay of 150 ms end-to-end for V oIP applications . In [22], a delay of up to 200 ms was considered to be acceptable. We can break this delay down into at least three different contributing components, which are as follows (i) encoding, compression, and packetization delay at the sender (ii) propagation, transmission and queuing delay in the network and (iii) buffering, decompression, depacketization, decoding, and playback delay at the receiver.3.1.2. Bandwidth for a single callThe required bandwidth for a single call, one direction, is 64 kbps. G.711 codec samples 20 ms of voice per packet. Therefore, 50 such packets need to be transmitted per second. Each packet contains 160 voice samples in order to give 8000 samples per second. Each packet is sent in one Ethernet frame. With every packet of size 160 bytes, headers of additional protocol layers are added. These headers include RTP+UDP+IP+Ethernet with preamble of sizes 12+8+20+26, respectively. Therefore, a total of 226 bytes, or 1808 bits, needs to be transmitted 50 times per second, or 90.4 kbps, in one direction. For both directions, the required bandwidth for a single call is 100 pps or 180.8 kbps assuming a symmetric flow.3.1.3. Other assumptionsThroughout our analysis and work, we assume voice calls are symmetric and no voice conferencing is implemented. We also ignore the signaling traffic generated by the gatekeeper. We base our analysis and design on the worst-case scenario for V oIP call traffic. The signaling traffic involving the gatekeeper is mostly generated prior to the establishment of the voice call and when the call is finished. This traffic is relatively small compared to the actual voice call traffic. In general, the gatekeeper generates no or very limited signaling traffic throughout the duration of the V oIP call for an already established on-going call. In this paper, we will implement no QoS mechanisms that can enhance the quality of packet delivery in IP networks. A myriadof QoS standards are available and can be enabled for network elements. QoS standards may include IEEE 802.1p/Q, the IETF’s RSVP, and DiffServ. Analysis of implementation cost, complexity, management, and benefit must be weighed carefully before adopting such QoS standards. These standards can be recommended when the cost for upgrading some network elements is high and the network resources are scarce and heavily loaded.3.2. VoIP traffic flow and call distributionKnowing the current telephone call usage or volume of the enterprise is an important step for a successful V oIP deployment. Before embarking on further analysis or planning phases for a V oIP deployment, collecting statistics about of the present call volume and profiles is essential. Sources of such information are organization’s PBX, telephone records and bills. Key characteristics of existing calls can include the number of calls, number of concurrent calls, time, duration, etc. It is important to determine the locations of the call endpoints, i.e. the sources and destinations, as well as their corresponding path or flow. This will aid in identifying the call distribution and the calls made internally or externally. Call distribution must include percentage of calls within and outside of a floor, building, department, or organization. As a good capacity planning measure, it is recommended to base the V oIP call distribution on the busy hour traffic of phone calls for the busiest day of a week or a month. This will ensure support of the calls at all times with high QoS for all V oIP calls. When such current statistics are combined with the projected extra calls, we can predict the worst-case V oIP traffic load to be introduced to the existing network.Fig. 4 describes the call distribution for the enterprise under study based on the worst busy hour and the projected future growth of V oIP calls. In the figure, the call distribution is described as a probability tree. It is also possible to describe it as a probability matrix. Some important observations can be made about the voice traffic flow for inter-floor and external calls. For all these type of calls, the voice traffic has to be always routed through the router. This is so because Switchs 1 and 2 are layer 2 switches with VLANs configuration. One can observe that the traffic flow for inter-floor calls between Floors 1 and 2 imposes twice the load on Switch 1, as the traffic has to pass through the switch to the router and back to the switch again. Similarly, Switch 2 experiences twice the load for external calls from/to Floor 3.3.3. Define performance thresholds and growth capacityIn this step, we define the network performance thresholds or operational points for a number of important key network elements. These thresholds are to be considered when deploying the new service. The benefit is twofold. First, the requirements of the new service to be deployed are satisfied. Second, adding the new service leaves the network healthy and susceptible to future growth. Two important performance criteria are to be taken into account. First is the maximum tolerable end-to-end delay; and second is the utilization bounds or thresholds of networkresources. The maximum tolerable end-to-end delay is determined by the most sensitive application to run on the network. In our case, it is 150 ms end-to-end for V oIP. It is imperative to note that if the network has certain delay sensitive applications, the delay for these applications should be monitored, when introducing V oIP traffic, such that they do not exceed their required maximum values. As for the utilization bounds for network resources, such bounds or thresholds are determined by factors such as current utilization, future plans, and foreseen growth of the network. Proper resource and capacity planning is crucial. Savvy network engineers must deploy new services with scalability in mind, and ascertain that the network will yield acceptable performance under heavy and peak loads, with no packet loss. V oIP requires almost no packet loss. In literature, 0.1–5% packet loss was generally asserted. However, in [24] the required V oIP packet loss was conservatively suggested 5to be less than 10. A more practical packet loss, based on experimentation, of below 1% was required in [22]. Hence, it is extremely important not to utilize fully the network resources. As rule-of-thumb guideline for switched fast full-duplex Ethernet, the average utilization limit of links should be 190%, and for switched shared fast Ethernet, the average limit of links should be 85% [25]. The projected growth in users, network services, business, etc. must be all taken into consideration to extrapolate the required growth capacity or the future growth factor. In our study, we will ascertain that 25% of the available network capacity is reserved for future growth and expansion. For simplicity, we will apply this evenly to all network resources of the router, switches, and switched-Ethernet links. However, keep in mind this percentage in practice can be variable for each network resource and may depend on the current utilization and the required growth capacity. In our methodology, the reservation of this utilization of network resources is done upfront, before deploying the new service, and only the left-over capacity is used for investigating the network support of the new service to be deployed.3.4. Perform network measurementsIn order to characterize the existing network traffic load, utilization, and flow,network measurements have to be performed. This is a crucial step as it can potentially affect results to be used in analytical study and simulation. There are a number of tools available commercially and noncommercially to perform network measurements. Popular open-source measurement tools include MRTG, STG, SNMPUtil, and GetIF [26]. A few examples of popular commercially measurement tools include HP OpenView, Cisco Netflow, Lucent VitalSuite, Patrol DashBoard, Omegon NetAlly, Avaya ExamiNet, NetIQ Vivinet Assessor, etc. Network measurements must be performed for network elements such as routers, switches, and links. Numerous types of measurements and statistics can be obtained using measurement tools. As a minimum, traffic rates in bits per second (bps) and packets per second (pps) must be measured for links directly connected to routers and switches. To get adequate assessment, network measurements have to be taken over a long period of time, at least 24-h period. Sometimes it is desirable to take measurements over several days or a week. One has to consider the worst-case scenario for network load or utilization in order to ensure good QoS at all times including peak hours. The peak hour is different from one network to another and it depends totally on the nature of business and the services provided by the network.Table 2 shows a summary of peak-hour utilization for traffic of links in both directions connected to the router and the two switches of the network topology of Fig.1. These measured results will be used in our analysis and simulation study.。
通信工程外文文献
外文资料和中文翻译外文资料：Review of UMTS1.1 UMTS Network ArchitectureThe European/Japanese 3G standard is referred to as UMTS. UMTS is one of a number of standards ratified by the ITU-T under the umbrella of IMT-2000. It is currently the dominant standard, with the US CDMA2000 standard gaining ground, particularly with operators that have deployed cdmaOne as their 2G technology. At time of writing,Japan is the most advanced in terms of 3G network deployment. The three incumbent operators there have implemented three different technologies: J-Phone is using UMTS,KDDI has a CDMA2000 network, and the largest operator NTT DoCoMo is using a system branded as FOMA (Freedom of Multimedia Access). FOMA is based on the original UMTS proposal, prior to its harmonization and standardization.The UMTS standard is specified as a migration from the second generation GSM standard to UMTS via the General Packet Radio System (GPRS) and Enhanced Data for Global Evolution (EDGE), as shown in Figure. This is a sound rationale since as of April 2003, there were over 847 Million GSM subscribers worldwide1, accounting for68% of the global cellular subscriber figures. The emphasis is on keeping as much ofthe GSM network as possible to operate with the new system.We are now well on the road towards Third Generation (3G), where the network will support all traffic types: voice, video and data, and we should see an eventual explosion in the services available on the mobile device. The driving technology for this is the IP protocol. Many cellular operators are now at a position referred to as 2.5G, with the deployment of GPRS, which introduces an IP backbone into the mobile core network.The diagram below, Figure 2, shows an overview of the key components in a GPRS network, and how it fits into the existing GSM infrastructure.The interface between the SGSN and GGSN is known as the Gn interface and uses the GPRS tunneling protocol (GTP, discussed later). The primary reason for the introduction of this infrastructure is to offer connections to external packet networks, such as the Internet or a corporate Intranet.This brings the IP protocol into the network as a transport between the SGSN and GGSN. This allows data services such as email or web browsing on the mobile device,with users being charged based on volume of data rather than time connected.The dominant standard for delivery of 3G networks and services is the Universal Mobile Telecommunications System, or UMTS. The first deployment of UMTS is the Release ’99 architecture, shown below in Figure 3.In this network, the major change is in the radio access network (RAN) with the introduction of CDMA technology for the air interface, and ATM as a transport in the transmission part. These changes have been introduced principally to support the transport of voice, video and data services on the same network. The core network remains relatively unchanged, with primarily software upgrades. However, the IP protocol pushes further into the network with the RNC now communicating with the 3G SGSN using IP.The next evolution step is the Release 4 architecture, Figure 4. Here, the GSM core is replaced with an IP network infrastructure based around Voice over IP technology.The MSC evolves into two separate components: a Media Gateway (MGW) and an MSC Server (MSS). This essentially breaks apart the roles of connection and connection control. An MSS can handle multiple MGWs, making the network more scaleable.Since there are now a number of IP clouds in the 3G network, it makes sense to merge these together into one IP or IP/ATM backbone (it is likely both options will be available to operators.) This extends IP right across the whole network, all the way to the BTS.This is referred to as the All-IP network, or the Release 5 architecture, as shown in Figure 5. The HLR/VLR/EIR are generalised and referred to as the HLR Subsystem(HSS).Now the last remnants of traditional telecommunications switching are removed, leaving a network operating completely on the IP protocol, and generalised for the transport of many service types. Real-time services are supported through the introduction of a new network domain, the IP Multimedia Subsystem (IMS).Currently the 3GPP are working on Release 6, which purports to cover all aspects not addressed in frozen releases. Some call UMTS Release 6 4G and it includes such issues as interworking of hot spot radio access technologies such as wireless LAN.1.2 UMTS FDD and TDDLike any CDMA system, UMTS needs a wide frequency band in which to operate to effectively spread signals. The defining characteristic of the system is the chip rate, where a chip is the width of one symbol of the CDMA code. UMTS uses a chip rate of 3.84Mchips/s and this converts to a required spectrum carrier of 5MHz wide. Since this is wider than the 1.25MHz needed for the existing cdmaOne system, the UMTS air interface is termed ‘wideband’ CDMA.There are actually two radio technologies under the UMTS umbrella: UMTS FDD and TDD. FDD stands for Frequency Division Duplex, and like GSM, separates traffic in the uplink and downlink by placing them at different frequency channels. Therefore an operator must have a pair of frequencies allocated to allow them to run a network, hence the term ‘paired spectrum’. TDD or Time Division Duplex requires only one frequency channel, and uplink and downlink traffic are separated by sending them at different times. The ITU-T spectrum usage, as shown in Figure 6, for FDD is 1920- 980MHz for uplink traffic, and 2110-2170MHz for downlink. The minimum allocation an operator needs is two paired 5MHz channels, one for uplink and one for downlink, at a separation of 190MHz. However, to provide comprehensive coverage and services, it is recommended that an operator be given three channels. Considering the spectrum allocation, there are 12 paired channels available, and many countries have now completed the licencing process for this spectrum, allocating between two and four channels per licence. This has tended to work out a costly process for operators, since the regulatory authorities in some countries, notably in Europe, have auctioned these licences to the highest bidder. This has resulted in spectrum fees as high as tens of billions of dollars in some countries.The Time Division Duplex (TDD) system, which needs only one 5MHz band in which to operate, often referred to as unpaired spectrum. The differences between UMTS FDD and TDD are only evident at the lower layers, particularly on the radio interface. At higher layers, the bulk of the operation of the two systems is the same. As the name suggests, the TDD system separates uplink and downlink traffic by placing them in different time slots. As will be seen later, UMTS uses a 10ms frame structure which is divided into 15 equal timeslots. TDD can allocate these to be either uplink or downlink,with one or more breakpoints between the two in a frame defined. In this way, it is well suited to packet traffic, since this allows great flexibility in dynamically dimensioning for asymmetry in traffic flow.The TDD system should not really be considered as an independent network, but rather as a supplementfor an FDD system to provide hotspot coverage at higher data rates. It is rather unsuitable for large scale deployment due to interference between sites, since a BTS may be trying to detect a weak signal from a UE, which is blocked out by a relatively strong signal at the same frequency from a nearby BTS. TDD is ideal for indoor coverage over small areas.Since FDD is the main access technology being developed currently, the explanations presented here will focus purely on this system.1.3 UMTS Bearer ModelThe procedures of a mobile device connecting to a UMTS network can be split into two areas: the access stratum (AS) and the non-access stratum (NAS). The access stratum involves all the layers and subsystems that offer general services to the non-access stratum. In UMTS, the access stratum consists of all of the elements in the radio access network, including the underlying ATM transport network, and the various mechanisms such as those to provide reliable information exchange. All of the non-access stratum functions are those between the mobile device and the core network, for example, mobility management. Figure 7 shows the architecture model. The AS interacts with the NAS through the use of service access points (SAPs).UMTS radio access network (UTRAN) provides this separation of NAS and AS functions, and allows for AS functions to be fully controlled and implemented within the UTRAN. The two major UTRAN interfaces are the Uu, which is the interface between the mobile device, or User Equipment (UE) and the UTRAN, and the Iu, which is the interface between the UTRAN and the core network. Both of these interfaces can be divided into control and user planes each with appropriate protocol functions.A Bearer Service is a link between two points, which is defined by a certain set of characteristics. In the case of UMTS, the bearer service is delivered using radio access bearers.A Radio access bearer (RAB) is defined as the service that the access stratum (i.e.UTRAN) provides to the non-access stratum for transfer of user data between the User Equipment and Core Network. A RAB can consist of a number of subflows, which are data streams to the core network within the RAB that have different QoS characteristics,such as different reliabilities. A common example of this is different classes of bits with different bit error rates can be realised as different RAB subflows. RAB subflows are established and released at the time the RAB is established and released, and are delivered together over the same transport bearer.A Radio Link is defined as a logical association between a single User Equipment (UE) and a single UTRAN access point, such as an RNC. It is physically comprised of one or more radio bearers and should not be confused with radio access bearer.Looking within the UTRAN, the general architecture model is as shown in Figure 8 below. Now shown are the Node B or Base Station (BTS) and Radio Network Controller (RNC) components, and their respective internal interfaces. The UTRAN is subdivided into blocks referred to as Radio Network Subsystems (RNS), where each RNS consists of one controlling RNC (CRNC) and all the BTSs under its control. Unique to UMTS is the interface between RNSs, the Iur interface, which plays a key role in handover procedures. The interface between the BTS and RNC is the Iub interface.All the ‘I’ interfaces: Iu, Iur and Iub, currently3 use ATM as a transport layer. In the context of ATM, the BTS is seen as a host accessing an ATM network, within which the RNC is an ATM switch. Therefore, the Iub is a UNI interface, whereas the Iu and Iur interfaces are considered to be NNI, as illustrated in Figure 9.This distinction is because the BTS to RNC link is a point-to-point connection in that a BTS or RNC will only communicate with the RNC or BTS directly connected to it, and will not require communication beyond that element to another network element.For each user connection to the core network, there is only one RNC, which maintains the link between the UE and core network domain, as highlighted in Figure 10. This RNC is referred to as the serving RNC or SRNC. That SRNC plus the BTSs under its control is then referred to as the SRNS. This is a logical definition with reference to that UE only. In an RNS, the RNC that controls a BTS is known as the controlling RNC or CRNC. This is with reference to the BTS, cells under its control and all the common and shared channels within.As the UE moves, it may perform a soft or hard handover to another cell. In the case of a soft handover, the SRNC will activate the new connection to the new BTS. Should the new BTS be under the control of another RNC, the SRNC will also alert this new RNC to activate a connection along the Iur interface. The UE now has two links, one directly to the SRNC, and the second, through the new RNC along the Iur interface. In this case, this new RNC is logically referred to as a drift RNC or DRNC, see Figure 10. It is not involved in any processing of the call and merely relays it to the SRNC for connection to the core. In summary, SRNC and DRNC are usually associated with the UE and the CRNC is associated with the BTS. Since these are logical functions it is normal practice that a single RNC is capable of dealing with all these functions.A situation may arise where a UE is connected to a BTS for which the SRNC is not the CRNC for that BTS. In that situation, the network may invoke the Serving RNC Relocation procedure to move the core network connection. This process is described inSection 3.中文翻译：通用移动通信系统的回顾1.1 UMTS网络架构欧洲/日本的3G标准，被称为UMTS。
通信专业英语作文模板
通信专业英语作文模板英文回答：1. What is the definition of communication?Communication is the process of effectively conveying a message from one person or group to another, with theintent of creating shared understanding. It involves the exchange of information, thoughts, feelings, and ideas through various channels, such as speaking, writing, gestures, and visual cues.2. What are the different types of communication?Verbal communication: Spoken or written words used to convey a message.Nonverbal communication: Body language, facial expressions, tone of voice, and eye contact that convey messages without words.Intrapersonal communication: Communication with oneself, involving internal thoughts, feelings, and self-reflection.Interpersonal communication: Communication between individuals, including conversations, discussions, and relationships.Mass communication: Dissemination of a message to alarge audience through media such as television, radio, and print.3. What are the key elements of effective communication?Clarity: The message is easy to understand and unambiguous.Accuracy: The message is truthful and represents the intended meaning.Relevance: The message is pertinent to the recipient's needs and interests.Timeliness: The message is delivered at an appropriate time.Completeness: The message includes all necessary information.Conciseness: The message is brief and to the point.Empathy: The message demonstrates understanding of the recipient's perspective.Feedback: The sender receives feedback to ensure the message has been received and understood.4. What are the barriers to effective communication?Language differences: Misunderstandings due to linguistic barriers.Cultural differences: Varying communication styles and protocols across cultures.Personal biases: Preconceived notions or prejudices that influence perception.Noise: Distractions that interfere with the transmission or reception of the message.Lack of attention: The recipient is not paying enough attention to the message.Emotional barriers: Strong emotions that hinder clear thinking and communication.5. What are the strategies for improving communication skills?Active listening: Paying full attention to the speaker and demonstrating comprehension.Effective speaking: Clearly and confidently expressing oneself with appropriate tone and body language.Feedback and clarification: Seeking and providing feedback to ensure understanding.Cultural sensitivity: Being aware of and adapting to different communication styles across cultures.Emotional management: Controlling emotions and maintaining a professional demeanor.Written communication skills: Writing emails, reports, and other documents effectively and clearly.中文回答：1. 什么是沟通？沟通是有效地将信息从一个人或群体传达给另一个人或群体，以期达成共同理解的过程。
通信英语作文
通信英语作文IntroductionIn today’s world, communication plays a crucial role in connecting people from different cultures and backgrounds. With the advancement of technology, various means of communication have emerged, making it easier for people to stay connected. In this article, we will explore the importance of communication in the modern world and discuss different modes of communication in English.Importance of CommunicationCommunication is essential for promoting understanding and building relationships. In a globalized world, effective communication skills are highly valued. It helps individuals express their thoughts, ideas, and emotions, facilitating cooperation and collaboration. Whether in personal or professional settings, effective communication is vital for success.Modes of Communication1. Verbal CommunicationVerbal communication involves the use of spoken or written words to convey messages. In English, it is crucial to have good verbal communication skills to interact with people from different countries. This can be achieved through language learning, practicing pronunciation, and improving vocabulary and grammar.2. Non-verbal CommunicationNon-verbal communication involves the use of body language, gestures, facial expressions, and tone of voice to convey messages. It is equally important to understand and interpret non-verbal cues when communicating in English. Being aware of cultural differences in non-verbal communication can prevent misunderstandings and promote effective communication.3. Written CommunicationWritten communication is important for formal and professional communication. It includes emails, letters, reports, and other written documents. In English, having good writing skills is essential to convey messages clearly and concisely. It requires proper grammar, vocabulary, and organizational skills.4. Digital CommunicationWith the advent of technology, digital communication has become an integral part of our lives. It includes communication through email, instant messaging, social media, and video conferencing. In English, digital communication skills are essential, as it allows people to connect with others globally, share ideas, and collaborate on projects.Improving Communication Skills in English1. Language LearningLearning English as a second language is essential for effective communication. It involves studying grammar, vocabulary, and pronunciation. Taking language courses, practicing speaking with native speakers, and immersing oneself in an English-speaking environment can improve language skills.2. Active ListeningActive listening is a crucial skill for effective communication. It involves paying full attention to the speaker, understanding their message, and responding appropriately. Practicing active listening can help in understanding different accents and improving overall communication skills.3. Cultural AwarenessCultural awareness is important when communicating in a multicultural environment. Understanding cultural norms, values, and customs can help avoid misunderstandings and foster effective communication. Being open-minded and respectful towards different cultures is essential for successful communication.4. Practice and FeedbackRegular practice is key to improving communication skills. Engaging in conversations with native English speakers, participating in language exchange programs, and seeking feedback from others can help identify areas for improvement and enhance overall communication abilities.ConclusionEffective communication in English is vital for personal and professional success in today’s interconnected world. By developing strong communication skills, both verbal and non-verbal, individuals can overcome language barriers and connect with people from diverse backgrounds. Continuous learning, practice, and cultural awareness are crucial in becoming proficient in communication in English. So, let’s embrace the importance of communication and work towards enhancing our skills in order to thrive in our personal and professional lives.。
介绍通信工程专业英语作文
介绍通信工程专业英语作文英文回答：Telecommunications engineering is a branch ofelectrical engineering that deals with the transmission of information over long distances. It involves the design, construction, and maintenance of communication systems,such as telephone networks, data networks, and satellite communication systems.Telecommunications engineers are responsible for ensuring that communication systems are reliable, efficient, and secure. They must have a strong understanding of the principles of communication theory, as well as the latest technologies used in the field.Telecommunications engineering is a rapidly evolving field, with new technologies being developed all the time. As a result, telecommunications engineers must beconstantly learning and adapting to new technologies.Telecommunications engineering is a challenging and rewarding field. It offers the opportunity to work on cutting-edge technologies and to make a real difference in the world.中文回答：电信工程是电气工程的一个分支，它涉及远距离的信息传输。
通信工程专业英语论文
通信工程专业英语论文 Document serial number【UU89WT-UU98YT-UU8CB-UUUT-UUT108】The General Situation of AT89C51The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip; the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:Compatible with MCS-51Products4K Bytes of In-System Reprogrammable Flash MemoryEndurance: 1,000 Write/Erase CyclesFully Static Operation: 0 Hz to 24 MHzThree-Level Program Memory Lock128 x 8-Bit Internal RAM32 Programmable I/O LinesTwo 16-Bit Timer/CountersSix Interrupt SourcesProgrammable Serial ChannelLow Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramPin Description:VCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. (Sink/flow)Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during programverification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally beingpulled low will source current (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally beingpulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memories that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/sourcefour TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3alsoreceives some control signals for Flash programming and verification.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1(LB1) is programmed, EA will be internally latched (fasten with a latch) on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage（VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Oscillator Characteristics：XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source,XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low times specifications must be observed.Idle Mode：In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabledinterrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down ModesPower Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in theThe AT89C51 code memory array is programmed byte-bybytein either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51,the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than ms. Repeat steps 1 through 5, changing the address and data for the entire array oruntil the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on . Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that and must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.AT89C51的概况AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
通信工程专业英语论文翻译
CDMA versus TDMATerm Paper :DTEC 6810Submitted by:Sabareeshwar Natarajan.Fall 2006DTEC 6810Communication TechnologyCDMA Vs TDMA in travel:Both GSM and CDMA can be found across United States, which doesn’t mean that it doesn’t matter which technology we choose. When we travel domestically it is possible that we reach areas where digital service is not available. While traveling between places it is possible that we reach certain rural areas were only analog access is offered. CDMA handsets offer analog capabilities which the GSM don’t offer. Another difference between GSM and CDMA is in the data transfer methods. GSM’s high-speed wireless data technology, GPRS (General Packet Radio Service), usually offers a slower data bandwidth for wireless data connection than CDMA’s high-speed technology, which has the capability of providing ISDN (Integrated Services Digital Network) with speeds as much as 144Kbps.GSM’s benefits over the CDMA in domestic purpose are that GSM uses SIM card that identifies a user and stores the information in the handset. The SIM card can be swapped between handsets, which enable to move all the contacts to the new handset with ease. CDMA can have this flexibility with their own service that stores data on the operator’s datab ase. This service allows the user to swap data’s between two handsets with a little trouble, but the advantage is it can be done when the handset is even lost but in GSM technology, when a handset is lost, SIM card is also lost with it.When it comes for international roaming handsets with GSM is far better than CDMA handsets because GSM is used in most the markets across the globe. Users using tri-band or quad-band can travel to Europe, India and most of Asia and still can use their cell phone. CDMA does not have this multiband capability, thus cannot be used multiple countries with ease.Differences between CDMA and TDMA:CDMA technology claims that its bandwidth is thirteen times efficient than TDMA and forty times efficient than analog systems. CDMA also have better security and higher data and voice transmission quality because of the spread spectrum technology it uses, which has increased resistance to multipath distortion. The battery life is higher in TDMA compared to CDMA because CDMA handsets transmit data all the time and TDMA does not require constant transmission. CDMA has greater coverage area when compared to TDMA. Though, when it comes to international roaming TDMA is better than CDMA. CDMA is patented by Qualcomm, so an extra fee is paid to Qualcomm. When it comes to United States and Canada market size for CDMA is larger than GSM’s market size but worldwide the market size for GSM is far bigger both in the number of subscribers and coverage ,than CDMA.Conclusion:From the comparisons made above we cannot say that TDMA is better than CDMA or vice versa. The main advantage of the CDMA is that, in the single detection method it is more flexible than TDMA or joint detection. CDMA is said to have higher capacity than TDMA. But in the future GSM can be extended by an optional CDMA component in order to further increase the capacity. Finally, it does not matter whether which one is better CDMA or TDMA right now. It can be only found out with the evolution of these technologies. When going for a cell phone the user should choose the technology according to where they use it. For users who travel abroad it is better to go with GSM handsets. For the users in United States CDMA is better than TDMA because of the coverage we can get at rural areas where digital signals cannot be transmitted.CDMA与TDMA学期论文：6810 DTEC提交：sabareeshwar纳塔拉詹。
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The General Situation of AT89C51The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip; the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six InterruptSources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interruptarchitecture, a full duplex serial port, on-chiposcillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode总结stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillatordisabling all other chip functions until the next hardware reset.Block DiagramPin Description:VCC Supply voltage.GND Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. (Sink/flow)Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal总结pull-ups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memories that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.Port 3 also serves the functions of various special features of the AT89C51 as总结listed below:Port 3 also receives some control signals for Flash programming and verification.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at总结0000H up to FFFFH. Note, however, that if lock bit 1(LB1) is programmed, EA will be internally latched (fasten with a latch) on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage（VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Oscillator Characteristics：XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low times specifications must be observed.Idle Mode：In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down Modes总结Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset.Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.总结Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signatureThe AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end总结of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, andthe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.总结AT89C51的概况AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。