EDA考试程序

---'1' Counter---library ieee;use ieee.std_logic_1164.all;entity sj9 isport(din:in std_logic_vector(7 downto 0);counter:out integer range 0 to 8); end sj9;architecture bhv of sj9 isbeginprocess(din)variable temp:integer range 0 to 8;begintemp:=0;for i in 0 to 7 loopif din(i)='1' thentemp:=temp+1;end if;end loop;counter<=temp;end process;end bhv;6分频器library ieee;use ieee.std_logic_1164.all;entity f_divider isport(clk:in std_logic;output:buffer std_logic);end f_divider;architecture bhv of f_divider isbeginprocess(clk)variable count:integer range 0 to 5; variable op:std_logic;beginif clk'event and clk='1' thencount:=count+1;if count=3 thenoutput<=not output;count:=0;end if;end if;end process;end bhv; led译码器library ieee;use ieee.std_logic_1164.all;entity LED_encoder isport(a:in std_logic_vector(3 downto 0);dataout:out std_logic_vector(6 downto 0));end LED_encoder;architecture bhv of LEd_encoder isbegindataout<="0111111" when a="0000" else"0000110" when a="0001" else"1011011" when a="0010" else"1001111" when a="0011" else"1100110" when a="0100" else"1101101" when a="0101" else"1111101" when a="0110" else"0000111" when a="0111" else"1111111" when a="1000" else"1101111" when a="1001" else"1110111" when a="1010" else"1111100" when a="1011" else"0111001" when a="1100" else"1011110" when a="1101" else"1111001" when a="1110" else"1110001";end bhv;--------ROM--------16*8--------library ieee;use ieee.std_logic_1164.all;entity sj15rom isport(addr:integer range 0 to 15;dout:out integer range 0 to 255);end sj15rom;architecture bhv of sj15rom istype mem_type is array(0 to 15)of integer range 0 to 255;constantmemory:mem_type:=(15,34,85,122,49,65,47,9 4,212,3,55,67,81,29,44,37);begindout<=memory(addr);end bhv;------RAM-----------16*8------library ieee;use ieee.std_logic_1164.all;entity sj15ram isgeneric (m:integer:=8;n:integer:=16);port(wr_ena,clk:in std_logic;addr:in integer range 0 to n-1;din:in std_logic_vector(m-1 downto 0);dout:out std_logic_vector(m-1 downto 0)); end sj15ram;architecture bhv of sj15ram istype vector_array is array(0 to n-1)of std_logic_vector(m-1 downto 0);signal memory :vector_array;beginprocess(clk,wr_ena)beginif wr_ena='1'thenif clk'event and clk='1' thenmemory(addr)<=din;end if;end if;end process;dout<=memory(addr);end bhv;STOP_WATCH代码:COUNTER:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(clk,rst:in std_logic;outp1:out std_logic_vector(3 downto 0));end counter;architecture bhv of counter isbeginprocess(clk,rst)variable temp:std_logic_vector(3 downto 0); beginif rst='1' then temp:="0000";elsif clk'event and clk='1' thenif temp="1010" thentemp:="0000";elsetemp:=temp+1;end if;end if;outp1<=temp;end process;end bhv;REGIST:library ieee;use ieee.std_logic_1164.all;entity regist isport(inp2:in std_logic_vector(3 downto 0);store:in std_logic;outp2:out std_logic_vector(3 downto 0));end regist;architecture bhv of regist isbeginprocess(store)beginif store='1' thenoutp2<=inp2;end if;end process;end bhv;STOP_WA TCH:library ieee;use ieee.std_logic_1164.all;entity stop_watch isport(clk,stop:in std_logic;reg:out std_logic_vector(3 downto 0)); end stop_watch;architecture bhv of stop_watch is component counter isport(clk,rst:in std_logic;outp1:out std_logic_vector(3 downto 0));end component counter;component regist isport(inp2:in std_logic_vector(3 downto 0);store:in std_logic;outp2:out std_logic_vector(3 downto 0));end component regist;signal m:std_logic_vector(3 downto 0); beginu1:counter port map(clk,stop,m);u2:regist port map(m,stop,reg);end bhv;比较器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity comparer isport(a,b:in unsigned (7 downto 0);sel:in bit;x1,x2,x3:out bit);end comparer;architecture bhv of comparer isbeginprocess(a,b,sel)variable a_temp,b_temp:signed(7 downto 0); begina_temp:=conv_signed(a,8);b_temp:=conv_signed(b,8);case sel iswhen '0'=>if a>b thenx1<='1';x2<='0';x3<='0';elsif a=b thenx2<='1';x1<='0';x3<='0';elsex3<='1';x2<='0';x1<='0';end if;when '1'=>if a_temp>b_temp thenx1<='1';x2<='0';x3<='0';elsif a_temp=b_temp thenx2<='1';x1<='0';x3<='0';elsex3<='1';x2<='0';x1<='0';end if;when others=>null;end case;end process;end bhv;编码器library ieee;use ieee.std_logic_1164.all;entity encoder isport(a:in std_logic_vector(7 downto 0);b:out std_logic_vector(2 downto 0)); end encoder;architecture bhv of encoder isbeginb<="000" when a="00000001" else"001" when a="00000010" else"010" when a="00000100" else"011" when a="00001000" else"100" when a="00010000" else"101" when a="00100000" else"110" when a="01000000" else"111" when a="10000000" else"ZZZ";end bhv;并串转换器library ieee;use ieee.std_logic_1164.all;entity sj14 isport(clk,load:in std_logic;din:in std_logic_vector(7 downto 0);dout:out std_logic);end sj14;architecture bhv of sj14 isbeginprocess(clk)variable temp:std_logic_vector(7 downto 0); beginif clk'event and clk='1' thenif load='1' thentemp:=din;elsedout<=temp(7);temp:=temp(6 downto 0)&'0';end if;end if;end process;end bhv;存储控制器library ieee;use ieee.std_logic_1164.all;entity sj19 isport(clk,ready,lw_r,blast:in std_logic;mread,mwrite:out std_logic);end sj19;architecture bhv of sj19 istype state is (idle,decision,r_ead,w_rite); signal p_s,n_s:state;beginprocess(clk)beginif clk'event and clk='1' thenp_s<=n_s;end if;end process;process(ready,lw_r,blast,p_s)begincase p_s iswhen idle=>mwrite<='0';mread<='0';if ready='1' thenn_s<=decision;elsen_s<=idle;end if;whendecision=>mwrite<='0';mread<='0';if lw_r='0' thenn_s<=r_ead;elsen_s<=w_rite;end if;when r_ead=>mwrite<='0';mread<='1';if blast='1' thenn_s<=idle;elsen_s<=r_ead;end if;whenw_rite=>mwrite<='1';mread<='0';if blast='1' thenn_s<=idle;elsen_s<=w_rite;end if;end case;end process;end bhv;二百进制计数器library ieee;use ieee.std_logic_1164.all;entity counter isport(clk,rst,ena:in std_logic;d1,d2:out integer range 0 to 15;d3:out integer range 0 to 3);end counter;architecture bhv of counter isbeginprocess(clk,rst,ena)variable temp1:integer range 0 to 10; variable temp2:integer range 0 to 10; variable temp3:integer range 0 to 2;beginif rst='1' thentemp1:=0;temp2:=0;temp3:=0;elsif clk'event and clk='1' thenif ena='1' thentemp1:=temp1+1;if temp1=10 thentemp1:=0;temp2:=temp2+1;if temp2=10 thentemp2:=0;temp3:=temp3+1;if temp3=2 thentemp3:=0;end if;end if;end if;end if;end if;d1<=temp1;d2<=temp2;d3<=temp3;end process;end bhv;二进制_格雷码转换器library ieee;use ieee.std_logic_1164.all;entity shift isgeneric (n:integer :=4);port (inp:in std_logic_vector(n-1 downto 0);outp: out std_logic_vector(n-1 downto 0));end shift;architecture bhv of shift isbeging1:for i in 0 to n-2 generateoutp(i)<=not inp(i) when inp(i+1)='1' else inp(i);end generate;outp(n-1)<=inp(n-1);end bhv;空调控制器library ieee;use ieee.std_logic_1164.all;entity air_controller isport(temp_high,temp_low,clk:in std_logic;hot,cold:out std_logic);end air_controller; architecture bhv of air_controller is type state is (normal,high1,low1); signal n_s,p_s : state;beginprocess(clk)beginif clk'event and clk='1' thenp_s<=n_s;end if;end process;process(temp_high,temp_low,p_s) begincase p_s iswhen high1 => cold<='1';hot<='0';if temp_low='1' thenn_s<=low1;elsif temp_high='1' thenn_s<=high1;elsen_s<=normal;end if;when low1 => cold<='0';hot<='1';if temp_high='1' thenn_s<=high1;elsif temp_low='1' thenn_s<=low1;elsen_s<=normal;end if;when normal => cold<='0';hot<='0';if temp_high='1' thenn_s<=high1;elsif temp_low='1' thenn_s<=low1;elsen_s<=normal;end if;end case;end process;end bhv;密度编码器library ieee;use ieee.std_logic_1164.all;entity encoder isport(din:in std_logic_vector(7 downto 1);dout:out std_logic_vector(7 downto 0)); end encoder;architecture bhv of encoder isbeginprocess(din)variable count :integer range 0 to 7;begincount:=0;for i in 7 downto 1 loopcase din(i) iswhen '1'=>count:=count+1;when others=>next;end case;end loop;case count iswhen 0=> dout<="00000001";when 1=> dout<="00000010";when 2=> dout<="00000100";when 3=> dout<="00001000";when 4=> dout<="00010000";when 5=> dout<="00100000";when 6=> dout<="01000000";when 7=> dout<="10000000";end case;end process;end bhv;奇偶校验器library ieee;use ieee.std_logic_1164.all;entity xiti6_8 isport(datain:in std_logic_vector(7 downto 0);dataout:out std_logic);end xiti6_8;architecture bhv of xiti6_8 isbeginprocess(datain)variable temp:std_logic;begintemp:='0';for i in 0 to 7 looptemp:=temp xor datain(i);end loop;dataout<=temp;end process;end bhv;三态缓冲电路library ieee;use ieee.std_logic_1164.all;entity tri_state isport(ena:in std_logic;input:in std_logic_vector(7 downto 0);output:out std_logic_vector(7 downto 0));end tri_state;architecture bhv of tri_state isbeginoutput<=input when ena='0' else"ZZZZZZZZ";end bhv;数据选择器library ieee;use ieee.std_logic_1164.all;entity mux isport(a,b,c,d,sel1,sel2:in std_logic;y:out std_logic);end mux;architecture bhv of mux issignal sel:std_logic_vector(1 downto 0); beginsel<=sel1 & sel2;with sel selecty<=a when "00",b when "01",c when "10",d when others;end bhv;信号发生器－进程library ieee;use ieee.std_logic_1164.all;entity xhfsq isport(clk:in std_logic;dataout:out std_logic_vector(7 downto 0));end xhfsq;architecture bhv of xhfsq istype mem_type is array (0 to 63) of std_logic_vector(7 downto 0);constant memory : mem_type:=("11111111"等数据);beginprocess(clk)variable count:integer range 0 to 63;beginif clk'event and clk='1' thendataout<=memory(count);count:=count+1;end if;end process;end bhv;信号发生器－状态机library ieee;use ieee.std_logic_1164.all;entity signal_gen isport(clk:in std_logic;out1,out2:out std_logic);end signal_gen;architecture bhv of signal_gen istype state is(s1,s2,s3,s4);signal p_s1,n_s1:state;signal p_s2,n_s2:state;signal temp1,temp2:std_logic;beginprocess(clk)beginif clk'event and clk='1' thenp_s1<=n_s1;end if;end process;process(clk) beginif clk'event and clk='0' thenp_s2<=n_s2;end if;end process;process(p_s1)begincase p_s1 iswhen s1 => out1<='0';temp1<='0';n_s1<=s2;when s2 => out1<='1';temp1<='0';n_s1<=s3;when s3 => out1<='0';temp1<='1';n_s1<=s4;when s4 => out1<='0';temp1<='0';n_s1<=s1;end case;end process;process(p_s2)begincase p_s2 iswhen s1 => temp2<='0';n_s2<=s2;when s2 => temp2<='1';n_s2<=s3;when s3 => temp2<='0';n_s2<=s4;when s4 => temp2<='0';n_s2<=s1;end case;end process;out2<=temp1 xor temp2;end bhv;序列检测器library ieee;use ieee.std_logic_1164.all; entity str_detector isport (datain,rst,clk:in std_logic;dataout:out std_logic); end str_detector;architecture bhv of str_detector is type state is(s0,s1,s2,s3,s4,s5,s6); signal n_s,p_s :state;beginprocess(rst,clk)beginif rst='1' thenp_s<=s0;elsif clk'event and clk='1' thenp_s<=n_s;end if;end process;process(datain,p_s)begincase p_s iswhen s0 =>dataout<='0';if datain='1' thenn_s<=s1;elsen_s<=s0;end if;when s1=>dataout<='0';if datain='1' thenn_s<=s2;elsen_s<=s0;end if;when s2=>dataout<='0';if datain='0' thenn_s<=s3;elsen_s<=s2;end if;when s3=>dataout<='0';if datain='0' thenn_s<=s4;elsen_s<=s1;end if;when s4=>dataout<='0';if datain='1' thenn_s<=s5;elsen_s<=s0;end if;when s5=>dataout<='0';if datain<='0' thenn_s<=s6;elsen_s<=s2;end if;when s6=>dataout<='1';if datain='0' thenn_s<=s0;elsen_s<=s1;end if;end case;end process;end bhv;library ieee;use ieee.std_logic_1164.all;entity sj13 isgeneric(n:integer:=4);port(d,clk,rst:in std_logic;q:out std_logic);end sj13;architecture bhv of sj13 issignal m:std_logic_vector(n-1 downto 0); beginprocess(clk,rst)beginif rst='1' thenm<=(others=>'0');elsif clk'event and clk='1' thenm<=d&m(n-1 downto 1);end if;end process;q<=m(0);end bhv;优先级编码器library ieee;use ieee.std_logic_1164.all;entity mysup isport(a:in std_logic_vector(6 downto 0);b:out std_logic_vector(2 downto 0)); end mysup;architecture bhv of mysup isbeginb<="111" when a(6)='1' else"110" when a(5)='1' else"101" when a(4)='1' else"100" when a(3)='1' else"011" when a(2)='1' else"010" when a(1)='1' else"001" when a(0)='1' else"000" ;end bhv;。