MC68HC705SR3中文资料

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01-12-MC68HC908MR32(汉化)

列表中的章节第1章一般描述。

..............................................17。

第2章记忆。

........................................................25。

第3章模拟数字转换器（ADC）。

..................................45。

第4章时钟发生器模块（CGM）。

....................................57。

第5章配置寄存器（配置）。

..................................73。

第6章计算机操作（缔约方会议）。

................................75。

第7章中央处理器单元（中央处理器）。

......................................79。

第8章外部中断（IRQ）。

..........................................91。

第9章低电压抑制（LVI）。

..........................................97。

第10章输入/输出（输入/输出）端口（端口）。

................................101。

第11章上电复位（POR）。

........................................113。

第12章脉冲宽度调制器电机控制（PWMMC）。

................115。

第13章串行通信接口模块（科学）。

....................157。

第14章系统集成模块（模拟）。

................................181。

第15章串行外设接口模块（SPI）。

..........................195。

MC68HC68资料

Real-Time Clock plus RAM with Serial InterfaceCMOSThe MC68HC68T1 HCMOS Clock/RAM peripheral contains a real–time clock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three–wire interface for communication with a microcontroller or processor. Operating in a burst mode, successive Clock/RAM locations can be read or written using only a single starting address. An on–chip oscillator allows acceptance of a selectable crystal frequency or the device can be programmed to accept a 50/60 Hz line input frequency.The LINE and system voltage (V SYS ) pins give the MC68HC68T1 the capability for sensing power–up/power–down conditions, a capability useful for battery–backup systems. The device has an interrupt output capable of signaling a microcontroller or processor of an alarm, periodic interrupt, or power sense condition. An alarm can be set for comparison with the seconds, minutes,and hours registers. This alarm can be used in conjunction with the power supply enable (PSE) output to initiate a system power–up sequence if the V SYS pin is powered to the proper level.A software power–down sequence can be initiated by setting a bit in the interrupt control register. This applies a reset to the CPU via the CPUR pin, sets the clock out (CLKOUT) and PSE pins low, and disables the serial interface.This condition is held until a rising edge is sensed on the V SYS input pin,signaling system power coming on, or by activation of a previously enabled interrupt if the V SYS pin is powered up.A watchdog circuit can be enabled that requires the microcontroller or processor to toggle the slave select (SS) pin of the MC68HC68T1 periodically without performing a serial transfer. If this condition is not met, the CPUR line resets the CPU.•Full Clock Features — Seconds, Minutes, Hours (AM/PM), Day–of–Week,Date, Month, Year (0 – 99), Auto Leap Year •32–Byte General Purpose RAM•Direct Interface to Motorola SPI and National MICROWIRE t Serial Data Ports•Minimum Timekeeping Voltage: 2.2 V•Burst Mode for Reading/Writing Successive Addresses in Clock/RAM •Selectable Crystal or 50/60 Hz Line Input Frequency •Clock Registers Utilize BCD Data•Buffered Clock Output for Driving CPU Clock, Timer, Colon, or LCD Backplane•Power–On Reset with First Time–Up Bit•Freeze Circuit Eliminates Software Overhead During a Clock Read•Three Independent Interrupt Modes — Alarm, Periodic, or Power–Down •CPU Reset Output — Provides Orderly Power–Up/Power–Down •Watchdog Circuit•Pin–for–Pin Replacement for CDP68HC68T1•Chip Complexity: 8500 FET s or 2125 Equivalent Gates•Also See Application Notes ANE425 “Use of the MC68HC68T1 RTC with M6805 Microprocessor”, AN457 “Providing a Real–Time Clock for the MC68302”, and AN1065 “Use of the MC68HC68T1 Real–Time Clock with Multiple Time Bases”MICROWIRE is a trademark of National Semiconductor Inc.Order this document by MC68HC68T1/DMOTOROLASEMICONDUCTOR TECHNICAL DATAMC68HC68T1SECONDS MINUTES HOURS DAY OF THE WEEK DATE OF THE MONTHMONTHYEAR NOT USED NOT USED NOT USED NOT USEDNOT USED NOT USED NOT USED NOT USED NOT USED STATUS REGISTER CLOCK CONTROL REGISTERINTERRUPT CONTROL REGISTER$20$21$22$23$24$25$26$27$28$29$2A $2B $2C $2D $2E $2F $30$31$32$00$1F $20$32$33$7F $80$9F $A0$B2T H R UT H R UT H R U T H R UT H R UWRITE ADDRESSES ONLYWRITE ADDRESSES ONLYNOT USEDREAD ADDRESSES ONLYREAD ADDRESSES ONLY32 BYTES GENERAL–PURPOSE USER32 BYTES GENERAL–PURPOSE USERRAMCLOCK/CALENDAR RAMHEXADECIMALSECONDS MINUTES HOURS DAY OF THE WEEK DATE OF THE MONTHMONTH YEAR NOT USED SECONDS ALARM MINUTES ALARM HOURS ALARM NOT USEDNOT USED NOT USED NOT USED NOT USED NOT USEDCLOCK CONTROL REGISTERINTERRUPT CONTROL REGISTER$A0$A1$A2$A3$A4$A5$A6$A7$A8$A9$AA $AB $AC $AD $AE $AF $B0$B1$B2HEXADECIMALHEXADECIMALCLOCK/CALENDAR Figure 5. Address MapMC68HC68T1MOTOROLA$A0$A1$A2$A3$A4$A5$A6$B1$B2TENS 0 – 5TENS 0 – 5TENS 0 – 3TENS 0 – 1TENS 0 – 9UNITS 0 – 9UNITS 0 – 9UNITS 0 – 9UNITS 1 – 7UNITS 0 – 9UNITS 0 – 9UNITS 0 – 9$20$21$22$23$24$25$26$31$32READ WRITE HEX ADDRESS READ/WRITE REGISTERSDB7DB012HR 24PM/AM TENS 0 – 2XXX X X X 76543210WRITE–ONLY REGISTERSREAD–ONLY REGISTERRAM DATA BYTE$A8$A9$AA N/A N/A N/A N/A $B0$00 T0 $1F $80 T0 $9FFUNCTIONSECONDS (00 – 59)MINUTES (00 – 59)DB7, 1 = 12 HR, 0 = 24 HR DB5, 1 = PM, 0 = AMHOURS (01 – 12 OR 00 – 23)DAY OF WEEK (01 – 07)SUNDAY = 1MONTH (01 – 12)JAN = 1DATE OF MONTH (01 – 31)YEAR (00 – 99)CLOCK CONTROL REGISTERINTERRUPT CONTROL REGISTERSECONDS ALARM (00 – 59)MINUTES ALARM (00 – 59)HOURS ALARM (01 – 21 OR 00 – 23)DB5, 1 = PM, 0 = AM IN 12 HR MODESTATUS REGISTERDATA76543210D7D6D5D4D3D2D1D0UNITS 0 – 9UNITS 0 – 9UNITS 0 – 9TENS 0 – 5TENS 0 – 5PM/AM TENS 0 – 2X X NOTE:X = Don’t Care for Write X = 0 for ReadN/A = Not ApplicableFigure 6. Clock/RAM Registers76543210MC68HC68T1MOTOROLA26Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.◊。

MC68HC711K4CFN3中文资料

Order this document by MC68HC11KTS/DThis document contains information on a new product. Speciﬁcations and information herein are subject to change without notice.MOTOROLASEMICONDUCTORTECHNICAL DATAM68HC11 K SeriesTechnical Summary 8-Bit MicrocontrollerThe M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1,MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul-tiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static design allows operation at frequencies from 4 MHz to dc.This document contains information concerning standard, custom-ROM, and extended-voltage devic-es. Standard devices include those with disabled ROM (MC68HC11K1), disabled EEPROM (MC68HC11K3), disabled ROM and EEPROM (MC68HC11K0), or EPROM replacing ROM (MC68HC711K4). Custom-ROM devices have a ROM array that is programmed at the factory to cus-tomer specifications. Extended-voltage devices are guaranteed to operate over a much greater voltage range (3.0 Vdc to 5.5 Vdc) at lower frequencies than the standard devices. Refer to the device ordering information tables for details concerning these differences.1 Features• M68HC11 CPU• Power Saving STOP and WAIT Modes• 768 Bytes RAM (All Saved During Standby)• 24 Kbytes ROM or EPROM• 640 Bytes Electrically Erasable Programmable Read Only Memory (EEPROM)• Optional Security Feature Protects Memory Contents• On-Chip Memory Mapping Logic Allows Expansion to Over 1 Mbyte of Address Space • PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint)• Nonmultiplexed Address and Data Buses• Four Programmable Chip Selects with Clock Stretching (Expanded Modes)• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler — Three Input Capture (IC) Channels — Four Output Compare (OC) Channels— One Additional Channel, Selectable as Fourth IC or Fifth OC • 8-Bit Pulse Accumulator• Four 8-Bit or Two 16-Bit Pulse Width Modulation (PWM) Timer Channels • Real-Time Interrupt Circuit• Computer Operating Properly (COP) Watchdog • Clock Monitor• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)• Enhanced Synchronous Serial Peripheral Interface (SPI)• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter • Seven Bidirectional Input/Output (I/O) Ports (54 Pins) • One Fixed Input-Only Port (8 Pins)• Available in 84-Pin Plastic Leaded Chip Carrier (PLCC), 84-Pin Windowed Ceramic Leaded Chip Carrier (CLCC), and 80-Pin Quad Flat Pack (QFP)元器件交易网MOTOROLA M68HC11 K SeriesTable 1 Standard Device Ordering InformationPackage Temperature CONFIG Description Frequency MC Order Number 84-Pin PLCC–40 ° to + 85 ° C $DF BUFFALO ROM4 MHz MC68HC11K4BCFN4–40 ° to + 85 ° C$DDNo ROM2 MHz MC68HC11K1CFN23 MHz MC68HC11K1CFN34 MHzMC68HC11K1CFN4–40 ° to + 105 ° C$DDNo ROM2 MHz MC68HC11K1VFN23 MHz MC68HC11K1VFN34 MHzMC68HC11K1VFN4–40 ° to + 125 ° C$DDNo ROM2 MHz MC68HC11K1MFN23 MHz MC68HC11K1MFN34 MHzMC68HC11K1MFN4–40 ° to + 85 ° C$DCNo ROM, No EEPROM2 MHz MC68HC11K0CFN23 MHz MC68HC11K0CFN34 MHzMC68HC11K0CFN4–40 ° to + 105 ° C$DCNo ROM, No EEPROM2 MHz MC68HC11K0VFN23 MHz MC68HC11K0VFN34 MHzMC68HC11K0VFN4–40 ° to + 125 ° C$DCNo ROM, No EEPROM2 MHz MC68HC11K0MFN23 MHz MC68HC11K0MFN34 MHzMC68HC11K0MFN4–40 ° to + 85 ° C$DFOTPROM2 MHz MC68HC711K4CFN23 MHz MC68HC711K4CFN34 MHzMC68HC711K4CFN4–40 ° to + 105 ° C$DFOTPROM2 MHz MC68HC711K4VFN23 MHz MC68HC711K4VFN34 MHzMC68HC711K4VFN4–40 ° to + 125 ° C$DFOTPROM2 MHz MC68HC711K4MFN23 MHz MC68HC711K4MFN34 MHzMC68HC711K4MFN480-Pin QFP (14 mm X 14mm)–40 ° to + 85 ° C $DF BUFFALO ROM4 MHz MC68HC11K4BCFU4–40 ° to + 85 ° C$DDNo ROM2 MHz MC68HC11K1CFU23 MHz MC68HC11K1CFU34 MHzMC68HC11K1CFU4–40 ° to + 105 ° C$DDNo ROM2 MHz MC68HC11K1VFU23 MHz MC68HC11K1VFU34 MHzMC68HC11K1VFU4–40 ° to + 85 ° C$DCNo ROM, No EEPROM2 MHz MC68HC11K0CFU23 MHz MC68HC11K0CFU34 MHzMC68HC11K0CFU4–40 ° to + 105 °C$DCNo ROM, No EEPROM2 MHz MC68HC11K0VFU23 MHz MC68HC11K0VFU34 MHzMC68HC11K0VFU4元器件交易网M68HC11 K Series MOTOROLA84-Pin CLCC (Windowed)–40 ° to + 85 ° C$DFEPROM2 MHz MC68HC711K4CFS23 MHz MC68HC711K4CFS34 MHzMC68HC711K4CFS4–40 ° to + 105 ° C$DFEPROM2 MHz MC68HC711K4VFS23 MHz MC68HC711K4VFS34 MHzMC68HC711K4VFS4–40 ° to + 125 ° C$DFEPROM2 MHz MC68HC711K4MFS23 MHz MC68HC711K4MFS34 MHzMC68HC711K4MFS4Table 2 Extended Voltage (3.0 Vdc to 5.5 Vdc) Device Ordering InformationPackage Temperature Description Frequency MC Order Number 84-Pin PLCC–20 ° to + 70 ° CCustom ROM 1 MHz MC68L11K4FN13 MHz MC68L11K4FN3No ROM1 MHz MC68L11K1FN13 MHz MC68L11K1FN3No ROM, No EEPROM 1 MHz MC68L11K0FN13 MHz MC68L11K0FN3Custom ROM, No EEPROM1 MHz MC68L11K3FN13 MHz MC68L11K3FN380-Pin QFP–20 ° to + 70 ° CCustom ROM 1 MHz MC68L11K4FU13 MHz MC68L11K4FU3No ROM1 MHz MC68L11K1FU13 MHz MC68L11K1FU3No ROM, No EEPROM 1 MHz MC68L11K0FU13 MHz MC68L11K0FU3Custom ROM, No EEPROM1 MHz MC68L11K3FU13 MHzMC68L11K3FU3Table 1 Standard Device Ordering Information (Continued)Package Temperature CONFIG Description Frequency MC Order Number 元器件交易网元器件交易网Table 3 Custom ROM Device Ordering InformationPackage Temperature Description Frequency MC Order Number84-Pin PLCC–40°to + 85°C Custom ROM 2 MHz MC68HC11K4CFN23 MHz MC68HC11K4CFN34 MHz MC68HC11K4CFN4–40°to + 105°C Custom ROM 2 MHz MC68HC11K4VFN23 MHz MC68HC11K4VFN34 MHz MC68HC11K4VFN4–40°to + 125°C Custom ROM 2 MHz MC68HC11K4MFN23 MHz MC68HC11K4MFN34 MHz MC68HC11K4MFN4–40°to + 85°C Custom ROM, No EEPROM 2 MHz MC68HC11K3CFN23 MHz MC68HC11K3CFN34 MHz MC68HC11K3CFN4–40°to + 105°C Custom ROM, No EEPROM 2 MHz MC68HC11K3VFN23 MHz MC68HC11K3VFN34 MHz MC68HC11K3VFN4–40°to + 125°C Custom ROM, No EEPROM 2 MHz MC68HC11K3MFN23 MHz MC68HC11K3MFN34 MHz MC68HC11K3MFN480-Pin QFP–40°to + 85°C Custom ROM 2 MHz MC68HC11K4CFU23 MHz MC68HC11K4CFU34 MHz MC68HC11K4CFU4–40°to + 105°C Custom ROM 2 MHz MC68HC11K4VFU23 MHz MC68HC11K4VFU34 MHz MC68HC11K4VFU4–40°to + 85°C Custom ROM, No EEPROM 2 MHz MC68HC11K3CFU23 MHz MC68HC11K3CFU34 MHz MC68HC11K3CFU4–40°to + 105°C Custom ROM, No EEPROM 2 MHz MC68HC11K3VFU23 MHz MC68HC11K3VFU34 MHz MC68HC11K3VFU4MOTOROLA M68HC11 K SeriesM68HC11 K Series MOTOROLAFigure 1 Pin Assignments for 84-Pin PLCC/CLCCP B 6/A D D R 14P A 0/I C 3P B 7/A D D R 15P B 1/A D D R 9P B 4/A D D R 12P B 3/A D D R 11V S S P B 5/A D D R 13P B 2/A D D R 10P A 2/I C 1P A 3/O C 5/I C 4/O C 1P A 4/O C 4/O C 1P A 5/O C 3/O C 1P A 6/O C 2/O C 1V D DP A 1/I C 2PG7/R/WPG6PH7/CSPROGPH6/CSGP2 PH5/CSGP1 PH4/CSIO PH3/PW4PH2/PW3PH1/PW2 PH0/PW1XIRQ/V PPE 2TEST161TEST151V DD V SSTEST141PC6/DATA6V DD V SS PC7/DATA7 PC5/DATA5 PC4/DATA4PD2/MISO PD1/TxD PD0/RxD MODA/LIR MODB/V STBY RESET XTAL EXTAL XOUT E P G 0/X A 13P E 5/A N 5A V D DP E 4/A N 4P E 6/A N 6P E 7/A N 7P E 3/A N 3V R H V R L P E 0/A N 0P E 1/A N 1P E 2/A N 2A V S SP F 7/A D D R 7P F 6/A D D R 6P F 5/A D D R 5PC3/DATA3PG5/XA18P F 4/A D D R 4P B 0/A D D R 8P A 7/P A I /O C 1P D 5S S P D 4/S C K P D 3/M O S IP F 3/A D D R 3P F 2/A D D R 2P F 1/A D D R 1P F 0/A D D R 0PC2/DATA2PC1/DATA1PC0/DATA0IRQPG4/XA17PG3/XA16PG2/XA15PG1/XA141. Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry.2. V PPE applies only to devices with EPROM.元器件交易网MOTOROLA M68HC11 K SeriesFigure 2 Pin Assignments for 80-Pin 14 mm X 14 mm TQFPX T A L E E X T A L P D 1/T x D M O D B /V S T B Y M O D A L I R V D D R E S E T P D 0/R x D P C 6/D A T A 6P C 5/D A T A 5P C 4/D A T A 4P C 3/D A T A 3P C 2/D A T A 2V S SP C 7/D A T A 71415123456789455958575655545352515010111213494847461660PB6/ADDR14PB5/ADDR13PA3/OC5/IC4/OC1PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1PA7/PAI/OC1PD5/SS PD4/SCK PD3/MOSI PA1/IC2PA2/IC1PA0/IC3V DD V SSPB7/ADDR15PE2/AN2V RL PE0/AN0 PE1/AN1 PE3/AN3 PE4/AN4PF0/ADDR0PF1/ADDR1PF2/ADDR2PF3/ADDR3PF4/ADDR4PF5/ADDR5PF6/ADDR6PF7/ADDR7AV SS V RH 77767574737071686766657978698028293031323321222324252627343536P B 0/A D D R 8P H 3/P W 4P H 0/P W 1P H 4/C S I O P H 2/P W 3P H 1/P W 2P H 5/C S G P 1V S SV D D X I R Q P H 7C S P R O G P H 6/C S G P 2P G 7/R W P G 6P G 5/X A 18P G 4/X A 17MC68HC11K SERIES6444PE5/AN5PB4/ADDR1217P G 3/X A 1637P D 2/M I S O 72636261P C 1/D A T A 1P C 0/D A T A 0I R QP G 0/X A 13P G 2/X A 15P G 1/X A 14383940PB3/ADDR11PB2/ADDR10PB1/ADDR9181920PE6/AN6PE7/AN7AV DD434241M68HC11 K Series MOTOROLAFigure 3 M68HC11 K-Series Block DiagramV RL V RH PE0PE1PE2PE3PE4PE5PE6PE7PH0PH1PH2PH3PH4PH5PH6PH7PD0PD1PD2PD3PD4PD5MODB/MODA/PA0PA1PA2PA3PA4PA5PA6PA7PC0PC1PC2PC3PC4PC5PC6PC7PF0PF1PF2PF3PF4PF5PF6PF7PB0PB1PB2PB3PB4PB5PB6PB7XIRQ/V PPE IRQRESET XTAL EXTAL E *XOUT LIR V STBY PG0PG1PG2PG3PG4PG5PG6PG7V DD V SS AV DD AV SS *XOUT pin omitted on 80-pin QFP.元器件交易网TABLE OF CONTENTSSection Page1Features12Operating Modes112.1Single-Chip Operating Mode (11)2.2Expanded Operating Mode (11)2.3Bootstrap Mode (11)2.4Special Test Mode (11)2.5Mode Selection (11)3On-Chip Memory143.1Memory Map and Register Block (14)3.2RAM (17)3.3ROM/EPROM (18)3.4EEPROM (22)3.5Configuration Control Register (CONFIG) (24)3.6Security Feature (25)4Memory Expansion and Chip Selects274.1Memory Expansion (27)4.2Overlap Guidelines (30)4.3Chip Selects (30)4.3.1Program Chip Select (CSPROG) (31)4.3.2I/O Chip Select (CSIO) (31)4.3.3General-Purpose Chip Selects (CSGP1, CSGP2) (32)4.3.4Chip Select Priorities (32)4.3.5Chip Select Control Registers (32)4.3.6Examples of Memory Expansion Using Chip Selects (35)5Resets and Interrupts386Parallel Input/Output427Serial Communications Interface498Serial Peripheral Interface569Analog-to-Digital Converter6010Main Timer6410.1Real-Time Interrupt (70)11Pulse Accumulator7112Pulse-Width Modulation Timer7412.1PWM Boundary Cases (78)MOTOROLA M68HC11 K Series元器件交易网REGISTER INDEXCCFORC Timer Compare Force$000B 66CONFIG System Configuration Register$003F 25COPRST Arm/Reset COP Timer Circuitry$003A 40CSCSTR Chip Select Clock Stretch$005A 33CSCTL Chip Select Control$005B 32DDDRA Data Direction Register for Port A $0001 42DDRB Data Direction Register for Port B$0002 43DDRF Data Direction Register for Port F $0003 46DDRG Data Direction Register for Port G$007F 47DDRH Data Direction Register for Port H$007D 46EEPROG EPROM Programming Control $002B 19GGPCS1A General-Purpose Chip Select 1 Address $005C 33GPCS1C General-Purpose Chip Select 1 Control $005D 34GPCS2A General-Purpose Chip Select 2 Address $005E 34GPCS2C General-Purpose Chip Select 2 Control $005F 34HHPRIO Highest Priority I-Bit Interrupt and Miscellaneous $003C 11, 40IINIT RAM and Register Mapping $003D 18INIT2EEPROM Mapping $0037 24MMMSIZ Memory Mapping Size$0056 28MMWBR Memory Mapping Window Base$0057 29OOC1D Output Compare 1 Data $000D 66OC1M Output Compare 1 Mask $000C 66OPT2System Configuration Options 2 $0038 12, 44, 59OPTION System Configuration Options$0039 39PPACNT Pulse Accumulator Counter$0027 73PACTL Pulse Accumulator Control $0026 73PGAR Port G Assignment$002D 28, 47PORTA Port A Data $0000 42PORTB Port B Data$0004 43PORTC Port C Data$0006 43PORTE Port E Data$000A 46PORTF Port F Data$0005 46PORTG Port G Data$007E 47PORTH Port H Data$007C 46PPAR Port Pull-Up Assignment $002C 48PPROG EEPROM Programming Control $003B 22PWCLK Pulse-Width Modulation Clock Select $0060 62, 76M68HC11 K Series MOTOROLA元器件交易网PWCNT[4:1]Pulse-Width Modulation Timer Counter 1 to 4 $0064–$0067 77PWDTY[4:1]Pulse-Width Modulation Timer Duty Cycle 1 to 4 $006C–$006F 78PWEN Pulse-Width Modulation Timer Enable $0063 77PWPER[4:1]Pulse-Width Modulation Timer Period 1 to 4 $0068–$006B 78PWPOL Pulse-Width Modulation Timer Polarity $0061 62, 76PWSCAL Pulse-Width Modulation Timer Prescaler $0062 63, 77SSCBDH/L SCI Baud Rate Control High/Low$0070, $0071 52SCCR1SCI Control 1 $0072 45, 52SCCR2SCI Control 2 $0073 53SCSR1SCI Status Register 1 $0074 54SCSR2SCI Status Register 2 $0075 55SPCR Serial Peripheral Control $0028 45SPCR Serial Peripheral Control Register$0028 57SPDR SPI Data $002A 58SPSR Serial Peripheral Status Register$0029 58TTCNT Timer Count $000E, $000F 66TCTL2Timer Control 2$0021 67TFLG2Timer Interrupt Flag 2 $0025 69, 72TI4/O5Timer Input Capture 4/Output Compare 5 $001E–$001F 67TMSK1Timer Interrupt Mask 1 $0022 68TMSK2Timer Interrupt Mask 2 $0024 68, 72TOC1–TOC4Timer Output Compare $0016–$001D 67MOTOROLA M68HC11 K Series2 Operating ModesThe M68HC11 K-series MCUs have four modes of operation that directly affect the address space.These modes are described as follows.2.1 Single-Chip Operating ModeIn single-chip operating mode, the M68HC11 K-series MCUs are stand-alone microcontrollers with no external address or data bus. Addressing range is 64 Kbytes and is limited to on-chip resources. Refer to the memory map diagram.2.2 Expanded Operating ModeIn expanded operating mode, the MCU has a 64 Kbyte address range and, using the expansion bus, can access external resources within the 64 Kbyte space. This space includes the same on-chip mem-ory addresses used for single-chip mode, in addition to addressing capabilities for external peripheral and memory devices. Addressing beyond 64 Kbytes is available only in expanded mode using the on-chip, register-based memory mapping logic. The additional address lines for memory expansion (XA[18:13]) are implemented as alternate functions of port G. The expansion bus (external address and data buses) is made up of ports B, C, and F, and the R/W signal. In expanded operating mode, high order address bits are output on the port B pins, low order address bits on the port F pins, and the data bus on port C. Refer to the memory map diagram.2.3 Bootstrap ModeBootstrap mode allows special-purpose programs to be loaded into internal RAM. The MCU contains 448 bytes of bootstrap ROM which is enabled and present in the memory map only when the device is in bootstrap mode. The bootstrap ROM contains a program which initializes the SCI and allows the user to download up to 768 bytes of code into on-chip RAM. After a four-character delay, or after receiving the character for address $037F, control passes to the loaded program at $0080. Refer to the memory map diagram. Refer also to Application Note M68HC11 Bootstrap Mode (AN1060/D).2.4 Special Test ModeSpecial test mode is used primarily for factory testing. In this operating mode, ROM/EPROM is removed from the address space and interrupt vectors are accessed externally at $BFC0–$BFFF.2.5 Mode SelectionOperating modes are selected by a combination of logic levels applied to two input pins (MODA and MODB) during reset. The logic level present (at the rising edge of reset) on these inputs is reflected in bits in the HPRIO register. After reset, the operating mode may be changed according to the table con-tained in the description of the HPRIO register.The functions of two features that are enabled by bits in OPT2 register are dependent upon the operat-ing mode. LIR driven is enabled with the LIRDV bit. Internal read visibility/not E is enabled with the IRVNE bit. Refer to the OPT2 register description that follows HPRIO.HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous $003C Bit 7654321Bit 0RBOOT*SMOD*MDA*PSEL4PSEL3PSEL2PSEL1PSEL0RESET:0 0 000110Single Chip00100110Expanded11000110Bootstrap01100110Special Test *The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up.RBOOT — Read Bootstrap ROM/EPROMValid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes.0 = Bootstrap ROM disabled and not in map1 = Bootstrap ROM enabled and in map at $BE00–$BFFF SMOD and MDA —Special Mode Select and Mode Select AThese two bits can be read at any time. They can be written anytime in special modes. MDA can only be written once in normal modes. SMOD cannot be set once it has been cleared.PSEL[4:0] —Priority Select Bits [4:0]Refer to 5 Resets and Interrupts . *Can be written only once in normal modes. Can be written anytime in special modes.LIRDV —LIR DrivenIn single-chip and bootstrap modes, this bit has no meaning or effect. The LIR pin is normally configured for wired-OR operation (only pulls low). In order to detect consecutive instructions in a high-speed ap-plication, this signal can be made to drive high for a short time to prevent false triggering.0 = LIR not driven high out of reset1 = LIR driven high for one quarter cycle to reduce transition time CWOM —Port C Wired-OR ModeRefer to 6 Parallel Input/Output . Bit 5 —Not implementedAlways read zeroIRVNE —Internal Read Visibility/Not EIRVNE can be written only once in normal modes (SMOD = 0). In special modes IRVNE can be written any time. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero. In expanded modes this bit determines whether IRV is on or off.0 = No internal read visibility on external bus1 = Data from internal reads is driven out the external data bus.In single-chip modes this bit determines whether the E clock drives out from the chip.0 = E is driven out from the chip.1 = E pin is driven low. Refer to the following table.InputsLatched at ResetMODB MODA ModeSMOD MDA 10Single Chip 0011Expanded 0100Bootstrap 1001Special Test11OPT2 — System Configuration Options 2$0038Bit 7654321Bit 0LIRDVCWOM —IRVNE*LSBF SPR2XDV1XDV0RESET:—Mode IRVNE Out of ResetE Clock Out of Reset IRV Out of Reset IRVNE Affects OnlyIRVNE Can Be Written Single Chip 0On Off E Once Expanded 0On Off IRV Once Boot0On Off E Anytime Special Test1OnOnIRVAnytimeLSBF —LSB First EnableRefer to 8 Serial Peripheral Interface.SPR2 —SPI Clock Rate SelectRefer to 8 Serial Peripheral Interface.XDV[1:0] —XOUT Clock Divide SelectControls the frequency of the clock driven out of the XOUT pinXDV [1:0]XOUT = EXTALDivided ByFrequency atEXTAL = 8 MHzFrequency atEXTAL = 12 MHzFrequency atEXTAL = 16 MHz0 018 MHz12 MHz16 MHz0 14 2 MHz 3 MHz 4 MHz1 06 1.3 MHz2 MHz 2.7 MHz 1 18 1 MHz 1.5 MHz 2 MHz3 On-Chip MemoryIn general, K-series MCUs have 768 bytes RAM, 640 bytes EEPROM, and 24 Kbytes ROM/EPROM.Some devices in the series have portions of their memory resources disabled. Some have ROM and some have EPROM replacing ROM. The following paragraphs describe the memory systems of devices in the series.3.1 Memory Map and Register BlockThe INIT, INIT2, and CONFIG registers control the presence and location of the registers, RAM, EE-PROM, and ROM/EPROM in the 64 Kbyte CPU address space. The 128-byte register block originates at $0000 after reset and can be placed at any 4 Kbyte boundary ($x000) after reset by writing an ap-propriate value to the INIT register. Refer to Figure 4.Figure 4 Memory MapEXPANDED24 KBYTES ROM/EPROM(CAN BE REMAPPED TO $2000–$7FFF OR$A000–$FFFF BY THE CONFIG REGISTER)FFC0FFFFNORMAL MODEINTERRUPTVECTORS128-BYTE REGISTER BLOCK (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER)768 BYTES RAM(CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER)SINGLE CHIPBOOTSTRAPSPECIAL TEST$0000$1000$A000$FFFFx000x07F A000FFFFBFC0BFFFSPECIAL MODE INTERRUPT VECTORSBOOT ROM(ONLY PRESENT INBOOTSTRAP MODE)BE00x080x37F 640 BYTES EEPROM(CAN BE REMAPPED TO ANY4K PAGE BY THE INIT2 REGISTER)RESERVED (SPECIAL TEST MODE ONLY)NOTE: ROM/EPROM can be enabled in special test mode by setting ROMON bit in the config register after reset.Figure 5 RAM and Register MappingTable 4 M68HC11 K Series Register and Control Bit Assignments(Can be remapped to any 4-Kbyte boundary)Bit 7654321Bit 0$0000PA7PA6PA5PA4PA3PA2PA1PA0PORTA $0001DDA7DDA6DDA5DDA4DDA3DDA2DDA1DDA0DDRA $0002DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0DDRB $0003DDF7DDF6DDF5DDF4DDF3DDF2DDF1DDF0DDRF $0004PB7PB6PB5PB4PB3PB2PB1PB0PORTB $0005PF7PF6PF5PF4PF3PF2PF1PF0PORTF $0006PC7PC6PC5PC4PC3PC2PC1PC0PORTC $0007DDC7DDC6DDC5DDC4DDC3DDC2DDC1DDC0DDRC $000800PD5PD4PD3PD2PD1PD0PORTD $000900DDD5DDD4DDD3DDD2DDD1DDD0DDRD $000A PE7PE6PE5PE4PE3PE2PE1PE0PORTE $000B FOC1FOC2FOC3FOC4FOC5000CFORC $000C OC1M7OC1M6OC1M5OC1M4OC1M3000OC1M $000D OC1D7OC1D6OC1D5OC1D4OC1D3000OC1D $000E Bit 1514131211109Bit 8TCNT (High)$000F Bit 7654321Bit 0TCNT (Low)$0010Bit 1514131211109Bit 8TIC1 (High)$0011Bit 7654321Bit 0TIC1 (Low)$0012Bit 1514131211109Bit 8TIC2 (High)$0013Bit 7654321Bit 0TIC2 (Low)$0014Bit 1514131211109Bit 8TIC3 (High)$0000$007F $0080$02FF $0300$037F$407F$4000$12FF$1080$107F $1000$0000$007F$0000$007F $0080$02FF INIT = $00REG @ $0000RAM @ $0080INIT = $10REG @ $0000RAM @ $1000INIT = $04REG @ $4000RAM @ $0000REGISTER BLOCK REGISTER BLOCK RAM A RAM A RAM BRAM BRAM A RAM BREGISTER BLOCKBit 7654321Bit 0$0015Bit 7654321Bit 0TIC3 (Low) $0016Bit 1514131211109Bit 8TOC1(High) $0017Bit 7654321Bit 0TOC1 (Low) $0018Bit 1514131211109Bit 8TOC2 (High) $0019Bit 7654321Bit 0TOC2 (Low) $001A Bit 1514131211109Bit 8TOC3 (High) $001B Bit 7654321Bit 0TOC3 (Low) $001C Bit 1514131211109Bit 8TOC4 (High) $001D Bit 7654321Bit 0TOC4 (Low) $001E Bit 1514131211109Bit 8TI4/O5 (High) $001F Bit 7654321Bit 0TI4/O5 (Low) $0020OM2OL2OM3OL3OM4OL4OM5OL5TCTL1 $0021EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2 $0022OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I TMSK1 $0023OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F TFLG1 $0024TOI RTII PAOVI PAII00PR1PR0TMSK2 $0025TOF RTIF PAOVF PAIF0000TFLG2 $00260PAEN PAMOD PEDGE0I4/O5RTR1RTR0PACTL $0027Bit 7654321Bit 0PACNT $0028SPIE SPE DWOM MSTR CPOL CPHA SPR1SPR0SPCR $0029SPIF WCOL0MODF000Bit 0SPSR $002A Bit 7654321Bit 0SPDR $002B MBE0ELAT EXCOL EXROW T1T0EPGM EPROG* $002C0000HPPUE GPPUE FPPUE BPPUE PPAR $002D00PGAR5PGAR4PGAR3PGAR2PGAR1PGAR0PGAR $002E Reserved $002F Reserved $0030CCF0SCAN MULT CD CC CB CA ADCTL $0031Bit 7654321Bit 0ADR1 $0032Bit 7654321Bit 0ADR2 $0033Bit 7654321Bit 0ADR3 $0034Bit 7654321Bit 0ADR4 $0035BULKP LVPEN BPRT4PTCON BPRT3BPRT2BPRT1BPRT0BPROT $0036Reserved $0037EE3EE2EE1EE00000INIT2 $0038LIRDV CWOM0IRVNE LSBF SPR2XDV1XDV0OPT2 $0039ADPU CSEL IRQE DLY CME FCME CR1CR0OPTION $003A Bit 7654321Bit 0COPRST $003B ODD EVEN LVPI BYTE ROW ERASE EELAT EEPGM PPROG $003C RBOOT SMOD MDA PSEL4PSEL3PSEL2PSEL1PSEL0HPRIO $003D RAM3RAM2RAM1RAM0REG3REG2REG1REG0INIT $003E TILOP0OCCR CBYP DISR FCM FCOP0TEST1 $003F ROMAD1CLKX PAREN NOSEC NOCOP ROMON EEON CONFIG $0040Reserved to$0055Reserved $0056MXGS2MXGS1W2SZ1W2SZ000W1SZ1W1SZ0MMSIZ $0057W2A15W2A14W2A130W1A15W1A14W1A130MMWBRBit 7654321Bit 0$00580X1A18X1A17X1A16X1A15X1A14X1A130MM1CR $00590X2A18X2A17X2A16X2A15X2A14X2A130MM2CR $005A IOSA IOSB GP1SA GP1SB GP2SA GP2SB PCSA PCSB CSCSTR $005B IOEN IOPL IOCSA IOSZ GCSPR PCSEN PCSZA PCSZB CSCTL $005C G1A18G1A17G1A16G1A15G1A14G1A13G1A12G1A11GPCS1A $005D G1DG2G1DPC G1POL G1AV G1SZA G1SZB G1SZC G1SZD GPCS1C $005E G2A18G2A17G2A16G2A15G2A14G2A13G2A12G2A11GPCS2A $005F0G2DPC G2POL G2AV G2SZA G2SZB G2SZC G2SZD GPCS2C $0060CON34CON12PCKA2PCKA10PCKB3PCKB2PCKB1PWCLK $0061PCLK4PCLK3PCLK2PCLK1PPOL4PPOL3PPOL2PPOL1PWPOL $0062Bit 7654321Bit 0PWSCAL $0063TPWSL DISCP00PWEN4PWEN3PWEN2PWEN1PWEN $0064Bit 7654321Bit 0PWCNT1 $0065Bit 7654321Bit 0PWCNT2 $0066Bit 7654321Bit 0PWCNT3 $0067Bit 7654321Bit 0PWCNT4 $0068Bit 7654321Bit 0PWPER1 $0069Bit 7654321Bit 0PWPER2 $006A Bit 7654321Bit 0PWPER3 $006B Bit 7654321Bit 0PWPER4 $006C Bit 7654321Bit 0PWDTY1 $006D Bit 7654321Bit 0PWDTY2 $006E Bit 7654321Bit 0PWDTY3 $006F Bit 7654321Bit 0PWDTY4 $0070BTST BSPL0SBR12SBR11SBR10SBR9SBR8SCBDH $0071SBR7SBR6SBR5SBR4SBR3SBR2SBR1SBR0SCBDL $0072LOOPS WOMS0M WAKE ILT PE PT SCCR1 $0073TIE TCIE RIE ILIE TE RE RWU SBK SCCR2 $0074TDRE TC RDRF IDLE OR NF FE PF SCSR1 $00750000000RAF SCSR2 $0076R8T8000000SCDRH $0077R7/T7R6/T6R5/T5R4/T4R3/T3R2/T2R1/T1R0/T0SCDRL $0078Reserved to$007B Reserved $007C PH7PH6PH5PH4PH3PH2PH1PH0PORTH $007D DDH7DDH6DDH5DDH4DDH3DDH2DDH1DDH0DDRH $007E PG7PG6PG5PG4PG3PG2PG1PG0PORTG $007F DDG7DDG6DDG5DDG4DDG3DDG2DDG1DDG0DDRG *MC68HC711K4 only.3.2 RAMAll members of the M68HC11 K series have 768 bytes of static RAM. The RAM can be mapped to any 4-Kbyte boundary. Upon reset, the RAM is mapped at $0080–$037F. The registers are also mapped to this 4-Kbyte boundary. In previous versions of the M68HC11 devices the register block being mapped to the same boundary would cause the portion of RAM overlapped by the register block to be lost. How-ever, a new RAM remapping feature has been added which automatically allows all of the RAM to be accessible even if the register block overlaps the RAM. Because the registers are located in the same4-Kbyte boundary after reset, 128 bytes of the RAM are located at $0300 to $037F. Remapping is ac-complished by writing appropriate values to the INIT register. Refer to the register and RAM mapping examples following the memory map diagram.When power is removed from the MCU, RAM contents may be preserved using the MODB/V STBY pin.A power source (2.0 Vdc –V DD) applied to this pin protects all 768 bytes of RAM.INIT —RAM and Register Mapping $003DBit 7654321Bit 0RAM3RAM2RAM1RAM0REG3REG2REG1REG0RESET:00000000Can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode.RAM[3:0] —Internal RAM Map PositionThese bits determine the upper four bits of the RAM address. At reset RAM is mapped to $0000. Nor-mally the RAM would be mapped at $0000–$02FF (768 bytes). However, the register block overlaps the first 128 bytes of RAM, causing them to be remapped to $0300–$037F. Refer to Figure 4 and Fig-ure 5.REG[3:0] —128-Byte Register Block Map PositionThese bits determine the upper four bits of the register block starting address. At reset registers are mapped to $0000 and overlap the first 128 bytes of RAM, causing them to be remapped to $0300–$037F. Refer to Figure 4 and Figure 5.3.3 ROM/EPROMStandard devices have 24 kbytes of EPROM (OTPROM in a non-windowed package). Custom ROM devices have a 24-Kbyte ROM array that is mask programmed at the factory to customer specifications.The MC68HC11K0, MC68HC11K1, MC68L11K0, and MC68L11K1 have no ROM/EPROM. Refer to the ordering information tables.The ROMAD and ROMON control bits in the CONFIG register control the position and presence of ROM/EPROM in the memory map. The ROM/EPROM can be mapped at $2000–$7FFF or $A000–$FFFF. If it is mapped to $A000–$FFFF, vector space is included. In single-chip mode the ROM/ EPROM is forced to $A000–$FFFF (ROMAD = 1) and enabled (ROMON = 1), regardless of the value in the CONFIG register. This ensures that there will be ROM/EPROM at the vector space. In special test mode, the ROMON bit is forced to zero so that the ROM/EPROM is removed from the memory map.Refer to Figure 4.Programming EPROM requires an external 12.25 volt nominal power supply (V PPE) that must be ap-plied to the XIRQ/V PPE pin. Three methods are used to program and verify EPROM/OTPROM.Normal EPROM/OTPROM programming can be accomplished in any operating mode. Normal pro-gramming is accomplished using the EPROM/OTPROM programming register (EPROG). The EPROG register enables the EPROM programming voltage, controls the latching of data to be programmed, and selects single- or multiple-byte programming.To program the EPROM, complete the following steps using the EPROG register:1.Set the ELAT bit in EPROG register. EELAT bit in PPROG must be cleared as it negates thefunction of the ELAT bit.2.Write data to the desired address.3.Turn on programming voltage to the EPROM array by setting the EPGM bit in EPROG register.4.Delay for 2 ms or more, as appropriate.5.Clear the EPGM bit in EPROG to turn off the programming voltage.。

空调的原理

电气系统
组成
– – – – – – – – 风扇电动机制冷压缩机电动机启动继电器热保护继电器温度控制器选择开关中间继电器控制开关及旋钮等
电气系统
电动机
– 单相异步电动机（小型家用窗式及分体式空调器的压缩机电动机和风扇电机）
电动机的控制电器
– 实现压缩机和风扇电动机的启动和停止及正常运行 – 常用的控制电器
R28 10K UP R27 10K J101 R26 10K R13 10K C20 104 C19 104 C18 SW107 104 POWER GND R25 1K R24 1K R23 1K R22 1K R21 100 R20 100 R19 100 R18 100 R17 100 R16 100 R15 100 R14 100
制热循环过程
– 电磁阀控制制冷工质按1－2－6－5－4－3 －2－1流动，使经压缩机压缩而得到的高压高温工质过热蒸气进入室内热交换器，则室内换热器成为冷凝器，向室内空气散热，空调器向室外送出热风，使室温升高；而室外换热器成为蒸发器，工质液体在低压条件蒸发，从室外空气中吸热，使室内温度升高。
单冷型空调器工作原理单冷型空调器
温度调节
– 由于轴流风扇2连续不断地迫使室外空气流过冷凝器，而使其中的高压高温工质蒸气最后被冷凝成液态后流入毛细管6中被节流，降压成为低压低温液体进入蒸发器10 中，吸收其周围空气的热量，使经过蒸发器外部的空气得到冷却降温。
单冷型空调器工作原理单冷型空调器
核心控制电路
电脑芯片
– MC68HC705SR3（MC68HC908JL3）
继电器输出电路
– 2003（达林顿管），12V 10A 继电器

JL3芯片中文版

tips
通过静态测试，我们旨在了解芯片和外围电路的关系。对使用单片机的应用系统而言，单片机只是系统的一小部分。单片机本身不能为用户提供实质性的功能服务，也就是主功能是由其他硬件提供的，单片机只是参与控制。单片机软件与电脑软件不同，各厂家单片机所使用的编程语言（汇编语言）不同，使用C语言编程虽然可以脱离汇编语言，但也必须和具体的单片机结合，用专用的编译软件去编译。要理解一个系统，必须同时学习和了解系统模型，电路硬件和单片机三方面。
tips 有的管脚只能用于输入或只能用于输出，是单向管脚如IRQ管脚。有的管脚既能用于输入也可用于输出，是双向管脚，文件中标为 I/O PIN，如PTA0--PTA6， PTB0—PTB7，PTD0—PTD7，它们的方向由程序对管脚方向寄存器设置决定。
2、芯片电流和晶振频率、功耗 • 芯片电流和晶振频率在一定范围内接近正比关系，因此在允许的情况下，可以用降低晶振频率的方法降低耗电,或降低VDD 来降低耗电。
3、口电容
• 口电容是芯片布线带来的，属于被动型电器指标，不是芯片设计故意作的电容，口电容对芯片的高频使用有影响
4、上拉电阻和下拉电阻
• 上拉就是将不确定的信号通过一个电阻嵌位在高电平！电阻同时起限流作用！下拉同理！在引脚悬空时有确定的状态
•
单片机芯片管脚
• • • • • 复习第一单元的内容 MC68HC908JL3芯片管脚管脚三态等重要知识点管脚电气
实物投影
管脚的电性能参数测试说明
4.5 to 5.5 Vdc,TA = TL to TH, (2).典型值是在25度时对电压中间点的测量平均值 (3).运行IDD测量条件为：外部方波时钟输入，所有的口设置为输入口，无DC负载，所有输出电容小于100pF.,OSC2电容的线性影响IDD的测量。所有模式置位。 (4).Wait IDD测量条件为：外部方波时钟输入，所有的口设置为输入口，无DC负载，所有输出电容小于100pF.,OSC2电容的线性影响IDD的测量。 (5).STOP IDD测量条件为：OSC1接地，口无电流，LVI功能被屏蔽 (6).最大值是指POR(上电复位)可靠的最大电压 (7) .如果在内部POR(上电复位)退出前，未达到最小VDD，RST复位管脚必须被外部强行拉低直至VDD达到最小值为止。 (8). RPU1和RPU2是在VDD =5.0V时测量的

HC705单片机的LED驱动技术

HC705单片机的LED驱动技术
本文介绍了使用MC68HC705J1A 大电流引脚，不使用外部晶体管放大电路，直接驱动LED 的的方法。

文中所提出的计算公式对不同的单片机（MCU）（低电平电流IOL 不同）都适用。

只是公式中的最大低电平电流要改变。

正常的HCOMS I/O 引脚具有足够的电流来驱动HCMOS 或TTL 电路的输入。

这些引脚通常在输出低电平0.4V 时能够吸入1.6mA 的电流。

但是在许多应用
场合，当1 个CMOS 输出引脚用于驱动较大电流的设备时，就显得力不从心了。

例如LED（发光二极管）、前级运算放大器等，大约需要10mA 电流。

通
常的做法是再加驱动电路，如：用三极管的放大电路驱动或用其他如75452 等驱动能力大的集成电路来驱动。

MC68HC705J1A 有4 个I/O 引脚（PA4～PA7），在输出低电平0.4V 的吸电流能力为10mA,这样就有足够的电流来驱动LED 或其他需要大电流驱动的设
备了。

1 个简单的例子如图所示。

为了得到第1 个电阻R 的值，我们利用欧姆定律，电源电压除以吸入电流：tips:感谢大家的阅读，本文由我司收集整编。

仅供参阅！。

单片机在电热水器中的应用_周鲜成

文章编号:　1009-3818(2000)04-0060-03单片机在电热水器中的应用周鲜成(湖南商学院信息工程与信息管理系　湖南长沙　410205)摘　要:　介绍了用单片机构成电热水器控制器的基本设计方法。

利用MC68HC05系列单片机可构成一功能较为完善的电热水器控制器,控制器的设计可按总体方案、软件设计、调试、固化四个步骤进行。

其硬件系统由输入、单片机和输出三大部分组成;软件系统的设计采用模块化结构,主要由主程序、中断服务程序和若干功能模块子程序组成。

为了节电和避免等用热水情况的出现,应用了模糊控制技术,定义温度偏差和温度变化率为输入模糊量,并通过模糊控制算法推断出加热时间的提前量。

关键词:　电热水器;单片机;硬件;软件;模糊控制中图分类号:　TP368.2:TM925.32 文献标识码:　A　电热水器是一种可供洗手间、厨房、浴室使用的家用电器。

具有无污染、安全、保温时间长、使用方便等优点。

随着人民生活水平的不断提高和我国电力工业的不断发展,电热水器得到不断普及。

目前市场上有两种电热水器,连续水流式和贮水式。

前者虽具有加热速度快和体积小等优点,但功率太大,大多数家庭的供电线路难以承受。

而市场上贮水式电热水器大多数采用机械式控制器,存在控温精度低、加热时间长、可靠性差、功能单一等不足。

针对上述情况,利用先进的单片机作为控制器的核心,结合模糊控制技术,可设计出一种多功能的电热水器控制器。

根据MOTOROLA公司的MC68HC05系列单片机的资源情况,选用MC68HC05构成电热水器的控制器能够实现对所有功能的控制。

1　MC68HC05单片机简介MC68HC05系列单片机是当今功能较强、性价比较高的八位单片机之一。

它具有丰富的I/O接口功能及完善的系统保护和软件控制节电方式。

其指令系统与早期Motor ola单片机兼容,同时增加了91条新指令,包含16位乘法、除法运算指令。

具体特点如下:收稿日期:2000-09-22作者:男　36岁　讲师(1)兼容性好。

看门狗MAX705、706、813中文说明

看门狗MAX705、706、813中文说明看门狗MAX705/706/8131 概述MAX705/706/813L是一组CMOS监控电路，能够监控电源电压、电池故障和微处理器(MPU或mP)或微控制器(MCU或mC)的工作状态。

将常用的多项功能集成到一片8脚封装的小芯片内，与采用分立元件或单一功能芯片组合的电路相比，大大减小了系统电路的复杂性和元器件的数量，显著提高了系统可靠性和精确度。

该系列产品采用3种不同的8脚封装形式：DIP、SO和mMAX。

主要应用于：微处理器和微控制器系统；嵌入式控制器系统；电池供电系统；智能仪器仪表；通信系统；寻呼机；蜂窝移动电话机；手持设备；个人数字助理(PDA)；电脑电话机和无绳电话机等等。

2 功能说明2.1 RESET/RESET操作复位信号用于启动或者重新启动MPU/MCU，令其进入或者返回到预知的循环程序并顺序执行。

一旦MPU/MCU处于未知状态，比如程序“跑飞”或进入死循环，就需要将系统复位。

对于MAX705和MAX706而言，在上电期间只要Vcc大于1.0V，就能保证输出电压不高于0.4V的低电平。

在Vcc上升期间RESET维持低电平直到电源电压升至复位门限(4.65V或4.40V)以上。

在超过此门限后，内部定时器大约再维持200ms后释放RESET，使其返回高电平。

无论何时只要电源电压降低到复位门限以下(即电源跌落)，RESET 引脚就会变低。

如果在已经开始的复位脉冲期间出现电源跌落，复位脉冲至少再维持140ms。

在掉电期间，一旦电源电压Vcc降到复位门限以下，只要Vcc不比1.0V还低，就能使RESET维持电压不高于0.4V 的低电平。

MAX705和MAX706提供的复位信号为低电平RESET，而MAX813L提供的复位信号为高电平RESET，三者其它功能完全相同。

有些单片机，如INTEL的80C51系列，需要高电平有效的复位信号。

2.2 看门狗定时器MAX705/706/813L片内看门狗定时器用于监控MPU/MCU的活动。

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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
1 GENERAL DESCRIPTION 2 PIN DESCRIPTIONS
3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS
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6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET
9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS 12 MECHANICAL SPECIFICATIONS
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A MC68HC705SR3
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1 GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS 12 MECHANICAL SPECIFICATIONS A MC68HC705SR3
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Register and bit mnemonics are deﬁned in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ‘u’ is used to indicate an undeﬁned state (on reset).
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