PMB2402中文资料

Applicationsq Digital mobile cellular systems as GSM, DAMPS, JDCq Various demodulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK q Space and power saving optimizations of existing discrete demodulator circuitsFunctional DescriptionThe PMB 2402 is a single-chip single-conversion heterodyn PM-receiver with phase shifting circuitry for the I/Q-phase baseband demodulation on chip. It also includes the second local oscillator, a gain controlled second IF-amplifier, two differential operational amplifiers for baseband filtering purposes and power down circuitry.The PMB 2402 is designed for digital mobile telephones according to the GSM-standard and other digital systems.Type Version Ordering Code Package PMB 2402S V 2.1Q67000-A6072P-DSO-28-4(Shrink, SMD))PMB 2402SV 2.1Q67006-A6072P-DSO-28-4 (Shrink,SMD, Tape + Reel)GSM Receiver Circuit Preliminary Data Bipolar ICPMB 2402FeaturesqHeterodyne receiver with demodulatorq Down mixing from 900 MHz receiver band to the base bandq Demodulation and generation of I/Q-baseband componentsq Low mixer noise 10 dB (SSB)q Input high intercept point + 2 dB q Integrated 0˚ and 90˚ phase shifter q 82 dB AGC-rangeq On-chip second LO-oscillator with external tuning circuit q Two differential operational amplifiersq Low power consumption due to highly flexible power-down capabilityq Wide input frequency range up to 1 GHz q Wide IF-range from 35 MHz to 100 MHzq Wide output frequency range up to 13.5 MHz q P-DSO-28-4 shrink packageqTemperature range – 25˚C to 85˚CP-DSO-28-4Pin Configuration (top view)Pin Definitions and FunctionsPin No.Symbol Function1SOI Non-inverting in-phase signal output2SOQ Non-inverting quadratur signal output3INQ Inverting op. amp. signal output (Q)4OUTQ Non-inverting op. amp. signal output (Q) 5OUTQ Inverting op. amp. signal output (Q)6INQ Non-inverting op. amp. signal intput (Q) 7SOQ Inverting quadratur signal output8LO2E External capacitors for oscillator9LO2B VCO-tuning circuit10GND Ground11IFI Inverting IF input12IFI Non-inverting IF input13GC Gain control input14LO2O VCO-signal output15MO Inverted output of first mixer16MO Non-inverted output of first mixer17V S Supply voltage18SI Non-inverted signal input of first mixer19SI Inverted signal input of first mixer20PD1Power-down input 121LO1Non-inverting input for first local oscillator 22LO1Inverting input for first local oscillator23PD2Power-down input 224SOI Inverting in-phase signal output25INI Non-inverting op. amp. signal input (I)26OUTI Inverting op. amp. signal output (I)27OUTI Non-inverting op. amp. signal output (I) 28INI Inverting op. amp. signal input (I)Block DiagramCircuit DescriptionThe input signal SI/SI and the amplified first local oscillator signal LO1/LO1 are mixed down to an intermediate frequency (IF). The open collector output of the mixer generates a differential current at pins MO/MO which is filtered by an external resonant circuit. The resulting voltage drives an external SAW-filter.The second local oscillator signal LO2 is generated in an on chip VCO and is fed to two dividers, which generate orthogonal signals at a quarter of VCO-frequency. The internal LO-signal is fed to an additionally divider, whose output signal LO2O is fed to the RF-signal of PLL-synthesizer. The filtered IF-signal reenters the chip at the IFI/IFI input, where it is amplified and demodulated to the final baseband output frequency with each of the orthogonal signals. The resulting in-phase and quadrature signals pass through differential output drivers and appear at SOI/SOI and SOQ/SOQ outputs, respectively. The amplification of the IF-signal before the second mixer stage is performed by a gain-controlled amplifier, the gain being determined by the voltage at the gain control input GC. Two differential operational amplifiers with the input signals INI/INI (INQ/INQ) and the output signals OUTI/OUTI (OUTQ/OUTQ) can be used as active filters.Differential signals and symmetrical circuitry are used throughout, except at the signal output. Bias drivers generate internal temperature- and supply voltage-compensated reference voltages required by various circuit blocks. Switching the power down inputs PD1 and PD2 from high to low (see table) sets the circuit from its normal operating mode into a mode with reduced supply current. PD1PD2RF-Part IF-Part VCO/DivdersL L OFF OFF ONL H OFF ON ONH L ON OFF ONH H ON ON ONInternal Input / Output CircuitsElectrical CharacteristicsAbsolute Maximum RatingsThe maximum ratings may noy be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.TA= –25˚C to 85˚CParameter Symbol Limit Values Unit Remarksmin.max.Supply voltage V S– 0.57VInput/output voltage(any except open collector)VIO– 0.5– 0.5VS+ 0.57.5VVVS≤ 7 VVS≤ 7 VOpen collector output voltage (MO/MO)VOC– 0.5– 0.5VS+ 2.57.5VVVS≥ 5 VVS≥ 5 VDifferential input voltage (any differential input)VI– 33VJunction temperature T j125˚C Storage temperature T stg– 55125˚CThermal resistence (junction to ambient)Rth JA55K/WK/WPDSO-28P-DSO-28-SOperational RangeWithin the operational range the IC operates as described in the circuit description. The AC/DC-characteristics limits are not guaranteed.V S = 4.5V to 5.5V; T A = –25˚C to 85˚C; refer to test circuit 1.Note:Power levels are referred to resistance of 50ΩParameter SymbolLimit Values UnitRemarksmin.max.SI/SI input level P SI – 11dBm SI/SI input frequency f SI 1000MHz LO1/LO1 input level P LO1– 113dBm LO1/LO1 input frequency f LO11100MHz Intermediate frequency f IF 35100MHz IFI/IFI input level P IFI – 24dBm IFI/IFI input frequency f IFI 35100MHz LO2 input level P LO2– 200dBm VCO externalLO2 input frequency f LO2140400MHz VCO frequency range f VCO 120250MHz with ext. capacitors LO2O output level P LO2O 120180mVpp LO2O output frequency f LO2O 1550MHz SOI/SOI, SOQ/SOQ output Bandwidth B SO 013.5MHz – 3 dB roll off GC input voltage V GC 02V L-PD1/PD2 voltage V PDL 01V H-PD1/PD2 voltageV PDH4V SVAC/DC CharacteristicsAC/DC-characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.VS= 4.75 to 5.25V; T A = 25˚C;Parameter Symbol Limit Values Unit Test Condition TestCircuitmin.typ.max.Supply current I S 3.11211.5205.515.51524.56.81918.530mAmAmAmAPD1 = L PD2 = LPD1 = L PD2 = HPD1 = H PD2 = LPD1 = H PD2 = L1First Mixer Signal Input SI/SIInput resistance R SI172533Ω2a Input inductance L SI 3.55 6.5nH In series to R SI2a Max. input level P SI– 13– 11dBm 1 dB compr. at MO/MO1Input intercept Point PIPI023dBm G MO = 14 dB1Blocking level P B– 16– 14– 12dBm 3 dB attenuation ofwanted Signal at MO1Input interference level at f =f int Pint– 38dBm– 98 dBm interference atf = (fint+/–f LO1) X2 at MO3Input frequency f SI960MHz1Noise figure N SINSI 7.59.58109.511.5dBdBDSB-noise,f C = 900 MHzSSB-noise,f C = 900 MHzincluding optimum noisematching1Output of First Mixer MO/MO (open collector)Output resistance R MORMO 11.27161020.813kΩkΩfMO= 45 MHzfMO= 71 MHz2c2cOutput capacitance C MO0.71 1.3pF parallel to R MO2c Total output current I MO +MO 3.55 6.5mA1Power gain from Signal input GMO1314dB1Intermediate frequency fIF35100MHz1AC/DC-Characteristics (cont’d)ParameterSymbolLimit Values UnitTest ConditionTest Circuitmin.typ.max.Input of First Mixer Local Oscillator LO1/LO1Input resistance R LO1490700910Ωf LO1 = 900 MHz2a Input capacitance C LO10.711.3pF parallel to R LO12a Input level P LO1V LO1– 111783890dBm mVppsee diagram 111Input frequencyf LO11100MHz1Isolation of First Mixer From SIto MO A SI – MO 30dB f SI = 945 MHz;f LO1 = 900 MHz 1SIto LO1A SI – LO160dB f SI = 945 MHz;f LO1 = 900 MHz 1LO1to MO A LO1 – MO 50dB f SI = 945 MHz;f LO1 = 900 MHz 1LO1to SI A LO1 – SI 60dB f SI = 945 MHz;f LO1 = 900 MHz 1MO to Si A MO – SI50dB f SI = 945 MHz;f LO1 = 900 MHz 1MO to LO1A MO – LO165dBf SI = 945 MHz;f LO1 = 900 MHz1IF Input IFI/IFI Input resistance R IFI 6390117Ω2a Input capacitance C IFI 0.350.50.65pF parallel to R IFI2a Max. input level P IFI V IFI – 1789dBm mVppV GC = 2 V, 1 dB compr. atSO;see diagram 411Input intercept pointP IPI see diagram 51Input frequency f SI 35100MHz 1Noise figureN SI101114dBSSB-noise1Input for Second Local Oscillator LO2 (VCO external)Input resistanceR LO21.91.32.41.83.12.3k Ωk Ωf LO2 = 180 MHz f LO2 = 360 MHz2b 2bAC/DC-Characteristics(cont’d)Parameter Symbol Limit Values Unit Test Condition TestCircuitmin.typ.max.Input capacitance C LO20.71 1.3pF2bInput level P LO2VLO2– 2063630dBmmVppinto 50Ω 1.11.1Input frequency f LO2140400MHz 1.1 Voltage Controlled Oscillator VCO (LO2)VCO-frequency f VCO120250MHz with ext. capacitors 1.2 VCO Output LO2OOutput resistance R LO2O0.9 1.2 1.5kΩOutput capacitance C LO2O0.71 1.3pFOutput level V LO2O150120160140mVppmVppIF≤ 75 MHzIF≥ 75 MHz11Output frequency f LO2O1550MHz1 Signal Outputs SOI/SOI, SOQ/SOQOutput resistance R SO175250325ΩOutput capacitance C SO0.71 1.3pFSO frequency roll off fSO13.5MHz see diagram 6DC output level V SO 2.0 2.5V1Diff. output offset voltage VSO/SO28mV between I/I or Q/Q1Voltage gain from IF to I/Q-output GSO57– 2561– 2165– 17dBdBVGC= 0 V see dia-VGC= 2 V gram 2 + 31Gain Control Input GCGC-input voltage V GC02V1 GC-input current–I GC1µA0V≤V GC≤ 2 V1 Gain control factor F GC40dB/V F GC = d G SO/d V GCsee diagram 31AC/DC-Characteristics(cont’d)Parameter Symbol Limit Values Unit Test Condition TestCircuitmin.typ.max.Power-Down Inputs PD1, PD2L-PD input voltage V PDL01V1L-PD input current I PD1LIPD2L 0.10.2µAµA0≤V PD1, 2L≤ 1 V1H-PD input voltage V PDH4V S V1 H-PD input current I PDH10µA4≤V PD1, 2L≤V S1Differential Operational Amplifier (open loop)Slew rate SR 4.6V/µs1 Gain BandwithProd.GBW12MHz1 Voltage gain A Vo55dB1 Phase marginϕR60degr.1 Gain margin A R14dB1 Common modeRejection RatioCMRR58dB1 Offset voltage V OFF1mV1 Output voltage V OUT0.8V S–1V1Test Circuit 1Test Circuit 1.1Test Circuit 1.2Test Circuit 2aTest Circuit 2bTest Circuit 2cThe S-parameters are tested at the indicated frequency and the equivalent parallel or series circuit is calculated on this base.Test Point Test Circuit Test Frequency / MHz Pin x Pin yLO1-input impedance2a9002122SI-input impedance2a9001819IFI-input impedance2a45 (901112)LO2-input impedance2b180, 3609–MO-output impedance2c45, 711516Test Circuit 3f W = wanted input signal from received channelf int = unwanted interfering signal within band :f int =f LO –f IF / 2f LO = local oscillator signalf IFW = wanted IF signal from received channel =f LO –f Wf IFi t = unwanted IF / 2 signal from interfering channel:f IFint =f LO –f intfIF2in= unwanted harmonic signal of f IF2in :f IF2in = 2×f IFintApplication CircuitDiagram 1First Mixer Gain versus LO-Level P LO1P SI = – 40 dBm,f MO = 45 MHz Diagram 3Gain Control Characteristic Voltage Gain G SO versus GC-Voltage VGCDiagram 2Gain Control Characteristic Output LevelP SO versus input Level P IFIDiagram 4Gain Control CharacteristicMax. Input Level P IFI versus GC-Voltage V GC :(1 dB Compresion at SO)Diagram 5Gain–Control Characteristic Input Intercept Point P IPI versus GC-Voltage VGCDiagram 6Frequency Transfer Characteristic ofOutputs SOI / SOQSemiconductor Group21Package Outlines Plastic-Package, P-DSO-28-4 (Shrink) (SMD)(Dual-Small-Outlines) PMB 2402Dimensions in mm Sorts of Packing Package outlines for tubes, trays ect. are contained in our Data Book “Package Information”SMD = Surface Mounted Device元器件交易网。