74LCXH16245MTDX,74LCXH16245MTD,74LCXH16245G,74LCXH16245GX, 规格书,Datasheet 资料

© 2005 Fairchild Semiconductor Corporation DS500581May 2002Revised June 200574LCXH16245 Low Voltage 16-Bit Bidirectional Transceiver with Bushold74LCXH16245Low Voltage 16-Bit Bidirectional Transceiver with BusholdGeneral DescriptionThe LCXH16245 contains sixteen non-inverting bidirec-tional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low volt-age (2.5V or 3.3V) V CC applications with capability of inter-facing to a 5V signal environment. The device is byte controlled. Each byte has separate control inputs which could be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B Ports by placing them in a high impedance state.The LCXH16245 data inputs include active bushold cir-cuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.The LCXH16245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-ing CMOS low power dissipation.Featuress 2.3V–3.6V V CC specifications provided s 4.5 ns t PD max (V CC 3.3V), 20 P A I CC max s Power-down high impedance outputss Bushold on inputs eliminates the need for external pull-up/pull-down resistors s r 24 mA output drive (V CC 3.0V)s Implements patented noise/EMI reduction circuitry s Latch-up performance conforms to the requirements of JESD78s ESD performance:Human body model ! 2000VMachine model ! 200Vs Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)Ordering Code:Note 1: Ordering Code “G ” indicates Trays.Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Logic SymbolOrder Number Package NumberPackage Description74LCXH16245G (Note 1) (Note 2)BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide74LCXH16245MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 274L C X H 16245Connection DiagramsPin Assignment for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH HIGH Voltage LevelL LOW Voltage Level X ImmaterialZ High ImpedanceLogic DiagramPin Names DescriptionOE n Output Enable Input T/R n Transmit/Receive InputA 0–A 15Side A Inputs or 3-STATE Outputs (Bushold)B 0–B 15Side B Inputs or 3-STATE Outputs (Bushold)123456A B 0NC T/R 1OE 1NC A 0B B 2B 1NC NC A 1A 2C B 4B 3V CCV CC A 3A 4D B 6B 5GND GND A 5A 6E B 8B 7GND GND A 7A 8F B 10B 9GND GND A 9A 10G B 12B 11V CC V CC A 11A 12H B 14B 13NC NC A 13A 14JB 15NCT/R 2OE 2NCA 15Inputs OutputsOE 1T/R 1L L Bus B 0–B 7 Data to Bus A 0–A 7L H Bus A 0–A 7 Data to Bus B 0–B 7H XHIGH Z State on A 0–A 7, B 0–B 7InputsOutputsOE 2T/R 2L L Bus B 8–B 15 Data to Bus A 8–A 15L H Bus A 8–A 15 Data to Bus B 8–B 15HX HIGH Z State on A 8–A 15, B 8–B 1574LCXH16245Absolute Maximum Ratings (Note 3)Recommended Operating Conditions (Note 5)Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-mended Operating Conditions ” table will define the conditions for actual device operation.Note 4: I O Absolute Maximum Rating must be observed.Note 5: Floating or unused control inputs must be HIGH or LOW.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 7.0V V I DC Input Voltage 0.5 to V CC 0.5VV O DC Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to V CC 0.5Output in HIGH or LOW State (Note 4)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA 50V O ! V CCI O DC Output Source/Sink Current r 50mA I CC DC Supply Current per Supply Pin r 100mA I GND DC Ground Current per Ground Pin r 100mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage Operating 2.0 3.6V Data Retention1.5 3.6V I Input Voltage 0V CC V V O Output Voltage HIGH or LOW State0V CC V3-STATEV CCI OH /I OLOutput CurrentV CC 3.0V 3.6V r 24mAV CC 2.7V 3.0V r 12V CC 2.3V 2.7Vr 8T AFree-Air Operating Temperature4085q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterConditionsV CC T A 40q C to 85q C Units (V)Min MaxV IH HIGH Level Input Voltage 2.3 2.7 1.7V 2.7 3.6 2.0V IL LOW Level Input Voltage 2.3 2.70.7V2.73.60.8V OHHIGH Level Output VoltageI OH 100 P A 2.3 3.6V CC 0.2VI OH 8 mA 2.3 1.8I OH 12 mA 2.7 2.2I OH 18 mA 3.0 2.4I OH 24 mA3.0 2.2V OLLOW Level Output VoltageI OL 100 P A 2.3 3.60.2V I OL 8mA 2.30.6I OL 12 mA 2.70.4I OL 16 mA 3.00.4I OL 24 mA3.00.55I IInput Leakage CurrentDataV I V CC or GND2.33.6r 5.0P A Control O d V I d 5.52.33.6r 5.0 474L C X H 16245DC Electrical Characteristics (Continued)Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.AC Electrical CharacteristicsNote 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Parameter guaranteed by design.Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC T A 40q C to 85q C Units(V)Min MaxI I(HOLD)Bushold Input Minimum V IN 0.7V 2.345P ADrive Hold CurrentV IN 1.7V 45V IN 0.8V 3.075V IN 2.0V75I I(OD)Bushold Input Over-Drive (Note 6) 2.7300P A Current to Change State(Note 7) 300(Note 6) 3.6450(Note 7)450I OZ 3-STATE I/O Leakage V O V CC or GND 2.3 3.6r 5.0P A I OFF Power-Off Leakage Current V I or V O 5.5V 010P A I CC Quiescent Supply Current V I V CC or GND 2.3–3.620P A 'I CCIncrease in I CC per InputV IH V CC 0.6V2.3–3.6500P A SymbolParameterT A 40q C to 85q C, R L 500:UnitsV CC 3.3V r 0.3VV CC 2.7V V CC 2.5V r 0.2VC L 50 pF C L 50 pF C L 30 pF MinMax Min Max Min Max t PHL Propagation Delay 1.0 4.5 1.0 5.2 1.0 5.4ns t PLH A n to B n or B n to A n 1.0 4.5 1.0 5.2 1.0 5.4t PZL Output Enable Time1.0 6.5 1.07.2 1.08.5ns t PZH 1.0 6.5 1.07.2 1.08.5t PLZ Output Disable Time 1.0 6.4 1.0 6.9 1.07.7ns t PHZ 1.06.4 1.06.91.07.7t OSHL Output to Output Skew (Note 8) 1.0ns t OSLH1.0Symbol ParameterConditionsV CC (V)T A 25q C Units Typical V OLP Quiet Output Dynamic Peak V OL C L 50 pF, V IH 3.3V, V IL 0V 3.30.8V C L 30 pF, V IH 2.5V, V IL 0V 2.50.6V OLVQuiet Output Dynamic Valley V OLC L 50 pF, V IH 3.3V, V IL 0V 3.3 0.8VC L 30 pF, V IH 2.5V, V IL 0V2.50.6Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC Open, V I 0V or V CC 7pF C I/O Input/Output Capacitance V CC 3.3V, V I 0V or V CC8pF C PDPower Dissipation CapacitanceV CC 3.3V, V I 0V or V CC , f 10 MHz20pF74LCXH16245AC LOADING and WAVEFORMS Generic for LCX FamilyFIGURE 1. AC Test Circuit (C L includes probe and jig capacitance)Waveform for Inverting and Non-Inverting FunctionsPropagation Delay. Pulse Width and t rec Waveforms3-STATE Output Low Enable andDisable Times for Logic3-STATE Output High Enable andDisable Times for LogicSetup Time, Hold Time and Recovery Time for Logict rise and t fallFIGURE 2. Waveforms(Input Characteristics; f =1MHz, t r = t f = 3ns)Test Switch t PLH , t PHL Opent PZL , t PLZ 6V at V CC 3.3 r 0.3V, 2.7V and V CC x 2 at V CC 2.5 r 0.2Vt PZH , t PHZGNDSymbol V CC3.3V r 0.3V2.7V 2.5V r 0.2V V mi 1.5V 1.5V V CC /2V mo 1.5V 1.5V V CC /2V x V OL 0.3V V OL 0.3V V OL 0.15V V yV OH 0.3VV OH 0.3VV OH 0.15V 674L C X H 16245Schematic DiagramGeneric for LCX Family74LCXH16245 Physical Dimensions inches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A874L C X H 16245 L o w V o l t a g e 16-B i t B i d i r e c t i o n a l T r a n s c e i v e r w i t h B u s h o l dPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。