IXDN502D1

Features•Built using the advantages and compatibility of CMOS and IXYS HDMOS TM processes •Latch-Up Protected up to 2 Amps •High 2A Peak Output Current•Wide Operating Range: 4.5V to 30V •-55°C t o +125°C Ext ended Operat ing Temperat ure• High Capacitive LoadDrive Capability: 1000pF in <10ns • Matched Rise And Fall Times • Low Propagation Delay Time •Low Out put Impedance •Low Supply Current•Two Drivers in Single ChipApplications•Driving MOSFETs and IGBTs •Mot or Cont rols •Line Drivers•Pulse Generat ors•Local Power ON/OFF Switch•Switch Mode Power Supplies (SMPS)•DC t o DC Convert ers •Pulse Transformer Driver •Class D Switching Amplifiers •Power Charge PumpsGeneral DescriptionThe IXDF502, IXDI502 and IXDN502 each consist of t wo 2-Amp CMOS high speed MOSFET Gate Drivers for driving the latest IXYS MOSFETs & IGBTs. Each of the DualOutputs can source and sink 2 Amps of Peak Current while producing voltage rise and fall times of less than 15ns. The input of each Driver is TTL or CMOS compatible and is virtually immune to latch up. Patented* design innovations eliminate cross conduction and current "shoot-through".Improved speed and drive capabilit ies are furt her enhanced by very quick & matched rise and fall times.The IXDF502 is configured wit h one Gat e Driver Invert ing plus one Gat e Driver Non-Invert ing. The IXDI502 is config-ured as a Dual Inverting Gate Driver, and the IXDN502 is configured as a Dual Non-Invert ing Gat e Driver.The IXDF502, IXDI502 and IXDN502 are each available in the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-age, and the 6-Lead DFN (D1) package, (which occupies less than 65% of the board area of the 8-Pin SOIC).*United States Patent 6,917,227Ordering InformationDS99573B(03/10)NOTE:All parts are lead-free and RoHS CompliantCopyright © 2007 IXYS CORPORATION All rights reservedIXDF502 / IXDI502 / IXDN5022 Ampere Dual Low-Side Ultrafast MOSFET Drivers2Copyright © 2007 IXYS CORPORATION All rights reservedFigure 3 - IXDN502 Dual 2A Non-Inverting Gate Driver Functional Block DiagramFigure 2 - IXDI502 Dual Inverting 2A Gate Driver Functional Block DiagramFigure 1 - IXDF502 Inverting + Non-Inverting 2A Gate Driver Functional Block Diagram* United States Patent 6,917,2273Unless otherwise noted, 4.5V ≤ V CC ≤ 30V .All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions . All specifications are for one channel.Electrical Characteristics @ T A = 25 o C (3)Symbol Parameter Test Conditions Min TypMax Units V IH High input voltage CC 3.0 V V IL Low input voltage 4.5V ≤ V CC ≤ 18V 0.8 V V IN Input voltage range-5 V CC + 0.3 V I IN Input current 0V ≤ V IN ≤ V CC -10 10 µA V OH High output voltage V CC - 0.025V V OL Low output voltage0.025 V R OH High state output resistanceV CC = 15V 2.5 4 Ω R OL Low state output resistanceV CC = 15V 2 3 Ω I PEAK Peak output current V CC = 15V 2 A I DC Continuous output current1 A t R Rise time C LOAD =1000pF V CC =15V 7.5 10 ns t F Fall timeC LOAD =1000pF V CC =15V6.5 9 ns t ONDLY On-time propagation delay C LOAD =1000pF V CC =15V 25 32 ns t OFFDLY Off-time propagation delay C LOAD =1000pF V CC =15V 20 30 ns V CC Power supply voltage4.5 15 30 V I CCPower supply currentV IN = 3.5V V IN = 0V V IN = +V CC1 03 15 15mA µA µAAbsolute Maximum Ratings (1)Operating Ratings (2)Parameter Value Supply Voltage 35VAll Ot her Pins-0.3 V to V CC + 0.3V Junct ion Temperat ure 150 °CSt orage Temperat ure-65 °C to 150 °C Lead Temperat ure (10 Sec)300 °CParameter Value Operating Supply Voltage 4.5V to 30V Operat ing Temperat ure Range -55 °C to 125 °C (4) IXYS reserves the right to change limits, test conditions, and dimensions.Package Thermal Resist ance *8-Pin P DIP (PI)θJ-A (typ)125 °C/W 8-Pin S OIC (SIA)θJ-A (t yp)200 °C/W 6-Lead DFN (D1)θJ-A (t yp)125-200 °C/W 6-Lead DFN (D1)θJ-C (max)3.3 °C/W 6-Lead DFN (D1)θJ-S (t yp)7.3 °C/W4Copyright © 2007 IXYS CORPORATION All rights reservedUnless otherwise noted, 4.5V ≤ V CC ≤ 30V , Tj < 150o CAll voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions . All specifications are for one channel.Electrical Characteristics @ temperatures over -55 o C to 125 o C (3)Symbol Parameter Test Conditions Min Typ Max Units V IH High input voltage 4.5V ≤ V CC ≤ 15V 3.1 V V IL Low input voltage 4.5V ≤ V CC ≤ 15V 0.8 V V IN Input voltage range-5 V CC + 0.3 V I IN Input current 0V ≤ V IN ≤ V CC -10 10 µA V OH High output voltage V CC - 0.025V V OL Low output voltage0.025 V R OH High state output resistanceV CC = 15V6 Ω R OL Low state output resistanceV CC = 15V 5 Ω I DC Continuous output current1 A t R Rise time C LOAD =1000pF V CC =15V 11 ns t F Fall timeC LOAD =1000pF V CC =15V 10 ns t ONDLY On-time propagation delay C LOAD =1000pF V CC =15V 40 ns t OFFDLY Off-time propagation delay C LOAD =1000pF V CC =15V 38 ns V CC Power supply voltage4.5 15 30 V I CCPower supply currentV IN = 3.5V V IN = 0V V IN = + V CC1 03 40 40mA µA µANotes:1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanentdamage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.2. The device is not intended to be operated outside of the Operating Ratings.3. Electrical Characteristics provided are associated with the stated Test Conditions.4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function.* The following notes are meant to define the conditions for the θJ-A , θJ-C and θJ-S values:1) The θJ-A (t yp) is defined as junct ion t o ambient . The θJ-A of t he st andard single die 8-Lead PDIP and 8-Lead SOIC are dominat ed by t he resist ance of t he package, and t he IXD_5XX are t ypical. The values for t hese packages are nat ural convect ion values wit h vert ical boards and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is soldered on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a lowthermal resistance to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no t hermal management .2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not published for t he PDIP and SOIC packages. The θJ-C for t he DFN packages are import ant t o show t he low t hermal resist ance from junct ion t o the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.3) The θJ-S (t yp) is defined as junct ion t o heat sink, where t he DFN package is soldered t o a t hermal subst rat e t hat is mount ed on a heat sink.The value must be t ypical because t here are a variet y of t hermal subst rat es. This value was calculat ed based on easily available IMS in t he U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialect ric wit h a t hermal conduct ivit y of 2.2W/mC was assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the DFN package.5Pin DescriptionCAUTION: Follow proper ESD procedures when handling and assembling this component.10uFAgilent 1147A Current Probe IXYS reserves the right to change limits, test conditions, and dimensions.Pin Configu ration8 Lead PDIP (PI) 8 Pin SOIC (SI) IXDN4028 Pin SOIC (SI) IXDI4028 Pin SOIC (SI) IXDF402(SIA)(SIA)(SIA)6 Lead DFN (D1) 6 Lead DFN (D1)6 Lead DFN (D1)6Copyright © 2007 IXYS CORPORATION All rights reservedFig. 6Fig. 8Fig. 10Fig. 5Fig. 7Fig. 9Rise Time vs. Supply Voltage010203040506070800510152025303540Supply Voltage (V)R i s e T i m e (n s )560pF 1000pF10000pF5400pFFall Time vs. Supply Voltage10203040506070510152025303540Supply Voltage (V)F a l l T i m e (n s )560pF1000pF 10000pF5400pFRise / Fall Time vs. Temperature V SUPPLY = 15V C LOAD = 1000pF024681012-5050100150Temperature (C)R i s e / F a l l T i m e (n s )Rise timeFall timeRise Time vs. Capacitive Load0102030405060708090100100010000Load Capacitance (pF)R i s e T i m e (n s )5V15V 10V20VFall Time vs. Capacitive Load010203040506070100100010000Load Capacitance (pF)F a l l T i m e (n s )20V15V 10V 5VInput Threshold Levels vs. Supply Voltage0.511.522.5010203040Supply Voltage (V)T h r e s h o l d L e v e l (V )P ositive goinginputNegative goinginputFig. 12Fig. 14Fig. 11Fig. 13Input Threshold Levels vs. Temperature00.511.522.53-5050100150Temperature (C)I n p u t T h r e s h o l d L e v e l (V )Positive going inputNegative going inputPropagation Delay vs. Supply VoltageRising Input, C LOAD = 1000pF5101520253035400510152025303540Supply Voltage (V)P r o p a g a t i o n D e l a y T i m e (n s )Non-InvertingInvertingPropagation Delay vs. Supply VoltageFalling Input, C LOAD = 1000pF051015202530354045510152025303540P r o p a g a t i o n D e l a y T i m e (n s )InvertingNon-InvertingPropagation Delay vs. Temperature V SUPPLY = 15V C LOAD = 1000pF510152025303540-50050100150P r o p a g a t i o n D e l a y T i m e (n s )Positve going inputNegative going input8Copyright © 2007 IXYS CORPORATION All rights reservedSupply Current vs. Capacitive LoadV SU PPLY = 15V050100150200250300100100010000Load Capacitance (pF)S u p p l y C u r r e n t (m A )100kH z1M H z2M H zSupply Current vs. Capacitive LoadV SUPPLY = 10V020406080100120140160180200100100010000Load Capacitance (pF)S u p p l y C u r r e n t (m A )100kH z1M H z2M H zSupply Current vs. Capacitive LoadV SU PPLY = 5V0102030405060708090100100100010000Load Capacitance (pF)S u p p l y C u r r e n t (m A )100kH z1M H z2M H zFig. 18Fig. 19Fig. 20Fig. 21Fig. 22Fig. 17Supply C urrent vs. FrequencyV SU PPLY = 5V0102030405060708090100100100010000Frequency (kH z)S u p p l y C u r r e n t (m A )560pF1000pF 10000pF5400pFSupply Current vs. FrequencyV SUPPLY = 10V020406080100120140160180200100100010000Frequency (kHz)S u p p l y C u r r e n t (m A )560pF1000pF 10000pF5400pFSupply Current vs. FrequencyV SU PPLY = 15V050100150200250300100100010000Frequency (kH z)S u p p l y C u r r e n t (m A )560pF1000pF 10000pF5400pF9Fig. 23Fig. 24Fig. 25Fig. 26Fig. 28Fig. 27Supply C urrent vs. C apacitive LoadV SU PPLY = 20V050100150200250300350400100100010000Load Capacitance (pF)S u p p l y C u r r e n t (m A )100kH z1M H z2M H zSupply Current vs. FrequencyV SU PPLY = 20V50100150200250300350400100100010000Frequency (kHz)S u p p l y C u r r e n t (m A )560pF1000pF10000pF5400pFOutput Source Current vs. Supply Voltage012345670510152025303540Supply Voltage (V)S o u r c e C u r r e nt (A )Output Sink Current vs. Supply Voltage-7-6-5-4-3-2-100510152025303540Supply Voltage (V)S i n k C u r r e n t (A )Output Source Current vs. TemperatureV SUPPLY = 15V 00.511.522.533.5-5050100150Temperature (C)O u t p u t S o u r c e C u r r e n t (A )Output Sink Current vs. TemperatureV SUPPLY = 15V-3.5-3-2.5-2-1.5-1-0.5-5050100150Temperature (C)O u t p u t S i n k C u r r e n t (A )10Copyright © 2007 IXYS CORPORATION All rights reservedHigh State Output Resistance vs. Supply Voltage01234565101520253035Supply Voltage (V)O u t p u t R s i s t a n c e (o h m s )Fig. 29Fig. 30Low State Output Resistance vs. Supply Voltage0.511.522.533.544.505101520253035Supply Voltage (V)O u t p u t R e s i s t a n c e (o h m s )Supply Bypassing, Grounding Practices And Output Lead inductanceWhen designing a circuit t o drive a high speed MOSFET ut ilizingt he IXD_502, it is very import ant t o observe cert ain design crit eriain order t o opt imize performance of t he driver. Part icular at t ent ion needs t o be paid t o Su pply Bypassing, Grou nding, and minimizing the Output Lead Inductance.Say, for example, we are using t he IXD_502 t o charge a 1500pF capacitive load from 0 to 25 volts in 25ns.Using the formula: I = C ∆V/∆t, where ∆V=25V C=1500pF &∆t=25ns, we can determine that to charge 1500pF to 25 volts in25ns will t ake a const ant current of 1.5A. (In realit y, t he charging current won’t be const ant, and will peak somewhere around 2A). SUPPLY BYPASSINGIn order for our design to turn the load on properly, the IXD_502 must be able to draw this 1.5A of current from the power supplyin the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnit ude larger t han t he load capacit ance. Usually, t his wouldbe achieved by placing t wo different t ypes of bypassing capacit ors, with complementary impedance curves, very close to the driverit self. (These capacit ors should be carefully select ed and should have low inductance, low resistance and high-pulse current-service rat ings). Lead lengt hs may radiat e at high frequency duet o induct ance, so care should be t aken t o keep t he lengt hs of t he leads between these bypass capacitors and the IXD_502 to an absolut e minimum.GROUNDINGIn order for the design to turn the load off properly, the IXD_502 must be able t o drain t his 1.5A of current int o an adequat e grounding syst em. There are t hree pat hs for ret urning current t hat need to be considered: Path #1 is between the IXD_502 and its load. Pat h #2 is bet ween t he IXD_502 and it s power supply. Pat h#3 is bet ween t he IXD_502 and what ever logic is driving it. All t hreeof these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made t o keep t hese t hree ground pat hs dist inct ly separate. Otherwise, the returning ground current from the load may develop a volt age t hat would have a det riment al effect on t he logic line driving t he IXD_502.OUTPUT LEAD INDUCTANCEOf equal importance to Supply Bypassing and Grounding are issues relat ed t o t he Out put Lead Induct ance. Every effort shouldbe made t o keep t he leads bet ween t he driver and it s load as short and wide as possible. If t he driver must be placed fart her t han 0.2”(5mm) from the load, then the output leads should be treated as ransmission lines. In t his case, a t wist ed-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load.11Copyright © 2007 IXYS CORPORATION All rights reserved IXYS Semiconduct or GmbHEdisonst rasse15 ; D-68623; Lampert heim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.deIXYS Corporat ion3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670e-mail: sales@12。