OX9541中文资料
XP正版序列号XP好用的正版序列号

XP正版序列号XP好⽤的正版序列号收集的XP正版序列号VOL版:DG8FV-B9TKY-FRT9J-6CRCC-XPQ4G(上海版)MRX3F-47B9T-2487J-KWKMF-RPWBY(⼯⾏版)QC986-27D34-6M3TY-JJXP9-TBGMD(⼴州版)QHYXK-JCJRX-XXY8Y-2KX2X-CCXGD(⼴州政府版)T72KM-6GWBP-GX7TD-CXFT2-7WT2B(上海版)2005年上海政府0686版谢谢⼤家的⽀持,帮我点下需要的⼴告谢谢我会更加努⼒整理我的百科服务⼤家 QC986-27D34-6M3TY-JJXP9-TBGMD(珆塆交⼤学⽣版)VMXC2-M9HKH-DRYGC-FHQ7H-BJY33(0408版)TDWGX-DMF97-BJYDQ-X9DJV-CYHWQ(不明)G6X78-XG4KV-3MXT7-FT8YM-F3YW3(不明)T8FMX-Q4HQJ-3JW77-JGPDC-FY9DG(不明)MFBF7-2CK8B-93MDB-8MR7T-4QRCQ(北京版)FCKGW-RHQQ2-YXRKT-8TG6W-2B7Q8(韩⽂版)DRXKM-94K47-38QVX-F8K7R-2H7CD(⽇⽂版)RFYPJ-BKXH2-26FWP-WB6MT-CYH2Y(英⽂版)7HPVP-8VHPV-G7CQ3-BTK2R-TDRF3(英⽂版)BCJTW-2M9JH-M8HHT-KWWWM-3444Y(英⽂版)CD87T-HFP4C-V7X7H-8VY68-W7D7M(英⽂版)OEM版:华硕:家庭版:KR63J-B34MB-CVP9K-T478G-8Y3XG联想:家庭版: PWBPT-6PGKF-TP6MY-299P4-CPXQG (XXXXX-119-0001544-XXXXX)专业版: FCDGH-QW3DJ-VBC6C-9BYTX-4GKQJ (XXXXX-119-0001553-XXXXX)VF4HT-MPWB8-TWV6R-K6QM4-W6JCMH3B8D-MQPF9-WQMFB-GV3R4-VTF7W(04年联想版)DELL:家庭版: RCBF6-6KDMK-GD6GR-K6DP3-4C8MT (XXXXX-119-0001024-XXXXX)专业版: XJM6Q-BQ8HW-T6DFB-Y934T-YD4YT (XXXXX-119-0001024-XXXXX)KG7G9-67KHV-4FQKV-4DYXK-BHQTJCOMPAQ: 家庭版: KG27H-JV9M6-2CXKV-GMP22-HF2BQ (XXXXX-119-0001015-XXXXX)专业版: KYKVX-86GQG-2MDY9-F6J9M-K42BQ (XXXXX-119-0001015-XXXXX)HP:家庭版: MK48G-CG8VJ-BRVBB-38MQ9-3PMFT (XXXXX-119-0001067-XXXXX)专业版: DMQBW-V8D4K-9BJ82-4PCJX-2WPB6 (XXXXX-119-0001067-XXXXX)P2BXT-D7Y8P-F6WF2-HYXYP-49TJDACER:家庭版: CXCY9-TTHBT-36J2P-HT3T3-QPMFB (XXXXX-119-0001006-XXXXX)专业版: BW2VG-XXDY6-VW3P7-YHQQ6-C7RYM (XXXXX-119-0001006-XXXXX)KDD3G-HGVGM-M24p4-6BMMY-9XHF8IBM:家庭版: DMY26-78CX9-Q89DP-Q8QK8-VF2B8 (XXXXX-119-0001076-XXXXX)专业版: HCBR8-FGC2K-RY7BM-HM3KT-BKVRW (XXXXX-119-0001076-XXXXX)清华同⽅:家庭版: KMHJF-9M82Y-YPFV7-YQHXH-F9JW8 (XXXXX-119-0001794-XXXXX)专业版: M68XC-TX2C9-PKK8H-GP8JH-RC8XB (XXXXX-119-0001805-XXXXX)TCL:家庭版: XPGYX-J7BF9-4YJVV-7MWK9-WQT3Y (XXXXX-119-0001607-XXXXX)七喜:家庭版: GJMY6-GMJHY-2VJ79-K67WT-KQHYT (XXXXX-119-0001661-XXXXX)Samsung:家庭版: XVX72-2WCXQ-48VWH-T66HT-C7R2B (XXXXX-119-0001085-XXXXX) TOSHIBA家庭版: WDHPC-6WQPF-W3R3K-J2VF4-JFP8W (XXXXX-119-0001114-XXXXX) SONY:专业版: K7RGC-CDXYJ-FTYH2-Y3VVV-KBYC7 (XXXXX-119-6385501-XXXXX)⽅正:家庭版:FK4VC-XP9C3-BD78M-68492-BP9BY (XXXXX-119-0002964-XXXXX)专业版:F4G2M-BH2JF-GTGJW-W82HY-VMRRQ (XXXXX-119-0002973-XXXXX)富⼠通:家庭版:JY6V8-QV6YB-BD3GX-67DC9-JT7WD (XXXXX-119-0001373-XXXXX) TOSHIBA:家庭版:WDHPC-6WQPF-W3R3K-J2VF4-JFP8W (XXXXX-119-0001114-XXXXX)惠普英⽂:KYKVX-86GQG-2MDY9-F6J9M-K42BQ(XXXXX-119-0001015-XXXXX)P2BXT-D7Y8P-F6WF2-HYXY9-49TJD序列号:6XKGD-PGHV3-D46CB-XQ8V3-V7FTJ法语专业版⼤量微软贵宾VIP序列号(1) H2HYJ-28PQM-6HGFG-CWMMD-V2C62M74XB-7K8Y4-YT6MY-B6XX4-PWBF4VVBQJ-VHP8J-7DHHP-FK68Y-YHY2VD2Q4M-M47JY-FVXFJ-JPRKR-6GG82RCB4W-27GPV-HKPF7-WH43D-V6XPDY88HJ-4K4VP-W6Y3H-BWH6M-43GCPM7D6F-3GY6B-PWXPF-JPPYD-8XD2JFWFX8-2VBWD-2K8T7-R26QW-93T3CPW2DM-BHPPK-YV8V3-VFYVY-VQFKD8W4DX-VDYKX-JYFYC-VY4Q3-YJ4PD93XDW-CQTX4-PJ2Y4-YHRW4-G4DBFD2H37-MCK77-8YW4V-7C3YQ-K98RJQ3MM2-PX8HT-DG34Y-MH7Q4-WDG3WTRHB3-TTDC6-QDTKW-8GRQY-G7H6M3VHPK-BYHDR-X63B6-8FFFM-P6TW2CB4F7-JHGCM-47K6G-PB7BY-BX2W3TMYYT-RYXXQ-BHJ78-F6TWC-97BXTYTTD2-BQHYG-8F4D2-WCVHC-64TTTGRPC7-FVKTR-MXVMJ-4TD33-JMDF8DXVWV-PDKBH-2PK6Y-YQWCP-GQ43TFWT4K-YXKYV-FTWJG-B6WJF-CB73X273M3-4KG6D-34MMY-XYFWF-2P4VYTC2PX-Y77HM-QJQ7X-BHVBT-QF9PC4MXCM-8R7Q8-V74VD-6PPWY-QQBPMF4K8K-K6XFX-K7M68-M6P4P-MVV6YWFMT2-DWMYG-JYHVK-DCXYD-7M84BBWWYK-6QF64-7KJPR-HJBJ7-JD9G9V3QXP-MBQPK-RQGB3-6XFJR-2P2BBQXYMP-G3WTH-DX3RT-VX8FR-7MDHH44V3B-JHRC3-T4PRP-C4GHK-FTT2F3TC47-R6GKX-KMM3V-37DR2-K3CGBX8CXT-B38P8-MR6CG-XGJ76-734BXMWXP3-28PMK-CQYD7-QV6VC-X7F66YTX4R-RPQJC-2FTT2-XGH23-KDPHDCJ78M-4DDKT-6CCQF-VFB7J-6HM9QGKH26-V6VWJ-3YYJY-QFF2P-PYXBHJP6M2-HJCFC-8KCJ6-M2KMW-69B9TW4DYV-RJ7VP-X78K7-7KF78-DT8JD3F276-7BYC6-WT46Q-JMR7W-KT9F6H7CJG-Y7HPQ-W3D2C-3H64M-6FVVCT3RMP-XXVR7-TGGMK-H74VG-Y3YQVPJCYY-P6TQ4-DMPY4-4WGXV-4DJRB74GFB-DDKVK-V3M28-73GYW-MTFJWDFHFT-4XQRX-4J76Q-PKPP8-72TT6G7HBY-RPXFX-JFTP2-YYVVX-8W9QD VJGX6-R7VQ8-P6GW8-J6RPK-4QCB9 KMG2X-6D8XP-M23XR-6FWKX-B8JRH CRTGH-B68P2-XB6JC-44GCD-X9JHMP6PMF-2YWVR-XTHRJ-H2RM6-3BCVD WKM33-X3KC3-GWRJ3-MF2RR-QPGW7 7H7MF-Y6H36-KQ2W3-3QWMP-MG4V9 BXGG6-3M3VH-2QV7R-M6XGV-34XMP FJPJ4-33W73-68XT3-YRYJX-JJ3P9 HFWXW-4MPRF-H7WJD-P6JQV-4X6RK W8Y84-JTWGP-PFWDQ-G4D37-DQWWK 6MH6Y-G82FC-73XR4-TMW7H-CRGC2 Y3K3R-G2R7W-WMM6G-YW2KY-TXKMD KXPM7-B64RQ-7DWJP-7DT8Y-VGK2H 22WXC-BDHBH-D6XTY-8V7FC-6YCW3 V3PB3-H6MMJ-7BDHD-P3BWJ-K9J9P BCVB6-PWK3H-GMXQB-Y84XF-JHTJ4 BTMT7-MJV82-MV4FV-2GYMB-7GWC9 FPBY6-J33HB-RDVTJ-HFPKT-4C7WY2DD2D-3Y7JY-B8P27-6XPD8-M9VQF DHWBP-RJBCX-GXDCV-7YBBQ-MW9VW 7RWJY-C4H4G-28R8J-67JKB-WBX3D DB43K-FY62D-8C8X7-KCW3M-RMX4G 7PKQG-Y244T-HJGKJ-WD6MM-86DX3 THT72-6RFVK-6R3MK-TV8H3-KJFP2P7YRP-DWGPY-G34BX-4R8MC-X4GGY QTHKF-XP37X-GGDDH-M7P8D-RBMHJ 2TBP7-VTJDW-HGVBC-M37CJ-72WBD TG47B-6QVYK-CWKKJ-FXPQY-283MG DYFK6-63K44-74QW4-D44WC-F7PDV TPC7B-MGV6W-H2GY6-YRX4Q-9PQ9G 3CWQB-8Q78J-YMVY3-DBMCW-K3HV3 WQGR2-RJWGW-2VCMV-B284Q-BGMXH 8QFJX-XVD6T-36JK8-YFJ8X-MY47RQY4F4-H7WDG-7D2BH-XJRWB-V9J28 CRMCF-6BG6R-8G7HT-MYHWV-WCHV7 VC7C8-26TCW-GPK7T-HHKG3-TWV8X FPDJW-CC3D3-VH4V6-WD8HM-GKCD3 WHFX8-8QFYV-73F6D-GRRH6-78RKM 3D4TG-RBYQP-HYGDJ-BPR6D-JXQX3 KDM48-RMWC8-Q8FRM-PDQBQ-VYCBC 2DWJ8-66CPC-CDTTK-DDVYH-B7KP2 JJRX2-32RK2-GJP3M-M427J-MBQWX QHVBK-BM8W3-7QQPQ-26H23-X4CD6 DT277-RP2QW-3G2X9-364RD-J8KTG HPJRB-W3RM3-WK4RH-KDCT4-HQTDP WKM33-X3KC3-GWRJ3-MF2RR-QPGW7 7H7MF-Y6H36-KQ2W3-3QWMP-MG4V9 RXG3Q-28G3V-MTWPV-4TPDR-MPDHF QHB43-KH2KY-6DH36-D3DFT-MDG64F8MJP-QFPDB-4YXVX-XVM64-4QP6P DRQKX-JXDFJ-K3Y8W-DGQPP-GV89H BXGG6-3M3VH-2QV7R-M6XGV-34XMP FJPJ4-33W73-68XT3-YRYJX-JJ3P9 HFWXW-4MPRF-H7WJD-P6JQV-4X6RK W8Y84-JTWGP-PFWDQ-G4D37-DQWWK FJV3W-T8QKF-BG34F-CBVT8-2D2P3 BWTHJ-6QFJ3-3PCTB-J4FC8-W4M6T24WPT-3PJ23-77HR7-3PRQH-M9GFD66PJG-TYFPY-FFK2D-P424G-78T2K YMG7X-8PH82-686XC-23T3R-FDXHW TV3F2-37DQ4-66FKR-8DQTP-X94PM6JHVK-CCQP3-VFCRH-RXHY3-RQPPT YHTCM-VY2R3-TRD3M-34PCG-GFFGH RYMMY-PMGBJ-RKDJD-X2V3Q-TWBHV H67RX-VDRDH-MCXMR-JT2JQ-B6Y3M B8FTF-YGHBH-DJPJP-BH6TM-QDFHR DRCRH-7HPH4-MPKR7-RGKR7-GFVKMGK2MH-MFXGX-KWQBT-RWK8J-QGR8G MF7CF-3XXMG-7PP4Y-PYV83-2X7D3P87VW-YQ8J6-Y4QGP-JMKQ4-Q72W2V34JQ-DM8PH-YTCV7-FB738-GPBRH MGPD7-GF6VT-83YQD-422F8-GF3TK8R4KM-JQTQM-H8WGX-8F3MV-FCBCB FT627-G4XDP-4KDG8-66B4C-KC3T3W6JR7-V2FKM-6K2YV-FYQBW-X327M WGK4X-GHKXG-FFFKY-XDXV7-84PTQ HFBMY-QXQF2-F8RVK-JBPMR-Q3G6D 233WJ-DKFJ6-XK772-KRDKX-MR3J68VMPV-6C3HM-6XDBJ-XKC63-4P9V887G2P-DPQ4F-GTBB7-PCVXW-MVDKY KQF36-BJM8P-6JPWW-6W6H8-Y46TX22DVC-GWQW7-7G228-D72Y7-QK8Q37PJCG-CXBBM-WPRP3-JC348-D8WMGF38JH-BGF8G-G7GMW-XM4T6-VK3CK GKM3J-M2FQF-7JFKT-TPB84-RBJXP DRPK6-BDCB3-G2WXG-VWJ4V-829YH8VWCB-QMTHX-FVK2R-C6YJV-6TW8G6CGHB-GPMPR-42MGV-6PKB8-FV3V4 MGB64-RPKCV-3GKBC-PH8T4-YTXQ9Q6DJY-7DKTV-KQTFX-8X7WF-DWRW6 VCTQM-VTQ8Q-Q4GQ8-H3X8M-CQWT26YHC2-WW82B-C64DR-XXPDJ-C4P7M CRMCF-6BG6R-8G7HT-MYHWV-WCHV7 TTJ8X-K7G7K-TMW4F-6FPXH-C677H JYM4H-TMPVF-QCDPQ-HFRX2-2HFDTV66VK-XWC7M-VH3KR-JY6CV-HMYPQB6DBQ-MKKVX-VBYXJ-M373C-773HTRX2K6-XQDQT-FYXWY-8XWK8-9XTYD XWGPK-JRKGF-TGWKC-3T7M4-BGCBC YF8PG-GH747-DMTC3-2797D-6WBWM VTB7G-JDRHV-JRV7K-3BX4B-3TW6TFF7BH-G3TQF-GRQFX-PPF38-MH6MX CCYFQ-CYK72-HTB3Y-MF37F-DHXQK 4876D-XRHK2-PHG2T-JVJWY-72D6VPV77H-MCP3H-VBBJD-WQF8M-XK8DW⼤量微软VIP序列号(2)QYRY6-4Y3WR-QVR86-MDJMY-4C694 VGPT2-PV626-2X6T7-D7R6Q-7GRQJWF47Q-DGPDW-FMJBY-3RWY2-K3Y6D CWWQT-VQ3RH-TPWPQ-HRJRP-9P8FV 3WFVR-J3R6R-3TFVX-Y2GC8-VMP9Q47PQQ-D2F6R-FJ3QV-RV2GH-3JQBGGK2MH-MFXGX-KWQBT-RWK8J-QGR8G MPH32-4B3G8-2MVHQ-6V4QK-4VWG974GFB-DDKVK-V3M28-73GYW-MTFJW DFHFT-4XQRX-4J76Q-PKPP8-72TT6G7HBY-RPXFX-JFTP2-YYVVX-8W9QD VJGX6-R7VQ8-P6GW8-J6RPK-4QCB9 KMG2X-6D8XP-M23XR-6FWKX-B8JRH CRTGH-B68P2-XB6JC-44GCD-X9JHMP6PMF-2YWVR-XTHRJ-H2RM6-3BCVD VJGX6-R7VQ8-P6GW8-J6RPK-4QCB98Y32G-27HKV-TGGGM-4YDKG-DGKH2 CGXJJ-DXCMJ-7CD7D-7BMJT-PCCPH8GMVK-JGX6P-T36GY-P7K2Q-GD2MPT8WT3-VHMDT-JDHP2-KKGYH-7R4467VDYJ-3HYPJ-63CBQ-Y22QH-GM2B2 7777W-HB76V-68FBQ-PTHT6-PBHCH Windows XP PRO build 2600 or XP pro 2600 evaluation:7VF4T-D7QMK-CC87K-P2468-3M4PQX3BTD-7P44K-2FWW2-3DGB8-B88DJT3GXK-WDT8Y-XMKD3-Q6MQD-DT862 VG2PR-HTKCV-TC3D8-XVTDR-D2WHD PQQRK-GFPHC-QVJC8-6MTJQ-R8DKV J84TF-7CTBW-JH3TB-YXR3W-BJBRQJ84TF-7CTBW-JH3TB-YXR3W-BJBRQ 23QFT-DVY67-6G2VV-7JM76-BWQR3 68YG6-DCFRM-B7KYT-TJRMF-CXJKX 68YG6-DCFRM-B7KYT-TJRMF-CXJKX 87H3J-HD7TM-V66FW-PBDBX-HVH4R YG4WP-9YXKX-QM2YV-PR4X7-KDJTC CHXHP-PB2FG-B68BB-H8XGF-7V2PY K74GF-Y232R-PH3RR-YKB4H-PJCV3 BRJX8-FWBHG-2RXWK-H84W7-628J4 4V2YV-HHHX4-CKVDY-4R486-498V2G87BW-MYGY7-4FWGY-CCHQB-8FJ3B 6KM4D-2Q76R-278RX-QMXJD-88D7V4JRPY-6XGY7-2MY2V-BWRX7-YCHGP WMMJQ-8TKHC-MC7TJ-7WCF2-D8BRY RJQ6X-R4C2W-FFMT7-TGXVQ-9GTVG VM3QK-HYQ8B-VHVFB-DBQWP-XW83Y GYBRP-VG8CH-JRHTV-X8C7J-6GYMB F3RJW-XFQWM-4FH6Q-3CTMR-R82GR 8J8K6-GPMBM-RWVFV-2Y8VX-B66JY8J8K6-GPMBM-RWVFV-2Y8VX-B66JY 88F24-PGH68-DTMQM-8VV47-DG7283JJQX-H6YQB-CCX7K-6WXCK-Q6BYR XBB6Y-G6QWG-WPCFQ-F8B6B-HMCPW WYTDP-6YFYF-4KFGJ-GHRYY-9KPHH 6WF3Q-TRX4M-47PRY-MFQXV-86PJG F2R8R-QJJ3V-KJKMT-64T4T-B78YT BTHFD-Y6FCP-7KMCT-7JYXH-CBPFR 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BRVCH-CK3GP-RMC68-BRT2P-GGPDK YRRCQ-QJJDX-Q8446-2HJ4M-VCX4B DYQVP-VXGWT-6WGWP-847KG-VX6CH HRJ3B-8HM6G-RHJKW-7GFKF-JV4QB KXKJD-MP3MD-VVDCY-FW4WH-PX8X4 4VXBR-RB8YJ-GYQMK-XCCWY-PVCY4 MWGM4-XJRCY-PCT2D-TWVGM-YQCXG TPPQQ-4HCRP-7X2BM-8M4WB-D67MD 87FV3-GBCTH-X4PQV-HVFPG-9GWFP HP3BF-CVPFT-2BMCF-DR7YM-GVHTF PP7FF-F7DMG-3YKVG-3YK2V-K6F2G6R6P3-TCM6Q-JKVCQ-G7QY4-7W28M KFVXF-G7F24-CK7HC-JXMYF-F4C3C2VWTK-R8T7V-C8PTF-MKY87-HGWQ7 YKC42-KC63F-YFPY4-K3YGM-B86C9 QTQCG-7YMCF-WRTJW-8GWQ2-MHPTJ 8YGWK-DHRJ6-YVC7K-MHHR3-R8PRJ KWTY7-8MXJD-KKYMR-GHCXC-VPRVT WVWP3-QH837-FD3YP-X2XFG-DXGYB QGT66-X3GVF-W764T-38K8Y-WGTF7 FWDQR-QWMFR-FT2JF-WDQRP-CF2Y3 3V8BT-73P8F-8J8YM-T2VJ8-YDTYRC646W-6FHJQ-4FBTR-GYQFG-TF8GW D3FVV-MDJJP-P83VR-88MKC-6C7QQG66TD-777MB-Y2MQJ-Y3KYB-QP7HR 333X2-VTW2X-MMKHH-DPTDF-MVVC4 KRVRR-6CQWH-Y6XGY-6YVGG-VB8GR RB2TT-XJVGR-GXXB2-D6MQC-FKKRG RFC68-HVXRD-WRXYJ-2P4QP-M4GVV JVBHH-PC7YC-H87CK-R6R6H-PKVX8 RKK4D-4H3QK-FJCFC-6XCMV-V47PF8XCHD-F6DHJ-78DG2-YHDQ2-9FT7T HH3M4-P6KWG-KW4J7-FWDTB-PCWWY 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2JJ7P-6QBDD-YDMGK-28RVB-CTBJBD68MH-8V4KG-VVCHQ-B24BV-4DP3TJ7D8H-FW3Y2-JWT2R-CW4T3-T6RYY HQJDP-PFYXK-YKWWC-RX3T4-HT7JF KFBR8-J7QGD-D343R-XM7M6-9DQ6H BQ4YX-PDV6V-K3YRD-6RJJ7-DPRHPH7H7R-C2VRC-XK87X-DMTHB-7M4PC 6GG63-PHRVQ-BG3X7-48WXT-2XVDH RFRK8-HHGMY-BBMHQ-RCQF3-2BDM2 B728J-3P7FY-TRMRV-F7FCR-QC648 VV4JV-3QF73-PCFPC-HVWFX-DVR6T DBDVQ-PDYWM-P87B3-DXC3P-PWD3H 34VTV-BGTFP-BMWDT-XV4WK-32VCH6P6W6-HB3B3-6MQ3X-Y8DJP-TT7J2P64RC-836BM-VMGMF-P3YRP-2BHQ7 RVDM7-RJP4X-3JQRT-QP86V-FDCRR BC6JY-484YM-6878W-GCM7V-CVRTR TPH4R-XFQ3K-TD26T-KPKYC-GVFC2 RQT2K-RRX8J-46HKR-W6TCG-WC34D 47HQ8-DFKXM-JQHPD-4482X-3V62G JT8R3-CQXYV-DP2MV-JQKPX-CTB7G MKY4F-4HHDQ-MYXPG-JVJ4P-FXJXX F6Q88-2V6YQ-JC8CB-82TP7-JMHJY KVQQ4-BX72V-7HPVQ-VFPJT-G4F6R R7XKD-VTGX8-CD4CP-J6DQ4-9G8WT XHGBK-6GW3M-QJPRV-Y4GKQ-K2GC7。
YE3皖南电机样本系列xxxxxxxx(新版)

YE3皖南电机样本系列xxxxxxxx(新版)YE3系列是一种超高效率三相异步电动机,适用于需要节能连续运行的一般使用场所,如风机、水泵等。
这些电动机的机座号为63至355,功率范围为0.12至375千瓦,采用工作制S1和冷却方式IC411.它们符合中国GB-2012标准的2级能效等级(IEC3级)。
这些电动机外形美观,高效节能,采用F级绝缘,防护等级为IP55,电机噪声低、振动小,运行可靠。
这些电动机有许多优点,包括美观的外观、高效节能、F 级绝缘、IP55防护等级、低噪声、小振动和平稳运行。
这些电动机的性能数据如下:型号Type 功率额定电流转速效率功率因数额定转矩千瓦)(安培)(转/分)(牛顿·米)0.53 0.63 0.80 0.81 0.630.70 0.88 0.81 0.81 0.881.0 1.29 0.82 0.81 1.291.4 1.92 0.82 0.82 1.921.72.50 0.83 0.82 2.502.43.65 0.84 0.83 3.653.24.97 0.85 0.84 4.974.6 7.30 0.87 0.85 7.306.0 9.95 0.88 0.87 9.957.8 13.1 0.88 0.88 13.110.6 17.9 0.88 0.88 17.914.4 24.4 0.89 0.89 24.420.6 35.6 0.89 0.89 35.627.9 48.6 0.90 0.89 48.634.2 60.0 0.90 0.89 60.040.5 71.2 0.91 0.89 71.254.9 96.6 0.92 0.89 96.667.4 119 0.92 0.89 11980.8 145 0.93 0.89 145这些电动机的转速、效率、功率因数和额定转矩随功率的增加而增加。
这些电动机的额定电流和额定转矩也随功率的增加而增加。
Performance Data for 380V50Hz MotorsModel Type Power kW Rated Current A Speed ___ YE3-315S-2 195 0.45 1.8 96.5 0.95 1147YE3-315M-2 234 0.64 1.8 97.2 0.95 1376YE3-315L1-2 279 0.81 1.8 97.5 0.95 1640YE3-315L-2 323 1.1 1.8 97.7 0.95 1903YE3-315L2-2 349 1.4 1.8 97.8 0.95 2059YE3-315L3-2 383 1.8 1.8 97.9 0.95 2262YE3-355M1-2 383 2.6 1.6 97.9 0.95 2262YE3-355M-2 436 3.5 1.6 98.1 0.95 2574YE3-355L1-2 488 4.8 1.6 98.2 0.95 2886YE3-355L-2 549 6.3 1.6 98.3 0.95 3249YE3-355L2-2 619 8.4 1.6 98.4 0.95 3669YE3-355L3-2 654 11.2 2.1 98.5 0.95 3872YE3-63M1-4 0.45 21.5 2.1 84.4 0.87 3.2YE3-63M2-4 0.64 28.8 2.1 86 0.87 4.5YE3-71M1-4 0.81 35.3 2.1 87.6 0.88 5.7YE3-71M2-4 1.1 41.8 2.1 88.5 0.88 7.7YE3-80M1-4 1.4 56.6 2.3 89.2 0.89 9.8YE3-80M2-4 1.8 69.6 2.3 90 0.89 12.5YE3-90S-4 2.6 84.4 2.3 91.1 0.89 18.1YE3-90L-4 3.5 103 2.3 92 0.89 24.4YE3-100L1-4 4.8 136 2.3 92.6 0.89 33.3YE3-100L2-4 6.3 163 2.3 93.1 0.89 43.6Note: The table above shows the performance data for motors with a voltage of 380V and frequency of 50Hz。
9540a 判定要求

9540a 判定要求
9540a是一个用来判定的要求,下面将详细介绍并解释它的含义。
9540a可以被拆分为两个部分,即"9540"和"a"。
其中,"9540"代表一种规定或标准,"a"则表示这个标准的一个具体要求。
根据上述要求,下面将分别解释和阐述它们。
"9540"这个标准代表着一种特定的要求或规定。
在这个文章中,我们将通过详细的解释和描述来介绍这个要求的具体内容。
该要求的内容将以文字形式展示,避免使用图片链接或公式,以确保文章符合要求。
"a"则表示"9540"标准中的一个具体要求。
在本文中,我们将对这个要求进行详细的分析和解释,以确保读者对其含义有一个清晰的理解。
同时,我们还将避免重复问题,并且不进行自我介绍,以保持文章整洁、清晰。
接下来,我们将逐个介绍这个标准的要求,确保文章内容准确且严谨。
同时,我们将尽量使用中文描述,避免歧义或错误信息的出现。
使用丰富的词汇和通顺的语句来表达要点,以确保文章易于阅读。
本文将以整洁的格式和清晰的结构来呈现。
通过使用恰当的段落和标题,使文章的结构更加清晰,易于阅读。
同时,我们将避免输出任何http地址,以确保文章符合要求。
本文将详细介绍和解释9540a这个标准的要求。
通过准确、严谨和清晰的表达,避免重复问题和自我介绍,使用中文描述,以及整洁的格式和结构,我们将确保文章内容符合要求,达到预期的效果。
1990041资料

Extract from the onlinecatalogPTSA 0,5/ 6-2,5-ZOrder No.: 1990041The figure shows a 10-position version of the producthttp://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1990041Pcb terminal, number of poles: 6, pitch: 2.5 mm, U = 160 V, I = 2 A, cross section: 0.5 mm²http://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataDimensions / positionsPitch 2.5 mmNumber of positions6Pin dimensions0,4 x 0,75Pin spacing 2.5 mmTechnical dataRated surge voltage (III/3) 2.5 kVRated surge voltage (III/2) 2.5 kVRated surge voltage (II/2) 2.5 kVRated voltage (III/2)250 VRated voltage (II/2)250 VConnection in acc. with standard EN-VDENominal current I N 2 ANominal voltage U N160 VNominal cross section0.5 mm2Maximum load current 2 AStripping length8 mmConnection dataConductor cross section solid min.0.14 mm2Conductor cross section solid max.0.5 mm2Conductor cross section stranded min.0.2 mm2Conductor cross section stranded max.0.5 mm2Conductor cross section AWG/kcmil min.24Conductor cross section AWG/kcmil max20Certificates / ApprovalsCULNominal voltage U N300 VNominal current I N 2 AAWG/kcmil26-20ULNominal voltage U N300 VNominal current I N 2 AAWG/kcmil26-20Certification CCA, CUL, UL, VDE-PZIDrawingsDrilling diagramThe illustration shows the 5-pos. version – Zig-zag pinning startsat the right-hand position. Other pinning available on request.Dimensioned drawingThe illustration shows the 5-pos. versionAddressPHOENIX CONTACT GmbH & Co. KGFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 00Fax +49 5235 3 41200http://www.phoenixcontact.de© 2008 Phoenix ContactTechnical modifications reserved;。
en 954-1国内标准

en 954-1国内标准EN 954-1 国内标准EN 954-1,即“机械安全-安全相关控制系统的组成—第1部分:一般原则和定义”,是欧洲标准化委员会(CEN)制定的国际标准。
该标准主要涉及机械设备的安全相关控制系统的要求和定义。
在本文中,我们将介绍EN 954-1国内标准的主要内容和应用。
1. 背景与概述EN 954-1标准是针对机械设备的安全性进行评估和控制的重要标准之一。
它对于确保机械设备在正常运行过程中的安全性具有重要意义。
该标准基于风险评估和安全控制的原则,旨在帮助设计师和制造商识别和减少机械设备可能导致的伤害风险。
2. 标准内容EN 954-1标准主要包含以下几个方面的内容:2.1 定义和术语标准对于机械设备和相关控制系统中的一些定义和术语进行了详细解释和界定。
这些定义和术语的准确理解对于正确应用标准起着重要的指导作用。
2.2 安全相关控制系统的设计原则EN 954-1标准提出了安全相关控制系统的设计原则,旨在确保机械设备在整个使用寿命内的安全性。
这些原则包括但不限于:规定的安全功能、失效的概率、安全元件的选择、可靠度等。
2.3 安全相关控制系统的结构分类标准将安全相关控制系统根据结构和功能进行了分类,旨在提供设计师和制造商合理选用适当等级安全相关控制系统的依据。
2.4 性能级别(Performance Level)EN 954-1标准引入了性能级别的概念,用于评估和选择机械设备的安全相关控制系统。
性能级别是根据安全性能的可靠性、可达性、持久性等指标进行确定的,旨在帮助设计师和制造商选择和应用适当的安全相关控制系统。
2.5 评估和验证标准要求设计师和制造商通过评估和验证来验证机械设备安全相关控制系统的有效性。
评估和验证的方法和过程应该符合相关的标准和规范,并通过可信的评估机构进行认证。
3. 应用和意义EN 954-1标准的应用范围非常广泛,几乎涵盖了所有的机械设备和相关控制系统。
它对于确保机械设备的安全性能、降低人员伤害风险以及提高工作效率都起到了重要的作用。
OXuPCI954_DS

External—Free ReleaseOxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210 © Oxford Semiconductor, Inc. 2007F EATURES• Four 16C950 High performance UART channels • 8-bit Pass-through Local Bus (PCI Bridge )• IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver)• Efficient 32-bit, 33 MHz, multi-function target-only PCIcontroller, fully compliant to PCI Local Bus Specification 3.0 and PCI Power Management Specification 1.1 • Software compatible with OXmPCI954• UARTs fully software compatible with 16C550-type devices • UART operation up to 60 MHz via external clock source. Up to 20 MHz with the crystal oscillator• Baud rates up to 60 Mbps in external 1x clock mode and 15 Mbps in asynchronous mode• 128-byte deep FIFO per transmitter and receiver • Flexible clock prescaler, from 1 to 31.875• Automated in-band flow control using programmable Xon/Xoff in both directions•Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#• Programmable RS485 turnaround delay• Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control• Infra-red (IrDA) receiver and transmitter operation • 9-bit data framing, as well as 5, 6, 7, and 8 bits • Detection of bad data in the receiver FIFO• Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers.• Local registers to provide status/control of device functions • 11 multi-purpose I/O pins, which can be configured as input interrupt pins or ‘wake-up’• Auto-detection of a wide range of optional MICROWIRE TM compatible EEPROMs, to re-configure device parameters • Function access , to pre-configure each function prior to handover to generic device drivers • Operation via I/O or memory mapping• 3.3 V or 5 V operation (PCI Universal Voltage)• Extended operating temperature range: -40° C to 85° C •176-pin LQFP packageD ESCRIPTIONThe OXuPCI954 is a single chip solution for PCI-based serial and parallel expansion add-in cards. It is a dual function PCI device, where function 0 offers four ultra-high performance OX16C950 UARTs, and function 1 is configurable either as an 8-bit local bus or a bi-directional parallel port.Each UART channel in the OXuPCI954 is the fastest available PC-compatible UART, offering data rates up to 15 Mbps and 128-byte deep transmitter and receiver FIFOs. The deep FIFOs reduce CPU overhead and allow utilization of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices (and compatibles), as well as the OX16C95x family of high performance UARTs. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features including automated in-band flow control, readable FIFO levels, etc.To enhance device driver efficiency and reduce interrupt latency, internal UARTs have multi-port features such as shadowed FIFO fill levels, a global interrupt source register and Good-Data Status, readable in four adjacent DWORD registers visible to logical functions in I/O space and memory space.Expansion of serial ports beyond four channels is possible using the 8-bit pass-through Local Bus function. This provides a general address/data bus and interrupt capability to a discrete UART part, such as the Oxford SemiconductorOX16C954. Other controllers could be used to provide capabilities beyond additional UART ports. The addressable space provided by the Local Bus can be increased up to 256 bytes, and divided into four chip-select regions. This flexible expansion scheme caters for cards with up to 20 serial ports using external 16C950, 16C954 or compatible devices, or composite applications such as combined serial and parallel port expansion cards. Serial port cards with up to 20 ports (or with 4 serial ports and a parallel port) can be designed without redefining any device or timing parameters.The parallel port is an IEEE 1284 compliant SPP/EPP/ECP parallel port that fully supports the existing Centronics interface. The parallel port can be enabled in place of the local bus. A n external bus transceiver is required for 5V parallel port operation if device is 3.3V sourced.For full flexibility, all the default configuration register values can be overwritten using an optional M ICROWIRE compatibleserial EEPROM. This EEPROM can also be used to provide function access to pre-configure devices on the local bus/parallel port, prior to any PCI configuration accesses and before control is handed to (generic) device drivers.The OXuPCI954 can be used to replace the OXmPCI954 in a PCI application where quad UARTs and a local bus/parallel port functionality are required.OXuPCI954 DATA SHEETIntegrated High Performance Quad UARTs,8-bit Local Bus/Parallel Port,3.3 V and 5 V (Universal Voltage) PCI Interface .Improvements of the OXuPCI954 over Discrete SolutionsHigher degree of integrationThe OXuPCI954 device offers four internal 16C950 high-performance UARTs and an 8-bit local bus or abi-directional parallel port.Multi-function deviceThe OXuPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the local bus or drivers for the internal parallel port.Quad Internal OX16C950 UARTsThe OXuPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter and receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60 Mbps.Improved access timingAccess to the internal UARTs require zero or one PCI wait state. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latencyThe OXuPCI954 device offers shadowed FIFO levels and Interrupt status registers on the internal UARTs and the MIO pins. This reduces the device driver interrupt latency. Power managementThe OXuPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input.Optional EEPROMThe OXuPCI954 device can be reconfigured from an external EEPROM to the end-user’s requirements. However, this is not required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the EEPROM controller prevents the PCI system from ‘hanging’ due to an incorrectly programmed EEPROM.R EVISION H ISTORYRevision Modification May 2007 First publication.Sep 2007 Feature revision, including removal of D3coldT ABLE OF C ONTENTS1OXuPCI954 Device Modes (6)2Block Diagram (7)3Pin Information—176-Pin LQFP (8)3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus (8)3.1.1Mode ‘1’ : Quad UARTs + Parallel Port (9)3.2Pin Descriptions (10)4Configuration and Operation (16)5PCI Target Controller (17)5.1Operation (17)5.2Configuration Space (17)5.2.1PCI Configuration Space Register Map (18)5.3Accessing Logical Functions (20)5.3.1PCI Access to Internal UARTs (21)5.3.2PCI Access to 8-bit Local Bus (22)5.3.3PCI Access to Parallel Port (22)5.4Accessing Local Configuration Registers (23)5.4.1Local Configuration and Control Register ‘LCC’ (Offset 0x00) (23)5.4.2Multi-purpose I/O Configuration Register ‘MIC’ (Offset 0x04) (24)5.4.3Local Bus Timing Parameter Register 1 ‘LT1’ (Offset 0x08) (26)5.4.4Local Bus Timing Parameter Register 2 ‘LT2’ (Offset 0x0C) (27)5.4.5UART Receiver FIFO Levels ‘URL’ (Offset 0x10) (28)5.4.6UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14) (29)5.4.7UART Interrupt Source Register ‘UIS’ (Offset 0x18) (29)5.4.8Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C) (30)5.5PCI Interrupts (31)5.6Power Management (32)5.6.1Power Management of Function 0 (32)5.6.2Power Management of Function 1 (33)5.6.3Universal Voltage (34)5.7Unique Bar Option – for Function 0 (35)6Internal OX16C950 UARTs (36)6.1Operation – Mode Selection (36)6.1.1450 Mode (36)6.1.2550 Mode (36)6.1.3Extended 550 Mode (36)6.1.4750 Mode (36)6.1.5650 Mode (36)6.1.6950 Mode (37)6.2Register Description Tables (38)6.3UART Reset Configuration (41)6.3.1Hardware Reset (41)6.3.2Software Reset (41)6.4Transmitter and Receiver FIFOs (42)6.4.1FIFO Control Register ‘FCR’ (42)6.5Line Control and Status (43)6.5.1False Start Bit Detection (43)6.5.2Line Control Register ‘LCR’ (43)6.5.3Line Status Register ‘LSR’ (44)6.6Interrupts and Sleep Mode (45)6.6.1Interrupt Enable Register ‘IER’ (45)6.6.2Interrupt Status Register ‘ISR’ (46)6.6.3Interrupt Description (46)6.6.4Sleep Mode (47)6.7Modem Interface (47)6.7.1Modem Control Register ‘MCR’ (47)6.7.2Modem Status Register ‘MSR’ (48)6.8Other Standard Registers (48)6.8.1Divisor Latch Registers ‘DLL and DLM’ (48)6.8.2Scratch Pad Register ‘SPR’ (48)6.9Automatic Flow Control (49)6.9.1Enhanced Features Register ‘EFR’ (49)6.9.2Special Character Detection (50)6.9.3Automatic In-band Flow Control (50)6.9.4Automatic Out-of-band Flow Control (50)6.10Baud Rate Generation (51)6.10.1General Operation (51)6.10.2Clock Prescaler Register ‘CPR’ (51)6.10.3Times Clock Register ‘TCR’ (51)6.10.4External 1x Clock Mode (53)6.10.5Crystal Oscillator Circuit (53)6.11Additional Features (54)6.11.1Additional Status Register ‘ASR’ (54)6.11.2FIFO Fill Levels ‘TFL and RFL’ (54)6.11.3Additional Control Register ‘ACR’ (54)6.11.4Transmitter Trigger Level ‘TTL’ (55)6.11.5Receiver Interrupt. Trigger Level ‘RTL’ (55)6.11.6Flow Control Levels ‘FCL’ and ‘FCH’ (56)6.11.7Device Identification Registers (56)6.11.8Clock Select Register ‘CKS’ (56)6.11.9Nine-bit Mode Register ‘NMR’ (57)6.11.10Modem Disable Mask ‘MDM’ (57)6.11.11Readable FCR ‘RFC’ (58)6.11.12Good-data Status Register ‘GDS’ (58)6.11.13Port Index Register ‘PIX’ (58)6.11.14Clock Alteration Register ‘CKA’ (58)6.11.15RS485 Delay Enable ‘RS485_DLYEN’ (58)6.11.16RS485 Delay Count ‘RS485_DLYCNT’ (59)7Local bus (60)7.1Overview (60)7.2Operation (60)7.3Configuration and Programming (61)8Bidirectional Parallel Port (62)8.1Operation and Mode Selection (62)8.1.1SPP Mode (62)8.1.2PS2 Mode (62)8.1.3EPP Mode (62)8.1.4ECP Mode (62)8.2Parallel Port Interrupt (63)8.3Register Description (63)8.3.1Parallel Port Data Register ‘PDR’ (64)8.3.2ECP FIFO Address / RLE (64)8.3.3Device Status Register ‘DSR’ (64)8.3.4Device Control Register ‘DCR’ (64)8.3.5EPP Address register ‘EPPA’ (65)8.3.6EPP Data Registers ‘EPPD1-4’ (65)8.3.7ECP Data FIFO (65)8.3.8Test FIFO (65)8.3.9Configuration A Register (65)8.3.10Configuration B Register (65)8.3.11Extended Control Register ‘ECR’ (65)9Serial EEPROM (66)9.1Specification (66)9.1.1Zone 0: Header (67)9.1.2Zone 1: Local Configuration Registers (68)9.1.3Zone 2: Identification Registers (69)9.1.4Zone 3: PCI Configuration Registers (69)9.1.5Zone 4: Power Management DATA (and DATA_SCALE Zone) (70)9.1.6Zone 5: Function Access (70)10Operating Conditions (72)10.1DC Electrical Characteristics (72)11AC Electrical Characteristics (76)11.1PCI Bus Timings (76)11.2Local Bus (77)11.3Serial Ports (79)12Timing Waveforms (80)13Package Information (95)13.1176-Pin LQFP (95)14Ordering Information (96)1OX U PCI954D EVICE M ODESThe OXuPCI954 supports two modes of operation. These modes are summarized in the following table.Device Mode Mode Pin Selection Functionality0 MODE = 0 Function 0 : Quad UARTs Function 1 : 8-bit local bus1 MODE = 1 Function 0 : Quad UARTs Function 1 : Parallel Port* The OXuPCI954 is not pin-compatible with the OX16PCI954 or the OXmPCI954, but is the same in all other aspects.2B LOCK D IAGRAMFIFOSELMODEAD[31:0]C/BE[3:0]#PCI_CLKFRAME#DEVSEL#IRDY#TRDY#STOP#PARPERR#IDSELRST#INTA#PME#XTLIXTLOUART_Clk_Out Local_Bus ClkEE_DIEE_CSEE_CKEE_DOSOUT[3:0]SIN[3:0]RTS[3:0]DTR[3:0]CTS[3:0]DSR[3:0]DCD[3:0]RI[3:0]MIO[10:0]PD[7:0]ACK#PEBUSYSLCTERR#SLIN#INIT#AFD#STB#LBA[7:0]LBD[7:0]LBCS[3:0]LBWR#LBRD#LBRSTDATA_DIR OXuPCI954 Block DiagramOSCDIS XTLSEL3P IN I NFORMATION—176-P IN LQFP 3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus7 NC. Do not connect these pins:23, 40, 41, 136, 137, 138, 1393.1.1Mode ‘1’ : Quad UARTs + Parallel Port15 NC. Do not connect these pins:23, 40, 41, 74, 112, 113, 114, 115, 116, 117, 124, 136, 137, 138, 1393.2Pin DescriptionsFor the actual pinouts of the OXuPCI954 device (for the various modes), refer to the Section 3, Pin Information. The I/O direction key table is on page 15.PCI Interface – All ModesPin Dir1Name Description149, 150, 151, 154, 155,157, 158, 160, 164, 165,167, 168, 169, 170, 171,174, 13, 14, 15, 17, 18, 20,24, 25, 27, 28, 31, 32, 33,34, 35, 39P_I/O AD[31:0] Multiplexed PCI Address/Data bus161, 175, 12, 26 P_I C/BE[3:0]# PCI Command/Byte enable146 P_I CLK PCI system clock (33MHz)176 P_IFRAME#CycleFrame5 P_ODEVSEL#DeviceSelect1 P_IIRDY#Initiatorready2 P_OTRDY#Targetready6 P_O STOP# Target Stop request10 P_I/OPAR Parity8 P_OSERR#Systemerror7 P_I/OPERR#Parityerror163 P_I IDSEL Initialization device select144 P_I RST# PCI system reset142 P_ODINTA# PCIinterrupt147 P_OD PME# Power management eventSerial Port Pins – All ModesPin Dir1Name Description50 I FIFOSEL FIFO select. For backward compatibility with 16C550,16C650 and 16C750 devices the UARTs’ FIFO depth is 16when FIFOSEL is low. The FIFO size is increased to 128when FIFOSEL is high. The unlatched state of this pin isreadable by software. The FIFO size may also be set to 128by setting FCR[5] when LCR[7] is set, or by putting thedevice into Enhanced mode.82, 81, 63, 62 O(h)SOUT[3:0]IrDA_Out[3:0] These four pins are present in all modes but they can serve one of two functions, as follows:UART serial data outputs.UART IrDA data output when MCR[6] of the corresponding channel is set in Enhanced mode.91, 73, 72, 55I(h) I(h) SIN[3:0]IrDA_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:UART serial data inputs.UART IrDA data input when IrDA mode is enabled (seeabove).Serial Port Pins – All ModesPin Dir1Name Description89, 76, 71, 57 I(h) DCD[3:0]# Active-low modem data-carrier-detect input 84, 79, 65, 60O(h) O(h) O(h) DTR[3:0]#485_En[3:0]Tx_Clk_Out[3:0]These four pins are present in all modes but they can serveone of three functions, as follows:Active-low modem data-terminal-ready output. If automatedDTR# flow control is enabled, the DTR# pin is asserted anddeasserted if the receiver FIFO reaches or falls below theprogrammed thresholds, respectively.In RS485 half-duplex mode, the DTR# pin may beprogrammed to reflect the state of the transmitter empty bitto automatically control the direction of the RS485transceiver buffer (see register ACR[4:3]).Transmitter 1x clock (baud rate generator output). Forisochronous applications, the 1x (or Nx) transmitter clockmay be asserted on the DTR# pins (see register CKS[5:4]).83, 80, 64, 61 O(h) RTS[3:0]# Active-low modem request-to-send output. If automatedRTS# flow control is enabled, the RTS# pin is deassertedand reasserted whenever the receiver FIFO reaches or fallsbelow the programmed thresholds, respectively.85, 78, 67, 59 I(h) CTS[3:0]# Active-low modem clear-to-send input. If automated CTS#flow control is enabled, upon deassertion of the CTS# pin,the transmitter will complete the current character and enterthe idle mode until the CTS# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the CTS# pin.86, 77, 66, 58I(h) I(h) DSR[3:0]#Rx_Clk_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:Active-low modem data-set-ready input. If automated DSR#flow control is enabled, upon deassertion of the DSR# pin,the transmitter will complete the current character and enterthe idle mode until the DSR# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the DSR# pin.External receiver clock for isochronous applications. TheRx_Clk_In is selected when CKS[1:0] = ‘01’.90, 75, 70, 56 I(h)I(h) RI[3:0]#Tx_Clk_In[3:0]Active-low modem Ring-Indicator inputExternal transmitter clock. This clock can be used by thetransmitter (and indirectly by the receiver) when CKS[6]=’1’.Clock Interface Pins – All ModesPin Dir 1 Name Description49 I/OXTLOCrystal oscillator output when OSCDIS = ‘0’.External clock source input when OSCDIS = ‘1’48 I XTLI Crystal oscillator input when OSCDIS = ‘0’, up to 20MHz.N/C when OSCDIS = ‘1’45 I OSCDIS Oscillator disable.When 0, the internal crystal oscillator is enabled and a crystal needs to be attached to XTLI/XTLO.XTLSEL must be set according to the crystal frequency that is used (up to 20Mhz).When 1, the internal crystal oscillator is disabled and an external oscillator source (up to 60MHz) can be input to XTLO. XTLI is N/C and XTLSEL must be 0130 I XTLSEL Defines the frequency of the crystal attached to XTLI/XTLO(when OSCDIS = ‘0’)0 = 1 MHz – 12 MHz 1 = 12 MHz – 20 MHz8-bit Local Bus – Mode 0Pin Dir 1 Name Description 111O UART_CLK_Out Buffered crystal output. This clock can drive external UARTsconnected to the local bus. Can be enabled / disabled by software.123 O(h) LBRST Local bus active-high reset. 124 O LBRST# Local bus active-low reset. 104 O LBDOUT Local bus data out enable. This pin can be used by externaltransceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode.74 O LBCLK Buffered PCI clock. Can be enabled / disabled by software. 114, 115, 116, 117 O(h) O(h) LBCS[3:0]# LBDS[3:0]# Local bus active-low Chip-Select (Intel mode).Local bus active-low Data-Strobe (Motorola mode).112 O O LBWR# LBRDWR# Local bus active-low write-strobe (Intel mode).Local bus Read-not-Write control (Motorola mode).113 O Z LBRD# Hi-Z Local bus active-low read-strobe (Intel mode).Permanent high impedance (Motorola mode).105, 106, 108, 109 118, 119, 120, 122 O(h) LBA[7:0] Local bus address signals. 96, 97, 98, 99 100, 101, 102, 103I/O(h) LBD[7:0] Local bus data signals.Parallel Port – Mode 1Pin Dir 1 NameDescription123 I(h) I(h) ACK#INTR#Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place.Identical function to ACK# (EPP mode).122 I(h) PEPaper Empty. Activated by printer when it runs out of paper. 120 I(h) I(h) BUSYWAIT#Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data.Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles.109 OD(h) O(h) SLIN#ADDRSTB#Select (SPP mode). Asserted by host to select the peripheral.Address strobe (EPP mode) provides address read and write strobe.119 I(h) SLCT Peripheral selected. Asserted by peripheral when selected. 118 I(h) ERR#Error. Held low by the peripheral during an error condition. 108 OD(h) O(h) INIT#INIT#Initialize (SPP mode). Commands the peripheral to initialize.Initialize (EPP mode). Identical function to SPP mode. 106 OD(h) O(h) AFD#DATASTB# Auto Feed (SPP mode, open-drain).Data strobe (EPP mode) provides data read and write strobe.105 OD(h) O(h) STB#WRITE#Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0].Write (EPP mode). Indicates a write cycle when low and a read cycle when high . 96, 97, 98, 99, 100, 101, 102, 103I/O(h) PD[7:0] Parallel data bus.104OPDOUTParallel port data out enable. This pin should be used by external transceivers for 5 V signaling; it is high when PD[7:0] are in output mode and low when they are in input mode.Multi-purpose and External Interrupt Pins – All ModesPin Dir1Name DescriptionMODE0 1135 --135I/O(h)OMIO0NCMulti-purpose I/O 0. Can drive high or low, or assert a PCIinterrupt.Output Driving ‘0’. Can be left as a No-connect.134 134 134134I/O(h)MIO1NCMulti-purpose I/O 1. Can drive high or low, or assert a PCIinterrupt (as long as LCC[6:5] = “00”).Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)Can be left as a No-Connect.133 133 133133I/O(h)IMIO2PME_InMulti-purpose I/O 2. When LCC[7] = 0, this pin can drive highor low, or assert a PCI interrupt.Input power management event. When LCC[7] is set thisinput pin can assert a function 1 PME#.93, 94, 95, 125, 126, 127, 128, 132 I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCIinterrupt.EEPROM Pins – All ModesPin Dir1Name Description53 OEE_CKEEPROMclock.52 O EE_CS EEPROM active-high Chip Select.54 IU(h) EE_DI EEPROM data in, with internal pull-up.When the serial EEPROM is connected, this pin should bepulled up using a 1-10k resistor. When the EEPROM is notused the internal pull-up is sufficient.Pin to be connected to the external EEPROM’s EE_DO pin(if used).51 O EE_DO EEPROM data out.Pin to be connected to the external EEPROM’s EE_DI pin(if used).Table 1: Pin DescriptionsI/O Direction Key P_I PCI input 3.3 V Only P_O PCI output / PCITristates 3.3 V Only P_I/O PCI bi-directional 3.3 V Only P_OD PCI open drain 3.3 V OnlyI Input LVTTL level I(h) Input LVTTL level, 5 V tolerant IU(h) Input with internal pull-up LVTTL level, 5 V tolerant I/O(h) Bi-Directional LVTTL level, 5 V tolerantO Output Standard Output O(h) Output 5 V tolerant (High Voltage BI-Direct in output mode) OD Open drain Standard Open-drain Output OD(h) Open drain 5 V tolerant (High Voltage BI-Direct in open-drain mode) NC No connectG Ground V VoltageMiscellaneous PinsPin Dir 1 NameDescription44 IMODEMode selector Pin0 : Function 0 : Quad UART. Function 1 : 8-bit local bus.1 : Function 0 : Quad UART. Function 1 : Parallel port.Power and GroundPinType Name Description19, 42, 47, 69, 88, 107, 131, 148VVDDPower Supply (3.3 V)11, 22, 36, 140, 156, 162, 173 V VIOPCI I/O Universal VoltageDefines the (clamping) voltage of the PCI I/O Buffers.To be connected to the VIO pin of the PCI connector. 3, 4, 9, 16, 21, 29, 30, 37, 38, 43, 46, 68, 87, 92, 110, 121, 129, 141, 143, 145, 152, 153, 159, 166, 172G GNDPower Supply Ground (0 V)4C ONFIGURATION AND O PERATIONThe OXuPCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 3.0 and the PCI Power Management Specification, Revision 1.1.The OXuPCI954 affords maximum configuration flexibility by treating the internal UARTs, the local bus and the parallel port as separate logical functions. Each function has its own configuration space and is therefore recognized and configured by the PCI BIOS separately. The functions used are configured by the Mode Selection Pin as shown in Section 1 OXuPCI954 Device Modes.The OXuPCI954 is configured by system start-up software during the bootstrap process that follows bus reset. The system scans the bus and reads the vendor and device identification codes from any devices it finds. It then loads device-driver software according to this information and configures the I/O, memory and interrupt resources. Device drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by PCI.Each function operates as though it was a separate device. However there are a set of Local Configuration Registers that can be used to enable signals and interrupts, configure timings, and improve the efficiency of multi-port drivers. This architecture enables separate drivers to be installed for each function. Generic port drivers can be hooked to use the functions individually, or more efficient multi-port drivers can hook both functions, accessing the Local Configuration Registers from either.All registers default after reset to suitable values for typical applications such a 4/8 port serial, or combo 4-port serial/1-port parallel add-in cards. However, all identification, control and timing registers can be redefined using an optional serial EEPROM.5PCI T ARGET C ONTROLLER5.1OperationThe OXuPCI954 responds to the following PCI transactions:-•Configuration access: The OXuPCI954 responds to type 0 configuration reads and writes if the IDSELsignal is asserted and the bus address is selecting theconfiguration registers for function 0 or 1. The devicewill respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Anyother configuration transaction will be ignored by theOXuPCI954.•I/O reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers(BARs). If the address falls within one of the assignedranges, the device will respond to the I/O transactionby asserting DEVSEL#. Data transfer follows thisaddress phase. For the UARTs and 8-bit local buscontroller, only byte accesses are possible. For I/Oaccesses to these regions, the controller comparesAD[1:0] with the byte-enable signals as defined in thePCI specification. The access is always completed;however if the correct BE signal is not present thetransaction will have no effect.•Memory reads/writes: These are treated in the same way as I/O transactions, except that the memoryranges are used. Memory access to single-byte regions is always expanded to DWORDs in theOXuPCI954. In other words, OXuPCI954 reserves aDWORD per byte in single-byte regions. The deviceallows the user to define the active byte lane usingLCC[4:3] so that in Big-Endian systems the hardwarecan swap the byte lane automatically. For Memorymapped access in single-byte regions, the OXuPCI954 compares the asserted byte-enable withthe selected byte-lane in LCC[4:3] and completes theoperation if a match occurs, otherwise the access willcomplete normally on the PCI bus, but it will have noeffect on either the internal UARTs or the local buscontroller.•All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored.The OXuPCI954 will complete all transactions as disconnect-with-data, i.e. the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signaled in response to any access while the OXuPCI954 is reading from the serial EEPROM.The OXuPCI954 performs medium-speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OXuPCI954 as a target, so a bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required.The device supports any combination of byte-enables to the PCI Configuration Registers and the Local Configuration Registers. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read.The OXuPCI954 performs parity generation and checking on all PCI bus transactions as defined by the standard. Note this is entirely unrelated to serial data parity which is handled within the UART functional modules themselves. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct.The OXuPCI954 does not support any kind of caching or data buffering in addition to that already provided within the UARTs by the transmit and receive data FIFOs. In general, registers in the UARTs and on the local bus can not be pre-fetched because there may be side-effects on read.5.2Configuration SpaceThe OXuPCI954 is a dual-function device, where each logical function has its own configuration space. All required fields in the standard header are implemented, plus the Power Management Extended Capability register set. The format of the configuration space is shown in the following tables.In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0.。
XP95-PD中文资料

GAMEWELL-FCI12 Clintonville Road, Northford, CT 06472-1610 USA • Tel: (203) 484-7161 • Fax: (203) 484-7118Specifications are for information only, are not intended for installation purposes, and are subject to change without notice. No responsibility is assumed by Gamewell-FCI for their use.©2007 by Honeywell International Inc. All rights reserved. CS-2049 Rev. a1 page 1 of 2XP95-PD/-PDR,XP95-ID/-IDRAnalog Addressable DuctSmoke DetectorsDescriptionThe Gamewell-FCI analog addressable duct smoke detec-tors provide early detection of smoke and products with combustion present in air moving through an HVAC duct.Fans, blowers and complete systems may be shut down or activated in fire alarm mode by the Fire Alarm Control Panel (FACP) in the event of smoke detection.The Gamewell-FCI analog addressable duct smoke detec-tors may utilize either interchangeable photoelectric or ion-ization sensor heads. The external alarm indication is a light-emitting diode (LED), easily visible through the hous-ing. A manual reset switch is provided on the front of the sensor.Duct smoke detectors are also available with auxiliary relay contacts. The relay requires two additional wires for power and will activate when the sensor reaches alarm levels. All wiring must comply with local codes and regulations.XP95 Duct Smoke Detectors digitally transmit their address and the chamber’s analog value to the FACP for analysis.Air sampling is accomplished by two tubes which protrude into the duct. An exhaust tube of one standard length 7.5"(19.05 cm ) is provided with the sensor housing. Intake sam-pling tubes, which must be ordered separately, are supplied in three standard lengths: 2.5, 5, or 10 feet (0.762, 1.524, or 3.048 m).InstallationDuct mounting is accomplished by the use of a template and four sheet metal screws, provided. The duct detectors are compatible with the analog loops on Gamewell-FCI’s 600 Series Analog Addressable Control Panels.ProgrammingThe only programming required for the XP95 Duct Smoke Sensors is address setting. This is accomplished through the use of the XPert addressing card which is inserted into the sensor base.Features•Compatible with the Gamewell-FCI 600 Series analog addressable control panels•Interchangeable “Plug-in” photoelectric or ionization heads•Address is stored in the sensor base •Address is set by XPert addressing card •Remote alarm LED option•Two-wire supply- polarity insensitive •Very low standby current•LED alarm indication on sensor head•Rugged steel backbox with clear plastic cover •Large terminal connection screws•No additional screens or filters to clean or replace •Relay version available with optional remote test unit •Three standard tube lengths available: 2.5, 5, or 10 ft. (0.762, 1.524, or 3.048 m)C S -2049p h 1.w m fXP95 Series3242-1004:103 (photo)3242-1004:102 (ion)SIGNALING268AGAMEWELL-FCI12 Clintonville Road, Northford, CT 06472-1610 USA • Tel: (203) 484-7161 • Fax: (203) 484-7118CS-2049 Rev. a1 page 2 of Programming (Continued)When the sensor head is inserted into the base, the address is automatically relayed to the sensor. Changing the sensor does not require additional programming since the address remains on the XPert card located in the base.All other sensor-specific programming is accomplished at the FACP .Engineer’s SpecificationsThe contractor shall furnish and install, where indicated on the plans, analog addressable air duct smoke detectors.The sensors shall be listed by Underwriter’s Laboratories per UL 268A and UL-Listed as compatible with the Fire Alarm Control Panel (FACP). The sensors shall operate at air velocities from 300 to 4,000 feet (91.44 to 1219.20 m) per minute. The smoke sensor shall contain an integral LED that shall latch in when the unit goes into alarm, mounted at a 30° slant to provide a wide viewing angle.A manual reset/test switch shall be located on the front of the device. The housing shall contain a sensor base which will accept photoelectric or ionization heads. All wiring must comply with local codes and regulations. The duct sensor housing shall have a metal chassis with a clear plastic cover and complete mechanical installation may be per-formed without removal of the cover. The duct smoke detector shall be the Gamewell-FCI model, XP95-ID(R) or XP95-PD(R) analog addressable duct smoke detector.SpecificationsAmbient Temperature:32° F to 120°F (0°C to 49°C)Humidity:10% to 85% R.H Material:18 gauge steel backbox,clear plastic coverDimensions:10.0" H x 8.25" W x 2.25" D(25.4 H x 21.0 W x 5.7 D cm)Maximum Net Weight: 4.0 lbs. (1.814 kg)Mounting:Template and necessaryhardware suppliedRadioactive Element:For Ionization versions only:Americium 241 (0.9 microcuries)Sensitivity:Factory set (ion); or adjustablevia the IF600 control panel (photoelectric)Air Velocity:300 to 4,000 feet per minute.Pressure Differential:0.01 to 1.2 inches (1.524 to 20.320meters per second) of waterStandby Current:Photoelectric: 340 µAIonization: 280 µAAlarm LED Current:Photoelectric: 4 mAIonization: 2 mARemote Alarm OutputRange:20 mA maximum; diode gated Specifications (Continued)Relay Versions Only:Relay Contacts:Two dry Form-C contacts Relay Contact Ratings:10 A @ 24 VDC resistivemaximumOperating Voltage:24 VDC Current:Standby current:0.010 A @ 24 VDC Alarm current:0.055 A @ 24 VDCOrdering InformationModel DescriptionXP95-IDTwo-wire air duct, ionization smoke detector 24 VDC (RW-AAN)XP95-PD Two-wire air duct, photoelectric smokedetector 24 VDC (RW-AAP)30203-01Remote LED alarm indicator (two VDCs);used with XP95-PD and XP95-IDXP95-IDR Four-wire air duct, ionization smoke detector24 VDC with relay (RW-ARN)XP95-PDR Four-wire air duct, photoelectric smokedetector 24 VDC with relay (RW-ARP)30203Remote LED alarm indicator (24 VDCs);used with relay versions30007-02Remote test station with alarm LED;used with relay versions70896-02Sampling tube, 2.5 feet (0.762 m)70896-05Sampling tube, 5 feet (1.524 m)70896-10Sampling tube, 10 feet (3.048 m)XP95-I Ionization sensor head (replacement)XP95-P Photoelectric sensor head (replacement)72247Duct detector enclosure (WP-1)(See Data Sheet CS-2308).。
x9511_中文

±0.009
BASIC
参考
参考
笔记
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1, 3
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2, 3
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牧师L 2/01
Intersil公司所有产品的制造,组装和测试都采用ISO9000质量体系标准。
Intersil公司的质量CERTI网络阳离子可在/design/quality观看
机器型号
(每EIAJ ED- 4701方法C - 111)...................... 250V
模拟特性
电气特性
端至端阻值偏差...........................±20%
额定功率在+ 25°C
X9511W ................................................. 10mW
“不包括1.塑料或金属的0.010突起最大每一侧。
“不包括0.010 2.塑料引脚间的突起最高每边。
3.尺寸E和EA的测量与约束垂直于飞机座位的线索。
4.尺寸EB是测量不受约束的导线头。
5. 8和16引脚封装有一半最终引线,如图所示
小型封装系列(SO)
A
D
N
(N/2)+1
高x 45¡
A
E
E1
针#1
内径MARK
交流工作特性(在推荐工作条件,除非另有规定):
上电和掉电要求
在上电的时候没有顺序限制,与电压施加到电位器的引脚上电时
或断电状态。上电过程中,数据表参数DCP并不完全后申请到1毫秒
V
CC
达到其最终值。在V
CC
斜坡率规范是始终有效。
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OCXO SERIES 4000
n FEATURES APPLICATIONS Excellent frequency stability - SATCOM
Mechanical / Electrical frequency adjustment available - BASE STATIONS
- TEST INSTRUMENTS
n ELECTRICAL PERFORMANCE
PARAMETER OCXO SERIES 4000
AT CUT CRYSTAL SC CUT CRYSTAL Supply voltage, nom. 15V, 12V, 5V ±5% Standard
Power dissipation steady state 2.5 Watt Max.
Heat up power 5 Watt Max
Heat up time. 7 min Max
Frequency range 1 To 160 MHz Standard
Frequency Adjustment:
Electrical (0 to 5V) Electrical (0 to 10V) Mechanical ±10PPM Min
±15PPM Min
±1.5PPM Min
±0.7PPM Min
±1PPM Min
±0.6 PPM Min
±0.05 PPM
±0.1 PPM
±0.002 PPM
±0.005 PPM
Freq. stability vs. temperature
LX: 0°C to 60°C
FZ: -30°C to 70°C
(Standard, contact factory for different temp ranges and stabilities) Freq. stability vs. supply
changes
±0.005 PPM Max for ±5% Change ±0.002 PPM Max for ±5% Change
Freq. stability vs. load
changes
±0.005 PPM Max for ±5% Change ±0.001 PPM Max for ±5% Change
Long term stability (Aging) ± 1.5 PPM Max for 10 Years
± 0.3 PPM Max for 1 Years
±0.002 PPM/Day Max. ±0.6 PPM Max for 10 Years ±0.05 PPM Max for 1 Years ±0.0005 PPM/Day Max.
Output HCMOS/TTL/Sine 0 to +13dBm Harmonics, Sub Harmonics -30dBc(Sine Output)
Spurious -75dBc(Sine Output)
Duty cycle 40/60% to 60/40%(HCMOS)
Rise / fall time 10nS Max. (HCMOS,10%~90%Vout, 90%~10%Vout) Short term Stability (10MHz) 1 E-10 /Sec 5 E-11 /Sec
Phase Noise typical under static conditions
(Sine Output 10MHZ) Offset Phase Noise
10Hz -95 dBc/Hz
100Hz -125 dBc/Hz
1000Hz -135 dBc/Hz
10000Hz -150 dBc/Hz
Offset Phase Noise
10Hz -115 dBc/Hz
100Hz -135 dBc/Hz
1000Hz -145 dBc/Hz
10000Hz -150 dBc/Hz
Note: All Typical parameters for a 10MHz output and 5V Supply, for different frequencies consult factory
n HOW TO ORDER (PART NUMBER)
Prefix Output Type Cut Type
Series Revision Temperature Range Stability Frequency
Supply Voltage OX
1:TTL 2:HCMOS 3:ACMOS 4:LVCMOS 5:100K ECL 6:SINE 7:10K ECL 8: PECL 9:CUSTOM
0:AT (No Vcontrol ) 1: SC (No Vcontrol ) 2: AT (Mechanical Adj) 3: SC (Mechanical Adj) 4: AT (Elect Vcontrol) 5: SC (Elect Vcontrol) 6: AT (Mech & Elect.) 7: SC (Mech & Elect.)
4X:4000 40:
Height=
1”/25.4mm
41:
Height=
2”/50.8mm
42:
Height=
4”/101.6mm
44~49:
Odd Height
A
First letter Lowest Temperature,
Second letter Highest Temperature: From A=-55°C to Z=+70°C, Then: 1=+75°C, 2=+80°C, 3=+85°C… in 5°C steps Example: LZ: +0°C to +70°C LX: +0°C to +60°C FZ: -30°C to +70°C D3: -40°C to +85°C
Value x
10E-2 in PPM
Example 28=
0.28PPM 10= 0.1PPM
In MHZ
5: 5V 12; 12V 15; 15V。