General Terms Algorithms.

Gain-Based Technology Mapping for Discrete-SizeCell LibrariesAbstractIn this paper we describe a technology mapping technique based on the logical effort theory [13]. First, we appropriately characterize a given standard cell library and extract from it a set of cell classes. Each cell-class is assigned a constant-delay model and correspond-ing load-bounds, which define the conditions of the delay model’s validity. Next, we perform technology mapping using the classes determined in the first step. We propose several effective area-opti-mization heuristics which allow us to apply our algorithm directly to general graphs. E xperimental results show that our gain-based mapping algorithm achieves reduced delay with less area, com-pared to the mapper in SIS [15]. By adjusting the constant delay model associated with each class, we determine the area-delay trade-off curve. We achieve the best area-delay trade-off using a design-specific constant delay models.Categories and Subject DescriptorsJ.6 Computer-Aided Engineering - Computer-aided Design (CAD) General TermsAlgorithms.KeywordsLogic effort, gain, technology mapping1.IntroductionTechnology mapping is an essential step in logic synthesis for ASICs. Numerous technology mapping algorithms have been pro-posed in the literature [3][7][10][12][16] targeting traditional area-optimized standard cell libraries. In such libraries, each cell type may be available in several size instances. The larger the size instance of a cell, the more driving capability the cell provides. In addition, each cell is described by a load-dependent delay model which estimates its delay for the load it drives. The load of a cell includes the next-stage gate capacitance and interconnect capaci-tance. As technology advances, interconnect coupling capacitance also contributes to the cell’s load. In technology mapping using an area-based library, the interconnect capacitance is usually estimated by a wire-load model [2], especially when the layout information is not available.In [13], the concept of logical effort has been proposed to model the load-independent gate delay.(EQ1) In this model, the gate delay has been divided into two parts. Part (1) consists of the load dependent effort delay, in EQ1. The logical effort e is related only to the gate topology and is indepen-dent of the load capacitance. The gain g is defined by the E Q2 below, where is the output load, and is the gate input capacitance. Part (2) of the delay model is the load-independent parasitic delay p caused primarily by the gate’s parasitic capaci-tance.( EQ2)It can be seen from this model that the delay of a gate is indepen-dent of the output load as long as the gain g is known.Based on this delay model, [13] states that the optimal delay of multi-level logic is achieved when the effort delay is bal-anced for all the stages along critical paths. Since different cell types usually have different logical effort e, the optimal delay con-dition imposes different gain g requirements for them. The larger the logical effort, the less output load a cell can drive while main-taining the same effort delay.The authors of [6], [8], [14] proposed a delay-optimal, load-inde-pendent model based technology mapping algorithms for general graphs and achieved good timing results. Their approaches are applicable to continuously-sized networks [4] but are not suitable for a practical standard cell library where the assumption of contin-uously sizable cells does not hold. The logical-effort-based fanout optimization described in [11] also requires a near-continuous size buffer library.In this paper we propose a technology mapping technique based on the logical effort theory [13]. First, we appropriately characterize a given standard cell library and extract from it a set of gain-based cell classes. Each cell class is assigned a constant delay model and appropriate load bounds, which define the delay model’s validity. Next, we perform technology mapping using the classes determined in the first step. Several effective area optimization heuristics are proposed to make our algorithm applicable to general graphs. Experimental results show that our gain based mapping algorithm achieves reduced delay with less area, compared to the mapper in SIS[15]. By adjusting the constant delay model associated with each class, we derive an area-delay trade-off curve. We observe that the best area-delay trade-off is achieved for design-specific con-stant delay models.2.Gain-based cell class extractionAll the existing technology mapping algorithms which use the load independent models are based on the assumption that a cell can bePermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.DAC 2003, June 2-6, 2003, Anaheim, California, USA.Copyright 2003 ACM 1-58113-688-9/03/0006...$5.00.d e g⋅p+=e g⋅C out C ingC outCin----------=e g⋅Bo HuECE Department Univ. of CA, Santa Barbara CA 93106, USAhb@Malgorzata Marek-SadowskaECE DepartmentUniv. of CA, Santa BarbaraCA 93106, USAmms@ Yosinori WatanabeAlex KondratyevCadence Berkeley LabsBerkeley, CA 94704{watanabe, kalex}@34.1sized continuously to maintain its delay independence of the out-put load capacitance. This requirement is rarely satisfiable in com-mercial standard cell libraries. For example, it is possible that even the largest cell in the library cannot satisfy the load requirement and maintain the constant delay. Usually, a cell of a particular type has only 3 or 4 instances of different sizes. However, for each cell type we can determine a range of load capacitances for which the constant delay model holds. If the load capacitance is out of that range, there is no cell in the library which can drive such a big load while preserving constant delay.In the following subsections, we describe the three-step procedure of building the gain-based library used in our gain based technol-ogy mapping process.2.1 Cell characterization - deriving e and p First, we characterize each cell in the standard cell library using the delay model of E Q1. Usually, the gate delays in the original library are given in terms of table-lookups. A particular delay value with respect to such parameters as load, input slew rate, or input transition (falling or rising) can be retrieved from the table by using the specific values of those parameters as table indexes. Without loss of generality, let us assume that the original cells have the same rising and falling delay models. In case they are different, we take the worst case. We also assume that all the inputs of a cell have the same delay models. If they are different, we take the worst case delay. Extension for the general case is straightforward and this assumption does not limit the principle of our approach. As for the input slew rate, the situation is more complicated. Since the gate delay model in the library is usually different for different input slew rates, we have to determine an appropriate input slew rate in order to derive a model like that in EQ1. We have conducted experiments with commercial ASIC designs and observed the gen-eral tendency that slew rates are roughly the same along the critical paths under the condition that each stage has similar effort delay. It is also true that in custom or semi-custom designs, an experienced designer usually knows the circuit’s target slew rate. So we choose to set the target slew rate as a variable which can be user-defined. Once a target slew rate is given, the delay table of the cell is used to identify the relationship between the output load and delay. This relationship is linear for a practical range of load, and thus follows the model given in EQ1. Using this linear portion of the relation-ship and EQ1, we compute e and p.2.2 Determining the cell target gain g and the max load lAfter completing the first step, each cell is associated with the e and p values which specify the load independent delay model. Unlike the methods of previous works, ours provides a user-defined parameter global gain G, which is used to determine the target effort delay at each stage. G is determined with respect to the inverter in the original library. The target gains of the other cells can be determined based on the condition that each cell should have the same effort delay as in EQ3.(EQ3)Here denotes the logical effort of the inverter. Once the target gain for a cell is determined, we compute the corresponding maxi-mum output load l and delay value d associated with the target gain. From EQ2, l is given by EQ4.(EQ4) The delay d is obtainable from EQ1 since all the values of the right hand side of the equations are available now. The cell delay does not exceed d if the output load is less than or equal to the max-load l.2.3 Extracting gain-based cellsAs stated in [13], different instances of the same cell type have similar values of e and p parameters, although their sizes might differ significantly. Thus it is possible to reduce the complexity of the original library by using a single, constant-delay-based, or gain-based in our context, cell to represent a set of original cells with similar e and p.Definition 1: A gain-based cell c is a cell described by a property tuple (f, d, C, , ) where f represents the cell’s functionality;d is the load independent, constant delay of the cell; C is a set of cell instances from the original library; and are arrays of input capacitances and max loads, respectively. and are obtained by enumerating C in and l for each cell in C, and sort-ing them in ascending order.In fact, represents the range of output load capacitance. Within this range, the delay value less than or equal to d is guaranteed by choosing any cell in C if its max-load l is larger than the output load. We point out that acts like a constraint under which a constant delay model can be applied, and this constraint is implied by the limitation of the original library. In contrast, previous works applied a constant delay model in an unconstrained manner, since they assumed that cells were continuously sizable.We build the new library composed of gain-based cells as defined above. Each gain-based cell represents a set of original library cells with similar e and p. For example, four NAND2 cells can be repre-sented by one gain-based cell which has the same functionality as NAND2.In practice, one may restrict the range of input capacitances and loads defined by and within a certain bound. This is often the case for inverters, where state-of-the-art ASIC libraries contain inverters with various delay characteristices. In particular, those mainly used for clock trees have significantly different gains from the rest of the inverters. In such a case, it is possible that cells with the same functionality in the original library belong to different gain-based cells in the resulting library.3.Gain-based technology mappingAn AND-INV representation of the input netlist is referred to as a subject graph. A node in the subject graph is either of a type AND, INV, primary input, or primary output.A pattern is an AND-INV tree representation of a library cell. A match occurs when a pattern is identified in the subject graph. We refer to the nodes in the subject graph corresponding to the matched pattern as the internal nodes of the match. The inputs of a match are those nodes in the subject graph, which fanout directly to the internal nodes of the match and are not included in the match.A partial pattern is a sub-graph of an AND-INV tree representation of a library cell. Partial patterns can be used to create patterns. A partial match is obtained when a partial pattern is identified in the subject graph. The internal nodes and inputs of a partial match are defined similarly to those of a match.A solution s of a node i, denoted by s[i], in the subject graph is a match rooted at i. Solution s[i] stores the following information: (1) a cell c in the gain based library, denoted by c(s[i]), and (2) the cost tuple (D, L), where L represents the max-load s[i] can drive, and D represents the arrival time at i if the actual load is less than or equal to L.L determines the upper load bound. Within this bound the solution s[i](D, L) can deliver a signal before or at the time D. The tuple (D, L) measures the quality of solutions. For example, a solution with larger L (driving capability) and less D (arrival time) is pre-ferred. In the following description, we use D(s[i]) and L(s[i]) to represent D and L value related to the solution s[i].We store a set of non-inferior solutions at each node. A solution is called non-inferior if no other solution is better in terms of D and L. We do not record any area-related information about the solu-e g⋅gG e inv⋅e-----------------=e invl C in g⋅=C IN C LCINCLC IN C L C LC LC IN C Ltion since we are dealing with general graph mapping and such an information is unknown until we create the mapped netlist. We apply several effective area-optimization heuristics in the back-ward traversal phase to create a network with the smallest area.The mapping procedure is based on the bottom-up matching algo-rithm described in [5]. The idea is to store not only the complete matches (the solutions in our case) but also the partial ones. By doing so, when a node is processed, we only need to check the matches or partial matches at its immediate fanins and use such information to create new matches at the current node. In this way,a significant speedup is achieved. We denote a partial match at node i as p[i] and associate it with a cost tuple (D, L) as we do for solutions. We will show in the next section how exactly such a tuple is computed for a partial match. In addition to the non-infe-rior solutions (complete matches), we also maintain a set of non-inferior partial matches for each partial pattern at each node in the subject graph. The definition of non-inferior partial match is simi-lar to that of the non-inferior solutions.The approach in [5] uses only tree patterns. To handle some of the non-tree cells, such as the XOR gates, we represent such a cell using a tree pattern by duplicating the inputs and perform an addi-tional check when a match for the pattern is found in the subject graph. Specifically, we associate conditions about which inputs of the tree pattern have to be identical, and permutation of the inputs of the match are examined to check the conditions. If the condi-tions hold, then a solution with XOR cell may be generated based on this match.To take into account different AND gate decompositions, we use the technique proposed in [9] and build a mapping graph which encodes all decompositions of AND gates up to 5 inputs. For ease of explanation, we assume that the mapping is performed on the subject graph and that the subject graph consists of only AND and INV nodes.3.1 Forward phase - generating solutionsIn the solution generation phase we traverse the subject graph in topological order from the primary inputs to the primary outputs.Topological order guarantees that when a node is processed, all of its fanin nodes have been processed already. In the following, we describe the procedure that generates all the solutions at one node.For each already processed node, there is a set of non-inferior par-tial matches for each partial pattern. The cost tuple (D, L) of each match or partial match is computed based on the costs of the solu-tions at the inputs of that match. Particularly, for each primary input, (D, L) can be set by the designer and D is the arrival time of primary input and L is the maximum load it can drive. In the fol-lowing, we use the example shown in Figure 1 to illustrate the pro-cedure of creating partial matches and solutions for internal nodes. Suppose that the node i in figure 1 is currently processed. The inputs to i are the nodes m and n , which have already been pro-cessed and associated with, for simplicity, only a set of solutions but no partial matches. Suppose the nodes m and n have two solu-tions each. First, we create the non-inferior partial matches at nodei . If the node i is an AND type, it is obvious that an AND pattern has a match here if an AND pattern indeed exists in the pattern set.Thus we create a partial match p0[i](D, L) based on both solutions s0 from m and n . D(p0[i]) is the arrival time of the partial matchp0[i] and assumes the worse of two values D(s0[m]) or D(s0[n]).L(p0[i]) is the max load of the partial match p0[i], which assumes the smaller value of L(s0[m]) and L(s0[n]). By enumerating all pairs of solutions at m and n , a set of partial, non-inferior cost matches can be built.Partial matches can also be built from partial matches. In Figure 1,if the node m and the node n have partial matches, we can also cre-ate non-inferior partial matches from them using the same proce-dure above.During the partial match construction process, we check to see whether any of the newly created partial matches could be trans-formed into a solution. Take the previous example, and suppose that an AND cell is available in the gain based library; we can reduce partial match p0[i](D, L) to a solution s0[i](D, L). The D(s0[i]) is the sum of D(p0[i]) and the constant delay of the cell,in this case, the AND cell. Simply put, the arrival time of the solu-tion is the sum of its input worst arrival time, D(p0[i]), and its own delay.Determining the L(s0[i]) is somewhat more complex. To derive a solution from a partial match p0[i](D, L), we have to determine whether p0[i] has the capability to drive the gain based cell c wechoose for the solution. Thus, the following condition has to besatisfied:, (E Q5)In EQ5, is the j th input capacitance of as definedin section 2.3. E Q5 checks if L(p0[i]) is larger than at least one input capacitance in the array , which stores all the input capacitances of the original library cells included in the gain based cell c. In other words, EQ5 guarantees that there exists at least one original library cell such that the capacitance of each input of the cell does not exceed the upper load bound of the solution at the corresponding input of the s0[i] from which the partial match p0[i]was created.Based on EQ5, we find the largest possible index j such that EQ5holds. L(s0[i]) is given by , which is the j th max-load in as defined in section 2.3. Simply, L(s0[i]) is the largest pos-sible max load value we can assign to a solution s0[i] while still guaranteeing the worst case delay D(s0[i]).It can be seen that L(s0[i]) is computed in such a way that it con-sumes all the driving capability of some, if not all, input solutions.In other words, it assumes that input solutions have only one single fanout: that is, the current solution. So if there is a solution of another node which uses the same input solutions, some input solutions might not be able to drive both fanouts within the maxi-mum loads. We call this situation a max-load violation. However,it does not cause any problem to our mapper because in the back-ward traversal phase, we will decide whether the solution is shared or duplicated to correct any max-load violations, if required, to achieve the target timing.For the same reason, we can handle naturally the wire load model in the mapping phase. To do so, we modify EQ5 to incorporate the capacitance of a two-pin wire as stated in EQ6., (E Q6)E Q6 says that the inputs of p0[i] should be able to drive at leastone 2-pin wire in addition to the library cell c. In backward tra-versal, we still use solution/gate duplication if necessary. In an extreme case, we can duplicate every solution such that only 2-pin wires exist in the mapped network except the primary inputs,although it might not be desirable due to excessive area overhead and/or performance degradation. This problem is discussed in detail in Section 3.2.2.s 0[m](D, L)s 1[m](D, L)s 1[n](D, L)s 0[n](D, L)i nmp 0[i](D, L)s 1[i](D, L)ks 0[i](D, L)Fig. 1: Generating partial matches and complete solutions atnode i L p 0i []()C IN jc ()>j ∃C IN c ()<C IN jc ()C IN c ()C IN c ()C L jc ()C L c ()L p 0i []()C IN jc ()C 2pin +>j ∃C IN c ()<We also perform buffer insertion when creating solutions. For example, as shown in Figure 1, we check to see whether a non-inferior solution s1[i] with a buffer cell could be used as well as the s0[i]. With the same procedure, we can build a buffer chain where each stage constitutes a non-inferior buffer solution.The above procedure is applied to every node in the subject graph.During the process, only non-inferior partial matches and solutions are maintained.At the end, we obtain a set of solutions for each primary output. It follows from EQ6 that each solution s guarantees the existence of a tree implementation of the primary output using the cells of the original library whose delay is at most D(s) if the wire capacitance is compatible with that used in E Q6 and the load at the primary output does not exceed L(s). In practice, it is often possible to share logic among implementations for different outputs while satisfying the load and delay requirements. We present procedures for effec-tively selecting solutions in the next section.3.2 Backward phase - solution selection and area optimizationAfter all the nodes have been processed and associated with a set of solutions, we traverse the subject graph from the primary out-puts to build the final mapped network. We use a procedure which combines the following several heuristics.3.2.1 Selecting SolutionsGiven the required time and load requirement at primary outputs,we first sort the primary outputs according to their criticality in time under the load requirement, where without loss of generality,we assume that there is at least one solution that meets the load requirement for each primary output.When selecting a solution, we are guided by the constraint tuple (L, R). L states that the selected solution must have the driving capability larger than L. R is the required time the solution must meet. Among the eligible solutions, we select the one with the largest driving capability. This is our maximum max-load heuris-tic. Figure 2 illustrates an example. Referring to figure 2, suppose we are to select a solution for the node i under the constraint (L, R)propagated from the previous stage - in this case, a NOR gate.Since it is unknown a priori how many fanouts a node will drive because we encode several decompositions [2] and fanouts might be duplicated, we select a solution which can drive as many fanouts as possible. Suppose the node i has two candidate solutions s0 and s1 with D0 < R , L0 > L and D1 < R , L1 > L; L0 > L1. Apply-ing our max-load heuristic, s0 is selected to be implemented at node i .Once a solution is selected at a node, we form a new constraint and propagate it to the fanins of the selected solution. is the input capacitance of the selected solution and is the new required time R - D(s0).The above procedure is applied to a node which has never been visited before. In case when a node has been visited already andone or more solutions may have been selected, we first check to see whether there exists any selected solution which satisfies the new constraint. In the example above, when the node i is visited again from the edge connecting to node j , since s0 has already been chosen previously, we first find out whether s0 can be reused. If so,we choose s0. If no existing solutions can be used to fulfill the new requirement, the same procedure as the one used to select s0 is invoked.Observe, that once a solution has been reused, it is possible that the real load from all the fanouts might exceed the max load. This max load violation will be rectified in the solution refinement and /or duplication phase.3.2.2 Duplicating SolutionsIn the case when a solution drives more load than its max-load allows, solution duplication is necessary to achieve the target gain.But care must be taken to avoid excessive duplication. Excessive duplication will eventually compromise the performance. Usually,primary inputs are outputs of other logic blocks, and thus we can-not assume that they possess an infinite driving capability. Exces-sive duplication might cause a dramatic increase in the load that the primary inputs drive. As a result, the speedup achieved by duplication might be overwhelmed by the delay penalty caused by excessive loading of the primary inputs.It is not trivial to tell whether duplication is really necessary. It could be a by-product of earlier incorrectly selected solutions, or previous unnecessary duplications. There is no global metric of a network which could be used to justify the necessity for duplica-tion.In light of this analysis, we try to avoid duplication as much as possible. We duplicate only those solutions which are on the criti-cal path and whose max-load is violated. To do this, we traverse the network in topological order from primary outputs. When deciding whether duplication should be performed on a solution s ,we first compute the real required time for s . We obtain by performing static timing analysis on the mapped network. If max-load of s is larger than its fanout load, we skip s ; otherwise, we fur-ther check on the need for duplication. In the case when max-load constraint is violated, but the slack existing in s allows us to meet target timing, we skip duplication. Because of the order in which the network is traversed, when s is processed, no solutions in its fanin cone have been processed yet. We define a partial slack S(s)using EQ7:(EQ7)In this equation, D(s) is the delay value associated with s . Given a partial slack S(s), if max-load violation of s can be tolerated within the target timing, we skip the duplication. We note that S(s) acts like an implicit slack assignment. The advantage of introducing S(s) is that a duplication can be avoided even at the node where the load violation is observed with respect to the delay given in the gain based cell, as long as the actual delay required to drive the load is within the available slack. Further, using S(s) we provide more flexibility for choose solutions at the fanins of the current node.Solution duplication procedure is interleaved with the gate sizing described in section 3.2.5. Gate sizing is performed on both dupli-cated and original solutions to reduce the loading of fanin solu-tions.3.2.3 Refining solutionsThe objective of the refinement step is to eliminate unnecessary duplication. Intuitively, we would like to choose the solutions with larger driving capabilities and less area overhead while still meet-ing timing requirements. Here the driving capability of a solution refers to its max-load constraint.In the solution refinement step, we take into account both the net-work area and the overall driving capability and penalty. We uses 0(D, L)s 1(D, L)(L, R)ijFig. 2: select a solution with max drive for node iL 'R ′,()L 'R 'R 'R 'S s ()R 'D s ()–=the following metric to compare solutions s0 and s1. A solution s0 is better than s1 if one of the following conditions holds:(1) s0 can drive all the fanouts, but s1 cannot; choosing s0 allows us to avoid duplication.(2) s0 and s1 can drive all the fanouts, and cost(s0) < cost(s1). The cost of a solution is given by E Q8, where F A(s) is the area of fanout free region (FFR(s)) rooted at s. In other words, if s is deleted, the area saving is F A(s). F A(s) reflects the area overhead introduced by s only. FC(s) is the total input capacitance of the leaf nodes in FFR(s). FC(s) gives the overall capacitance which has to be driven by the rest of network if s is introduced. It is intuitively plausible that less capacitance is desirable to avoid solution dupli-cation. FD(s) is the total spare driving capability of all solutions feeding FFR(s). The idea is to select those solutions which depend on strong drivers so that duplication is less likely to occur. Spare driving capability specifies how much more capacitance a solution can drive before reaching its max-load constraint.(EQ8)(3) neither s0 nor s1 can drive all the fanouts. We modify EQ8 to take into account max-load of the solution, as expressed in EQ9, to avert a possibly unnecessary duplication.(EQ9)We perform the solution refinement immediately after the solution selection, since at that time, the initial mapped network has already been built, and we have more accurate fanout information for each selected solution. We visit each node in topological order from pri-mary outputs and use the metric described above to select better solutions than the existing ones.3.2.4 Gate sizingE ach solution is associated with a gain-based cell representing a set of original, different-sized cells. It is the gate sizing’s task to pick a specific cell from each set to actually implement the solu-tion and thus construct the mapped network.We traverse the subject graph in topological order from primary outputs. For each solution at the visited node, we choose the small-est original library cell which meets the target timing. In fact, we use either partial slack in EQ7 or real slack from static timing anal-ysis, depending on the stage of network generation, since we apply gate sizing both during solution duplication and after solution merging. In the solution duplication step, we use partial slacks. That is, we choose the smallest library cell which can be tolerated by partial slack available at the visited node. After solution merg-ing, we use the real slack to determine if a cell can be down-sized.3.2.5 Merging solutionsIt is possible to merge solutions such that one of them is sufficient to drive all the fanouts. This procedure may reverse bad decisions made at the duplication step. It is possible because partial or real slack is often available on non-critical paths.We traverse the subject graph in topological order from primary outputs to primary inputs. For each node in the subject graph, if multiple solutions exist at this node, we check whether it is possi-ble to use a single solution to drive all the fanouts of two or more existing solutions without violating the target timing. If that is the case, we replace those solutions by a single one. In this way, we can reduce the network area and load capacitance.4.ExperimentsWe implemented the gain based technology mapper in SIS1.2 [15]. We used a 0.18u commercial standard cell library for the experi-ments. All the experiments were run on 1.4Ghz Pentium 4 proces-sor with 1G bytes memory. The operation system is GNU/Linux Mandrake 9.0. We use a wire load model which computes the capacitance of a wire according the number of its fanouts.4.1 Gain vs. Area-Delay trade-offIn this experiment, we explore the area-delay trade-off by using different global gain values. After selecting a global gain, the delays of all gains based cells are fixed with respect to this gain regardless of load capacitance. Once the mapper finishes its for-ward traversal phase, the minimum delay at the output is known and we call it the target delay. Clearly the value of the target delay, to a large extent, is determined by the target gain. The larger the gain, the larger the target delay. For example, if we want a high performance, we can set the target gain to a smaller value and achieve a smaller target delay. But a smaller gain value usually requires more area. This is so because smaller target gain value implies an overall smaller driving capability for all cells. Thus it is possible that more area is required because more duplications are necessary to satisfy the gain requirement. It is interesting to explore how delay and area react to different values of the target gain.In Figure 3, we show the area-delay trade-off for different gains for the benchmark C1355. The x and y axis represent delay and area of the circuit after mapping. The curve is determined by using differ-ent values of target gains, which are marked in the figure for each data point. It can be seen that to achieve the best area-delay trade-off, the target gain value has to be carefully selected. For the exam-ple in Figure 4, G = 2.25 is a reasonable choice (delay = 2.26 ns at this point) since smaller gain comes with a large area overhead. Although it is indeed possible to implement C1355 with delay less than 2.1ns as indicated in Figure 3, where the target gain is less than 2, the area is prohibitively large due to excessive duplication. In general, we observe that good delay-area trade-off is generally located within a rather limited gain region 1.6 ~ 2.5. Fig 4 gives another delay-area trade-off curve for C880. It indicates that even if user-predefined G is not available before technology mapping, it is possible to create a gain based library which combines a small set of gains selected within that range. Since our gain based library with respect to one gain consists of only around 20~30% cells compared to the original library, the new library based on a set of gains is still managable by our mapping algorithm.t s() cosFA s()FC s()⋅FD s()----------------------------------=t s() cosFA s()FC s()⋅FD s()L s()⋅----------------------------------=Fig. 3: Area-delay trade-off for C1355。