Some Timing Terminology

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高速pcb设计与电路板分析课程讲义3

高速设计分析技术Agenda 课程安排High Speed Trends 高速设计趋势y gSynchronous Design 同步系统设计Source Synchronous Design 源同步系统设计-DDR2-DDR3Serial Link Design 高速串行设计-Interconnect consideration 互连考虑I t t id ti-Technologies 设计技术-8b/10b Encoding 8b/10b编码Trend towards serial connectivity向串行连接发展高速电路设计趋势Parallel I/O − Common Clock并行IO –共同时钟系统Pre-layout simulation for design exploration and post-layout simulation for verification可以通过SI前后仿真进行设计•Signal timing 信号时序•Signal noise 信号噪声•Undershoot and overshoot 过冲Parallel I/O − Common Clock (继续) 并行IO –共同时钟Increase data pin counts How to increase data rate? 如何提高数据速率Increase data pin counts 增加管脚Increase bus clock frequency 增加时钟频率But…… 但是……•Increase data pin counts − it’s more hard for PCB design(need more space for trace breakout, routing…..) 增加管脚造成PCB 设计困难•Increase clock frequency − it will reduce timing margin,destroy signal integrity (due to multi-drop top.), restrict data trace length, increase EMI…增加时钟频率使得时序紧张, 信号完整性问题突出, 走线线长约束严格, 电磁辐射增加…Parallel I/O − Source Synchronous并行I/O –源同步系统Provide guidelines for physical layout by sweeping the solution space 可以通过参数扫描分析确定电气约束Measurements for voltage and time specifications and worst case Measurements for voltage and time specifications and worst case report 得到最坏情况下的信号质量和时序要求Bus timing analysis 总线时序分析•Slew rate prorating/derating for Setup/Hold Time compensations (DDR2) 考虑边沿速率造成的的建立保持时间的补偿(DDR2)Increase bus clock frequency Parallel I/O − Source Synchronous (继续)并行I/O –源同步系统How to increase data rate? 如何提高数据速率Increase bus clock frequency 增加时钟频率From single strobe to dual strobe 采用读写数据采样时钟From single end strobe to differential strobe signaling 采用差分时钟•Increase bus clock frequency − there is no theoretical limit on bus clock frequency, but higher clock frequency will cause signal integrity depredation(due to multi ‐drop top.) But…… 但是……p (p p )增加时钟频率使得信号完整性问题突出…•From single strobe to differential strobe − for less timing margin while design migrates to high speed, differential strobe will increase valid timing window采用差分时钟提高速率但是因为速率提高, 时序参数更为紧张Parallel I/O -Integrating SI with Timing 并行接口分析–综合考虑SI 和时序Multiple TopologiesWaveformandSolution SpaceTiming Equation Signal Integrity and Timing Analysis integrated to one solution 信号完整性和时序分析组成一个完整的解决方案Vin_AC_HighVin_DC_HighVrefVin_DC_LowVin_AC_Low “Sim Start time” normalizedSerial I/O 串行I/OInterconnect loss of the channel (entire signal path) 考虑互连损耗Jitter controlled is required due to CDR 控制抖动Modeling complex drivers and receivers 需要更复杂的器件模型 Stress test the design with LARGE bit streams 要分析大量数据位传输S-parameter simulation (Time domain & Frequency Domain) S-参数分析, 时域和频域分析Agenda 课程安排High Speed Trends 高速设计趋势y gSynchronous Design 同步系统设计Source Synchronous Design 源同步系统设计-DDR2-DDR3Serial Link Design 高速串行设计-Interconnect consideration 互连考虑I t t id ti-Technologies 设计技术-8b/10b Encoding 8b/10b编码Synchronous Design 同步设计系统Sometimes called “Common Clock” 又叫共同时钟系统Clocks are distributed from a central point to all of the loads. 时钟信号由同一时钟源发送Max operating frequency is a function of Tco, Tpd, Setup, Hold, and M ti f i f ti f T T d S t H ld d Clock Skew最大工作频率由缓冲延时，传输延时，建立，保持时间和时钟偏移决定Synchronous Data Transfer 数据传输方式Clock 14HoldDriverT coFlight Time Setup23D0 D1 D2D0 D1 D2Driving ReceivingSynchronous Timing Terminology时序参数Cycle Time (Tcycle)时钟周期Clock Skew时钟偏移Cycle 1Cycle 2 Clock to Output (Tco)时钟输出延时Clock JitterSynchronous Timing Terminology (继续)时序参数Interconnect Delay (Tpd)互连传输延时Positive Interconnect Delay (Tpd)Negative Interconnect Delay (Tpd)Defining Tco Tco 定义Tco = time from clock rise to Vmeas into test load从时钟边沿进入器件到数据从器件输出有效的时间(数据输出接测试负载)DinClockOutput BufferInternal LogicClock rises t = 0V measT R L = 50 ΩTcoLoad for Tco measurement (from databook)Components of Tco Tco的组成ClockI t lClockDinOutputBufferInternalLogicR L= 50 Ωrisest = 0V measTcoInternal delay = from clock rise to the point where the output begins to switch内部逻辑时延External (buffer) delay = how long the buffer takes to drive the reference load to V meas缓冲器时延Clock Jitter 时钟抖动Clock Clock Jitter occurs when the clock period varies from one period to the nextDriverCycle 1Cycle 2one period to the next 考虑周期差抖动•Usually caused by PLLinstability in the clockdriver 通常由锁相环引起 Jitter increases / decreases the clock periodthe clock period,decreasing the effective clock cycle 抖动减小有效时钟周期Clock Skew 时钟偏斜Clock Driver t = 0Occurs when differentdevices see the clocktransition at differenttimesD0D0t = 1t = 2时钟到达不同器件的时延Increases / decreasesthe apparent clockcycle. Depending onwhich devices aredriving / receivingD1D2D1D2g g根据驱动接收不同变化Reduces the effectiveclock cycle 减小有效时钟周期内部偏斜和外部偏斜•时钟驱动器造成内部偏斜•而PCB布线和设计以及外部环境引起的偏斜被称为外C部偏斜tSKEW_INTRINSIC = 器件引起的偏斜tSKEW_EXTRINSIC = PCB + 布线＋工作环境引起的偏斜tSKEW = tSKEW_INTRINSIC + tSKEW_EXTRINSIC内部偏斜-输出偏斜(tSK）•单一器件的指定输出之间的偏斜(JEDEC)•输出偏斜也称为引脚到引脚的偏斜。

踢足球英文

踢足球英文Football, also known as soccer in some parts of the world, is a popular sport that has gained worldwide recognition. In this document, we will explore the basics of playing football and familiarize ourselves with some commonly used English terms related to the sport.To begin with, let's talk about the rules of football. The game is played between two teams, with each team consisting of eleven players. The objective is to score goals by kicking the ball into the opponent's net. The team with the highest number of goals at the end of the game is declared the winner.The game starts with a kickoff, where one team begins with possession of the ball. The players use various techniques to maneuver the ball around the field. Passing is an essential skill in football, where players kick the ball to their teammates to maintain possession or create scoring opportunities. Players also use dribbling, which involves moving the ball while maintaining control with their feet.Defending is equally important in football. Players use tackles to dispossess opponents of the ball. The defender needs tobe agile, quick, and possess good timing to execute a successful tackle without fouling the opponent. A foul occurs when a player commits an illegal action, such as tripping, pushing, or handling the ball with their hands.Another aspect of football is set pieces, which are specific situations in which the game resumes after a stoppage. Some common set pieces include free kicks, corner kicks, and penalty kicks. A free kick is awarded when a player from the opposing team commits a foul. The ball is placed at the spot of the foul, and the team with possession gets a free attempt to kick the ball towards the opponent's goal without any interference. Corner kicks are awarded when the defending team is the last to touch the ball before it crosses the goal line. The attacking team takes a kick from the corner of the field, aiming to score a goal. Penalty kicks occur when a foul is committed inside the penalty area. The attacking team gets a one-on-one opportunity to kick the ball into the goal, with only the goalkeeper to beat.In football, there are various positions that players can occupy on the field. Let's take a look at some of the most common positions and their respective roles. The goalkeeper, also known as the goalie, is the player who defends the goal and prevents the opponent from scoring. Defenders are responsible for stopping the opponent's attack andprotecting the goal. Midfielders play a crucial role in both defending and attacking. They link the defense and the forward line, contributing to both parts of the game. Forwards, also known as strikers, are primarily responsible for scoring goals.While playing football, communication among teammates is essential. Here are some English terms commonly used on the football field:1. Pass: To kick the ball to a teammate.2. Shoot: To kick the ball towards the opponent's goal in an attempt to score.3. Tackle: To dispossess your opponent of the ball by kicking it away from them.4. Offside: A player is in an offside position if they are closer to the opponent's goal line than both the ball and the second-last defender at the moment the ball is played to them.5. Header: To strike the ball with your head.6. Dribble: To move the ball while maintaining control with your feet.7. Corner: A set piece where the attacking team takes a kick from the corner of the field.8. Penalty: A one-on-one opportunity to score a goal from 12 yards away, awarded for a foul inside the penalty area.In conclusion, football is a thrilling sport with a global fanbase. It requires teamwork, skill, and strategy. Understanding the basic rules and terminology of football in English can help you better appreciate and enjoy the game. Whether you are a player or a spectator, football provides excitement and entertainment for all involved. So grab a ball, find a field, and start playing the beautiful game!。

凸轮英文术语

凸轮英文术语Camshaft TerminologyIntroductionThe use of camshafts in various mechanical devices is essential for achieving proper timing and control over the opening and closing of valves. To better understand the intricacies of camshafts, familiarizing oneself with the associated English terminology is necessary. In this article, we will explore and define the key terms related to camshafts in alphabetical order.Base circleThe base circle refers to the smallest diameter of a camshaft where the cam profile has no lift. It acts as a reference point for measuring the total camshaft lift.Cam angleAlso known as the lobe separation angle or LSA, the cam angle refers to the angle between the centerlines of the intake and exhaust lobes. It determines engine performance characteristics, such as idle quality, low-end torque, and high-end power.Cam profileThe cam profile defines the shape and dimensions of the lobe on the camshaft. It determines the valve lift and duration, which directly impact engine performance.DurationThe duration measures the length of time that a valve remains open during the engine's operating cycle. It determines the amount of airflow and fuel that can enter the combustion chamber.FollowerThe follower, also known as a tappet or lifter, is a component that follows the camshaft's profile and transfers its motion to open or close valves in the engine. There are various types, including mechanical, hydraulic, and roller followers.Fuel pump lobeIn some engines, a fuel pump lobe is integrated into the camshaft. This lobe interacts with a fuel pump lever, responsible for supplying fuel to the engine's combustion chamber.Index angleThe index angle refers to the angle at which the camshaft is installed concerning the crankshaft. It determines the precise timing of valve opening and closing events.JournalsJournals are the cylindrical bearing surfaces on the camshaft. These surfaces rotate within the engine block, ensuring smooth operation and reduced friction.LiftThe lift measures the maximum distance that the valve opens off its seat during operation. It directly affects the volume of air and fuel that enters the engine's combustion chamber.OverlapOverlap refers to the period when both the intake and exhaust valves are open simultaneously during a four-stroke engine cycle. It aids in scavenging exhaust gases and improves engine performance.Phase angleThe phase angle describes the rotational position of the camshaft relative to the crankshaft. It determines the timing of valve opening and closing events, which impacts engine performance and efficiency.RampThe ramp refers to the inclined surface on a camshaft lobe that gradually raises and lowers the follower. It allows for smooth valve operation and minimizes wear on the valve train components.Valve timingValve timing refers to the precise opening and closing of valves concerning the engine's piston position. It plays a critical role in optimizing engine performance, fuel efficiency, and emissions.ConclusionMastering the English terminology associated with camshafts is crucial for individuals working in the field of automotive engineering or those with an interest in understanding engine dynamics. By familiarizing ourselveswith these key terms, we can better comprehend the complexities of camshaft design, operation, and their impact on engine performance.。

高速pcb设计与电路板分析课程讲义3

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高速设计分析技术1Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码2高速电路设计趋势Trend towards serial connectivity 向串行连接发展3Parallel I/O Common Clock 并行IO –共同时钟系统Pre-layout simulation for design exploration andpost-layout simulation for verification 可以通过SI前后仿真进行设计 Signal timing 信号时序 Signal noise 信号噪声Undershoot and overshoot 过冲4Parallel I/O Common Clock (继续) 并行IO –共同时钟How to increase data rate? 如何提高数据速率Increase data pin counts 增加管脚 Increase bus clock frequency 增加时钟频率But……但是……Increase data pin counts it's more hard for PCB design (need more space for trace breakout, routing…..) 增加管脚造成PCB设计困难 Increase clock frequency it will reduce timing margin, destroy signal integrity (due to multi-drop top.), restrict data trace length, increase EMI… 增加时钟频率使得时序紧张, 信号完整性问题突出, 走线线长约束严格, 电磁辐射增加…5Parallel I/O Source Synchronous 并行 I/O –源同步系统Provide guidelines for physical layout by sweeping the solution space 可以通过参数扫描分析确定电气约束Measurements for voltage and time specifications and worst case report 得到最坏情况下的信号质量和时序要求 Bus timing analysis 总线时序分析 Slew rate prorating/derating for Setup/Hold Time compensations (DDR2) 考虑边沿速率造成的的建立保持时间的补偿 (DDR2)6Parallel I/O Source Synchronous (继续) 并行 I/O –源同步系统How to increase data rate? 如何提高数据速率Increase bus clock frequency 增加时钟频率 From single strobe to dual strobe 采用读写数据采样时钟 From single end strobe to differential strobe signaling 采用差分时钟But……但是……Increasebusclockfrequencythereisnotheoreticallimitonbuscloc k frequency,buthigherclockfrequencywillcausesignalintegrity p ( p p) depredation(duetomulti‐droptop.) 增加时钟频率使得信号完整性问题突出… Fromsinglestrobetodifferentialstrobeforlesstimingmarginwhiledesignmigratestohighspeed,differentialstrobewillincreaseval idtiming window 采用差分时钟提高速率但是因为速率提高, 时序参数更为紧张7Parallel I/O - Integrating SI with Timing 并行接口分析–综合考虑SI和时序Multiple TopologiesTimingEquationWaveform and Solution SpaceSignal Integrity and Timing Analysis integrated to one solution 信号完整性和时序分析组成一个完整的解决方案8Parallel I/O - Integrating SI with Timing 并行接口分析–综合考虑SI和时序 (继续)Component SpecsA rising edge (when using tDSb and tDHb) must: – Start below VIL_DC – Switch through VIH_AC – Settle above VIH_DC Vin_Meas_R_Low = Vin_Low_DC Vin_Meas_R_High = Vin_High_AC MIN Delay Measured at first crossing of Vin_meas_R_Low MAX Delay Measured at last crossing of Vin_meas_R_HighMin Delay Vin_Meas_R_Low Vin_DC_Low Vin_AC_Low Vref Max Delay Vin_Meas_R_High Vin_AC_High Vin_DC_HighComponent timing is specified under specific loading and measurement conditions 器件时序由特定负载和测量条件构成Timing and signal integrity analysis must be compatible 时序和信号完整性必须兼顾 SI measurements are therefore "normalized" to component timing specs SI相关的测量最终转化为器件的时序规范 Timing Closure occurs when integrated analysis yields acceptable setup/hold margins 可接受的建立/保持时间裕量使时序收敛Vin_AC_High Vin_DC_High Vref Vin_DC_Low Vin_AC_Low"Sim Start time" normalized using reference load specs Switching times based on datasheet setup/hold specs9Serial I/O 串行 I/OInterconnect loss of the channel (entire signal path) 考虑互连损耗Jitter controlled is required due to CDR 控制抖动 Modeling complex drivers and receivers 需要更复杂的器件模型 Stress test the design with LARGE bit streams 要分析大量数据位传输S-parameter simulation (Time domain & Frequency Domain) S-参数分析, 时域和频域分析10Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码11Synchronous Design 同步设计系统Sometimes called "Common Clock" 又叫共同时钟系统 Clocks are distributed from a central point to all of the loads. 时钟信号由同一时钟源发送 Max M operating f ti frequency is a f i function of T ti f Tco, T d S t Tpd, Setup, H ld and Hold, d Clock Skew 最大工作频率由缓冲延时,传输延时,建立,保持时间和时钟偏移决定12Synchronous Data Transfer 数据传输方式1 4Hold32Tco Flight TimeD0 D1 D2D0 D1 D2DrivingReceiving13Setu pClock DriverSynchronous Timing Terminology 时序参数Cycle Time (Tcycle)时钟周期Clock Skew 时钟偏移 Cycle 1 Cycle 2Clock to Output (Tco) 时钟输出延时Clock Jitter14Synchronous Timing Terminology (继续) 时序参数Interconnect Delay (Tpd) 互连传输延时Positive Interconnect Delay (Tpd)Negative Interconnect Delay (Tpd)15Defining TcoTco定义Tco = time from clock rise to Vmeas into test load 从时钟边沿进入器件到数据从器件输出有效的时间(数据输出接测试负载)Clock Clock rises t=0 DinInternal LogicOutput BufferVmeasTco TRL = 50 Ω Load for Tco measurement (from databook)16Components of TcoClock Clock rises t=0 DinTco的组成Internal I t l LogicOutput BufferVmeasTcoRL = 50 Ω Internal delay = from clock External (buffer) delay = how rise to the point where the long the buffer takes to drive the output begins to switch reference load to Vmeas 缓冲器时延内部逻辑时延17Clock JitterClock Driver Cycle 1 Cycle 2时钟抖动Clock Jitter occurs when the clock period varies from one period to the next 考虑周期差抖动Usually caused by PLL instability in the clock driver 通常由锁相环引起 Jitter increases / decreases the clock period period, decreasing the effective clock cycle 抖动减小有效时钟周期18Clock Skew 时钟偏斜Clock t = 0 DriverOccurs when different devices see the clock transition atdifferent times 时钟到达不同器件的时延Increases / decreases the apparent clock cycle. Depending on which devices are driving / receiving 根据 g gt=1D0 D1 D2t=2D0 D1 D2驱动接收不同变化Reduces the effective clock cycle 减小有效时钟周期19内部偏斜和外部偏斜时钟驱动器造成内部偏斜而PCB布线和设计以及外部环境引起的偏斜被称为外而 C 布线和设计以及外部环境引起的偏斜被称为外部偏斜 tSKEW_INTRINSIC = 器件引起的偏斜 tSKEW_EXTRINSIC = PCB + 布线 + 工作环境引起的偏斜 tSKEW = tSKEW_INTRINSIC + tSKEW_EXTRINSIC20内部偏斜 - 输出偏斜 (tSK)单一器件的指定输出之间的偏斜 (JEDEC) 输出偏斜也称为引脚到引脚的偏斜.输出偏斜是同一输出偏斜也称为引脚到引脚的偏斜输出偏斜是同器件上同一跃迁的任何两个输出延时之间的差值21内部偏斜 - 封装偏斜 (tDSK)在相同环境下工作的两个独立器件的任何指定输出之间的传送延时之差也称为器件到器件的偏斜.类似于输出偏斜,只是它用于两个或多个相同的器件22外部偏斜 - 传送延时(tpd)当输出从一个指定的电平改变到另一个电平时,输入和输出电压波形上的指定基准点之间的时间23PCB走线影响时钟偏斜(传送延迟)因素Clock skew is caused by: 原因 variation in the loading between different agents on the bus (CL).负载不一致variation in interconnect characteristics (Z0, τ d ) 互连结构特性 ). Crosstalk 串扰 variation in electrical lengths. What is electrical length?互连电气长度差Clock Driver Z0 , τ dTdrvCL a CL b24TdrvZ0 , τ d建立和保持时间 (Tsetup和Thold)建立时间和保持时间:建立时间(setup time):是指在时钟信号上升沿到来以前,数据稳定不变的时间,如果建立时间不够,数据将不能在这个时钟上升沿被打入; 保持时间(hold time):是指在时钟信号上升沿到来以后,数据稳定不变的时间, 如果保持时间不够,数据同样不能被打入.25同步电路时序分析clk: 时钟驱动器 a: 数据发送器件 b: 数据接收器件 CLOCK(a) @ clk output CLOCK @ clk inputclkCLOCK(b) @ clk outputFROM CORECLK D QCLK D QaCLOCK(a) @ aDATA @ aDATA @ bTO COREbCLOCK(b) @ b26Setup Timing Diagram & Loop Analysis同步电路建立时间分析CLOCK @ clk input CLOCK(a) ( ) @ clk output CLOCK(a) @ a DATA @ a DATA @ b CLOCK(b) @ clk output CLOCK(b) @ b Tcycle Tdrv_clk Tprop_clk Tco Tprop Tmargin Tdrv_clk Tsetup(b)Tprop_clk(b) TjitterTcycle + Tdrv _ clk (b ) + T prop _ clk (b ) T jitter Tsetup Tm arg in T prop Tco T prop _ clk Tdrv _ clk = 027Hold Timing Equation 保持时间分析Uses same clock edge Hold equation 公式同一时钟沿Tdrv _ clk + T prop _ clk + Tco + T prop Tm arg in _ hold Thold T prop _ clk (b ) Tdrv _ clk (b ) = 0Define定义时钟偏斜Clock Delay 传送延迟Tclk ≡ Tdrv _ clk + T prop _ clk Clock Skew 时钟偏斜Tskew ≡ Tclk (b ) Tclk (a )28Simplify Timing Equations 公式简化Setup margin = Tcycle - Tco_max - Tpd_max - Tsetup + Tsetup_skew SETUP @ Maximum Data, Minimum Clock Hold margin = Tco_min + Tpd_min - Thold - Thold_skew HOLD @ Minimum Data,Maximum Clock29仿真波形分析时序30仿真波形分析时序 (继续)31Common Clock Bus Example 案例Intel Pentium-Pro reference design Pentium-Pro 参考设计Processor/Chipset Bus (GTL+, 66 MHz) GTL + 66MHz总线 Intel GTL+ Design Guidelines 参考英特尔GTL + 设计指导32Defining Device Timing 定义器件时序参数Pentium Pro Timings taken from "AC (dynamic) p Specifications" sections of Intel datasheets 时序参数参考器件手册 "AC Specifications" 部分 Important parameters 重要参数Clock → Data Valid for GTL+ Bus Tco时间 Setup / Hold requirements for GTL+ signals440FX (timings from 440LX)需要的建立保持时间PLL Jitter (if spec'd)锁相环抖动33Determining Flight Times 计算走线需要的飞行时间Device Timing InformationTcom in Tcom ax Setup Hold Pentium Pro 0.55 ns 4.40 ns 2.20 ns 0.45 ns 440FX 1.25 ns 7.25 ns 5.00 ns 0.00 nsBudgeted Parameters Clock Skew Clock Jitter Crosstalk Clock Freq. Clock Period 0.2 ns 0.4 ns 0.4 ns 66 MHz 15.15 ns Pentium Pro to 440FXTflightmax = ClockPeriod Tco max - Skew - Jitter - Crosstalk - Receiver(Setup) 15.15 ns 4.40 ns 0.20 ns 0.40 ns 0.40 ns 5.00ns 4.75 Tflightmin = Receiver(Hold) - Tco min + Skew + Jitter + Crosstalk 0.00 ns 0.55 ns 0.20 ns 0.40 ns 0.40 ns 0.45 ns 440FX to Pentium ProTflightmax = ClockPeriod Tco max - Skew - Jitter - Crosstalk - Receiver(Setup) 15.15 ns 7.25 ns 0.20 ns 0.40 ns 0.40 ns 2.20 ns 4.70 ns Tflightmin = Receiver(Hold) - Tco min + Skew + Jitter Crosstalk 0.45 ns 1.25 ns 0.20 ns 0.40 ns 0.40 ns 0.20 nsTflightmax = 4.70 ns Tflightmin = 0.45 ns34Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码35Source Synchronous Design 源同步设计Clock and Data originate at the same source 时钟和数据发自同一源 Originally called Clock forwarding Clock and Data are Correlated 时钟和数据信号相关 They are at the same process corner 相同条件 Temperature, voltage variations effect both the same way 相同影响 Major issue is Delay Variations between DATA and CLOCK 主要因素 Package 封装 PCB etch 电路板蚀刻Loading 负载 On-die Variations 片上参数 Crosstalk 串扰 ISI 码间干扰36Source Synchronous Data Transfer 数据传输方式STB D0 D1 D2 STB D0 D1 D2 Data / STB are synchronized at the driver 数据时钟在发送端保持同步 Device speed (fast, slow) is irrelevant since Data & STB are supplied by the same device 器件本身速率变化不重要 The significant issue is the gaccumulated skew between Data & STB as the signals travel between devices 数据时钟之间的偏斜是主要问题Driving Di iReceiving R i i37Limiting Factors for Source Synchronous Bus Speeds 影响速度的因素Design Factor Bus Length Device delay (Tco) Receiver setup / hold Jitter Differences in device p (fast, slow) ) speed ( Timing Requirement No longer applies No longer applies Still applies Dependes No longer appliesCritical factor is minimizing skew 关键是减小偏斜38Source Synchronous Terminology 时序参数Cycle time vs. Data RateStrobe vs. ClockDelay skew 延时偏移Correlated vs. Uncorrelated Etch39DLL Concept锁延时环D0MUX QD L LD1DQ0CDelay Line(Delay=C)Delay=ACLKDD0MUX QD1DQ1CPhase DetectorDelay Control. . .DQiD0A + BDelayD1MUX QCModelDelay=B40Data Valid Window (数据有效窗口)Conventional flight-time measurements cannot be used 传统的飞行时间测量不再适用 Valid time window concept 应用有效窗口 Calculate all the consumed timing and the timing margin 计算所有的消耗时间和需要的时序裕量Ske wtD Q S QD a ta V a lidt D VSke wtD Q S QA ll D Q a n d D Q S (a t D D R o u tp u ts ) A ll D Q a n d D Q S(a t C P U in p u ts )Skew'tD Q S Q + B o a rd S ke wD a ta V a lid ' tD V -B o a rd S ke wS kew'tD Q S Q + B o a rd S ke w41Derive Source Synchronous Timing Equations 时序计算公式 Setup margin = Tclk_min - Tdata_max -Tdelay_skew_max - Tsetup SETUP @ Maximum Data, Minimum Clock Hold margin = Tdata_rate + Tdata_min + Tdelay_skew_min - Tclk_max - Tcycle_to_cycle_jitter – Thold HOLD @ Minimum Data, Maximum Clock42Specialties for DDR2 - SSTL DDR2一些特性– SSTL电平SSTLVDDQVIH(ac)VIH(dc)VREFVIL(dc) VIL(ac)VSS43SSTL _1844Threshold 电平门限45过冲和时序测量Max Delay (Setup)1V/ns Min Delay (Hold)1.5V/ns 1 5V/nsMin, Max Delay{ΔT46DDR2 Slew Rate Derating 边沿斜率补偿Baseline setup/hold requirements are based on specific voltage and slew rate conditions 基准的建立/保持时间要求基于特定的翻转条件 System slew rates rarely conform to measurement conditions 系统工作的翻转条件很少与定义的基准的建立/保持时间的测试条件一致Loading can vary widely wit47hin the same system 负载变化DDR2 slew-rate derating defines adjustments to setup/hold specs based on actual slew rates of input signals 边沿斜率补偿可以按实际设计调整建立/保持时间DiePackageChip CorePinPad Core47Slew rate 边沿斜率计算48Applying Slew Rate Data 根据斜率查表得到建立保持时间补偿DQ DDR2 derating tables list adjustments to setup / hold timing 建立保持时间补偿表1.5V/nsDQS1.8V/nsSlew rates are measured for each signal independently 边沿斜率对每个信号都要计算 The timing adjustment is read from the table 查表得到时间量调整 Slew rates must be measured Sl t tb d for each edge of each signal 边沿斜率对每个信号每个边沿都要测量49A DDR2 Example DDR2例子AddressCLK ADDR/CMDControlClock/StrobeCTRL DATA DQSRead DataWrite DataMultiple timing relationships 多种时序关系 Each timing relationship involves multiple net classes 每一种时序关系包含多种网络类型 Each net class must be analyzed under multiple operating conditions 每一种网络必须在多种条件下分析Successful design ensures all timing requirements are met under all operating conditions 成功的设计确保所有的时序在所有条件下得到满足ControllerMemory50Real Waveform Processing 实际波形测量处理Let's consider a case where the controller writes data to memory 数据写入内存数据写内存DQ DQS is operated differentially 差分DQS信号Differential rising edge 差分边沿Rising DQS Falling DQS# DQS正端 DQS# 负端DQSRising edge on DQInterconnect delays are to be I t td l t b measured for DQ and DQS signals 互连延迟测量51DQ Signals 数据信号Quality 质量 A rising edge must: 上升沿Start below VIL_DC 从VIL_DC开始 Switch through VIH_AC 跳变到 VIH_AC上 VIH AC上 Settle above VIH_DC 在VIH_DC上保持稳定Timing 时序 MIN delay measured at first crossing of VIL_DC 最小延时测量点在波形第一次穿过VIL_DC的点 Used to compute hold margin 用来计算保持时间 JESD79-2C, page 96, note 21SI ViewMAX delay measured at first crossing of VIH_AC 最大延时测量点在波形第一次穿过VIH_AC的点 Used to compute setup margin 用来计算建立时间 JESD79-2C, page 96, note 20Timing Spec View52Differential DQS Signals 差分时钟信号Quality 质量 The differential voltage swing must be at least VID(ac) 差分信号必须达到正负VID(ac)电平 Must account for duty cycle distortion and Jitter 必须考虑时钟的失真和抖动 Timing MIN, MIN MAX d l delays are measured at d t crossing of DQS and DQS# 延时测量点在差分正负波形的交接点JESD79-2C, page 96, notes 20 & 21SI ViewTiming Spec View53DDR3 - Time Beyond VAC (TVAC) DDR3设计 - TVACSignals must remain above / below VIH/IL(ac) for aspecified time to ensure a valid transition 信号必须在VIH/IL(ac)之上保持一段时间 This time period, TVAC, is slew rate dependent TVAC也是随信号边沿斜率而不同 Signals must satisfy the TVAC requirement even if setup time is negative (signal has not reached VIH/IL(ac) before clock transition) 即使需要的建立时间为负信号也要满足TVAC时间Ref: JESD79-3A, Page 161, Table 71Ref: JESD79-3A, Page 162, Figure 10154"Fly By" ADDCMD / CLK 串行链路的地址/时钟ControllerCLK, CLK_N ADDRCMD / CTRLEnd-terminated daisy-chain topology for ADDCMD/CTRL and CK/CK# signals 菊花链结构的地址时钟走线 Address valid windows at memory inputs are larger, but staggered in time 地址总线的有效窗口台阶状的时延分布. . .55DDR3 Signal Integrity / Timing Analysis SI/时序分析READ WRITEL3DQ DQSL2DQ DQSL1DQ DQSL0DQ DQSADDRCLKCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQ56CK / DQS Relationship 系统时钟和数据采样时钟关系Rising edge of CK has required relationship to both edges of DQS 系统时钟和数据采样时钟的上升沿必须保持一定的时间关系 Relationship must be maintained at each SDRAM 每一个内存芯片都要保证Ref: JESD79-3A, Page 63, Figure 38Ref: JESD79-3A, Page 151, Table 6757CK/CK# to DQS (and therefore DQ) 系统时钟和数据总线ControllerCLK, CLK# ADDR DQS, DQS# DQ<0:N> DQS, DQS# DQ<0:N>Matched length routingMust maintain CK/DQS relationship at each SDRAM 每个内存芯片的系统时钟和数据采样时钟的时序关系都要保证CLK ADDR DQS DQ CLK ADDR DQS DQ 58CK/CK# to DQS (and therefore DQ) 系统时钟和数据总线 (继续)ControllerCLK, CLK# ADDR DQS, DQS# DQ<0:N> DQS, DQS# DQ<0:N>Matched length routingMust adjust DQS timing for each lane to j Q g maintain CK/DQS relationship at SDRAM 必须调整DQS时序 (Write leveling) DQ shifts must follow DQS shifts DQ随着QDS移动 Controllers can adjust DQ/DQS output timing to simplify PCB routing 控制器可以调节DQ/DQS输出时序CLK ADDR DQS DQ CLK ADDR DQS DQ59DQS/CLK AnalysisL3DQ DQSL2DQ DQSL1DQ DQSL0DQ DQSADDRCLKCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQ60Adjusting DQ/DQS Timing 调节DQ/DQS输出时序DQ/DQS aligned with CK/CK# on a per-byte lane basis 对每一路数据信号都要保持DQ/DQS与系统时钟的关系对每路数据信号都要保持DQ/DQS与系统时钟的关系 Write LevelingDDR3 memory devices can report on alignment of received CK/DQS signals DDR3内存报告CK/DQS对齐信息给控制器Controllers can utilize this information to optimizeCLK/DQS/DQ output timing for each byte lane 控制器可以根据这个信息调整DQ/DQS输出时序 Controllers compensate for skew in signals returned from memory on a per-byte line basis 控制器可以补偿部分时序偏差Read Leveling61Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码62Serial Link Design 高速串行设计63Serial I/O 高速串行接口Jitter controlled is required due to CDR 抖动控制 Point to point topology 点对点拓扑 Pre/De-emphasis for driver end and equalization at receiver end due to l t loss in l i long i t interconnect 预加重和均衡电路设计改善损耗影响 tHigh-Performance serial signaling implemented with differential signaling technology 差分走线Figure 7.11 Generalized SERDES serial connectionparallel to serial conversion parallel data bus8serial linkserial to parallel conversion SERDES8SERDES PLLrecovered parallel dataPLLbit clock64Differential Impedance 差分阻抗Odd O ModeZ oo =Ls Lm C s + CmLs + Lm Cs CmEven ModeZ oe =Z diff = 2 Z ooZ comm =1 Z oe 265Loosely & Tightly Coupled Diff Pair 松耦合和紧耦合Loosely Coupled DP 松耦合Differential Impedance depends only on single TL. Easy to do the layout, distance changes don't affect the differential impedance. y , g p 易于控制阻抗和布线Tightly Coupled DP 紧耦合High layout density, lower the cost. 布线密度大Differential noise is smaller than Loosely Coupled DP. 差分噪声小 Common noise can be easily controlled by using common mode choke. 可以用共模扼流圈抑制共模噪声 Can minimize the influences of discontinuity in the ground plane current return pass. 可以减小不完整参考平面影响66PCB structures that introduce Skew 差分走线偏差An escape from a BGA or connector pins introduces skew BGA 出线造成偏差This is an p example of skew compensation 一个控制偏差的例子67Broadside&Edge Coupled Diff Pair 上下面耦合和边沿耦合Broadside stripline offers better routing density but the impedance variation is larger due to manufacturing variations and the tight coupling of traces on different layers 上下面耦合提高布线密度但是阻抗难于控制 Edge-coupled stripline has the largest attenuation constant 边沿耦合带状线具有最大的衰减常数 Edge-coupled microstrip line has smallest propagationconstants 边沿耦合微带线具有最小的传播常数68Via Effect 过孔Microstripline viaStripline via69Via Effect signal via couple with power/ground via 换层孔旁加地孔Power / ground vias closed to signal via which will play a role for return current path 信号孔旁的地孔可以提供回流路径Layer 2 and layer3 have same voltage attribute70Right Angle Corner 直角走线Capacitive effect 电容效果 Un continuous impedance 阻抗不连续 Attenuate high frequency signals 高频信号衰减Zo Zo Ccorner45o bends, round and chamfered bends exhibit reduced effects 45o或圆角减小反射71Bends introduce skew 拐角造成偏差Back to back bends compensate for skew 返回拐角控制偏差 72线宽影响73Connector 连接器Connector – to be or not to be? 是否需要 Can you afford 2 connectors (in BP topology)? 添加俩个连接器互连质量是否能够满足要求 Sh ld you fi d a b Should find better connector? 是否有更好的连接器 ?74Measurements of Gbps Signals -Connector Via Discontinuity 连接器造成的阻抗不连续75Cross talk2MM connector列列列列列列列列 1 2 3 4 5 6 7 8连接器串扰分析2MM连接器屏蔽行 A 行 B 行 C 行 D 行 E 行 F 行 G 行 H 屏蔽地地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地+ - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地+ - 地仿真上升沿为150PS,摆幅为400MV的LVDS信号激励,远端最大串扰85MV76Cross talk连接器串扰分析 (继续)HS3连接器HS3 connector仿真上升沿为150PS,摆幅为400MV的LVDS信号激励,远端最大串扰12MV77Pre-Emphasis 预加重 (I)Time and Frequency Domain of Square wave (50% duty cycle) 观察50%占空比方波的时域频域 A finite-edge-rate square wavewith 50% duty cycle contains harmonic f h i frequency components at (frequency), 3*(frequency), t t (f ) 3*(f ) 5*(frequency), etc. 50%占空比方波的频域只包含奇次谐波Time DomainFrequency Domain78Pre-Emphasis 预加重(II)A wave with 25%/75% Duty Cycle 观察占空比25%/75%的波形This now changes the distribution of energy in the frequency "bins" 频谱分布变化了Time DomainFrequency Domain79Pre-Emphasis 预加重 (III)Combine the above two waveforms 上面两个波形叠加观察Time DomainFrequency DomainBy boosting the spectral distribution at the harmonics, you can reduce loss effects through pre-emphasis 增强了奇次谐波的能量分布, 改善损耗影响 Key Concept of Pre-emphasis: redistributing the energy of the driven waveform in the frequency domain to combat losses at certain frequencies, by selectively increasing the time domain drive strength 增强了某些频率点的能量, 可以有选择的提高时域驱动能力80Pre-Emphasis预加重(IV)High-frequencyLoss profile of lengthy backplane PCB trace 损耗曲线观察Total loss (dB) ( losses edge degradationFrequency (Hz)Xfer Function of pre-emphasis signal C = Sum of trace loss and pre-emphasis signalTotal loss (dB)Frequency (Hz)Diagrams courtesy Mindspeed,/io_shoot_mindspeed.pdfTotal loss (dB)Frequency (Hz)81Pre-Emphasis预加重 (V)Pre-emphasis not limited to "one boost"不仅限于" one boost" Multi tap Multi-tap enables strengthening of several frequencies to different levels 多抽头增强了更多频率点的能量 Time DomainFrequency Domain82Complex-IO Devices IO接口Pre-emphasis预加重/De-emphasis去加重Emphasis (t) = Input (t 1) (t-1) Main (+ & -) Input stimulus pattern 1000 1000 0111 0111 TX+ Pad 1000 1000 TX- Pad 0111 0111 Emphasis X011 1011 stimulus ti l X100 0100 patternin concert in oppositionBoost (+ & -)83测试案例A Pre-emphasis example. 预加重测试例子84Inter-Symbol Interference (ISI) 码间干扰1Data bit is sent 数据位传输 Before the previous bit is received, the next bit is sent 在前一位接收前, 下一位已发出When each bit reaches the end of the net, some portion will be reflected if not perfectly terminated 阻抗不匹配会产生反射Reflections propagate back towards (and reflect off of) the driver and can interfere with subsequent bits, especially if many receivers are on the line 反射会影响下面正在传输的数据位 Signal Reflection23485Interconnect Storage Potential 互连能量存储Unique for each interconnect 每个互连结构都存在Measures how long a bit's energy stays in link 测试一个bit 的能量可以持续多久 Can be measured from pulse response 可以通过脉冲响应得到 Directly related to how many bits you need to simulate 指导需要多少位传输能够看到全部情况ISP86Process1.步骤Determine the Interconnect's Storage Potential (ISP) 确定ISP the time for a pulse to decay 脉冲响应的衰减时间 2. Calculate the relevant preamble size (bit times) within the ISP 计算ISP时间内信号可以传输多少位 preamble = ISP / bit_time bit variations prior to the preamble are not likely to affect eye height 在之外的数据位不会影响现在传输的数据 3. Determine how many bits may need to be run to address preamblevariations 估算需要分析多少位 #bits = (preamble) * 2 (preamble)= (ISP *Gbps)*2 (ISP*Gbps) encoding schemes may reduce thi value 特定的编码可以大大减小需要的位 di h d this l 数 4. Simulate or measure this # bits in your channel 分析或测试足够的数据位87Stress Test the Design with LARGE Bit Streams 设计需要分析足够多位数Examine channel's Interconnect Storage Potential (ISP) for insight on length of required bit stream 分析ISP 造成的ISI 影响 q 分析造成的影响 Run high-capacity channel simulations, inspect eye diagrams 观察眼图 Examine the jitter 得到抖动 Examine the bit error rate 得到误码率88CA Mathematical Method 通道分析技术BIT PATTERN FFT iFFT FFTNOT typical circuit simulation 不是常规电路分析方法Requires characterization of interconnect (its "fingerprint") 需要先分析互连的脉冲响应 Techniques have been used in other disciplines for years 这个技术已经应用于其他方面 But new to digital PCB signal integrity 但是对板级分析来说是新引进的分析技术 89Time domain incorporates with frequency domain analysis Frequency domain 频域分析S21 = insertion loss Signal energy dissipated during the transmission, lower value imply higher loss S21 传输损耗 S11 = return loss Reflected i R fl t d signal d t i l due to impedance d Mismatch, lower value imply smaller reflection better SI S11 反射损耗90BER (Bit error rate) 误码率91Bath Tub浴盆曲线928b/10b Encoding 8b/10b编码8b/10b 8b/10b编码 Input: A standard 8 bit long word 输入: 8位数据 Output: 10 bit long data block 输出: 10位数据Originated with IBM 起源于IBM Patent: Widmer & Franaszek, September 1983 Standard means of encoding data in SerDes 串行传输编码标准 GbE, PCIe, S-ATA, etc10 bit 8 bit control938b/10b EncoderData SerializerSerial InterfacePurpose目的限制码型8b/10b limits data pattern permutationsInput: 256 possible data or 256 possible control 输入: 256种可能 Output: 1024 possible data or 1024 possible control 输出:1024种可能 512 permitted data (256 positive, 256 negative) 实际允许512种 24 permitted control (12 positive, 12 negative) 24种允许控制码型Limitation based on DC balance好的直流偏置Consecutive, identical bits tightly bounded, only three variations in any 10 bit block are allowed. 任一10位数据, 只允许下面三种连续传输码码型里有5个1和5个0 Five "1" and five "0" Four "1" and six "0" 码型里有4个1和6个0 码型里有6个1和4个0 Six "1" and four "0"For example,举例1 0 1 0 1 0 1 0 1 0: VALID – Five "1" and five "0" 1 0 1 0 0 0 1 0 1 0 0 0: INVALID – Seven "0" and three "1"94Purpose Cont'd目的(继续)Assures DC balance of interface 直流偏置Examples – imagine 1000 cycles of the following: 1000位码型 1 0 1 0 1 0 1 0 1 0: common mode is 0.5*Swing 是数据波动电压的一半是数据波动电压的半 0 1 1 1 1 1 1 1 1 0: common mode "drifts up" 会偏上 1 0 0 0 0 0 0 1 0 0: common mode "drifts down" 会偏下 Many SerDes buses limit the common mode. 高速串行传输对共模电压有要求DC Balance vs. Input Thresholds No Balance vs. Thresholds 95Key Concepts关键点Disparity 不均等性 What is the "trend" of the data bits so far? 描述数据趋势More "1" than "0"? Disparity is positive 1比0多, 不均等性为正 More "0" than "1"? Disparity is negative 0比1多, 不均等性为负 Otherwise, neutral disparity 否则为0All input patterns have "twin" outputs 每种输入对应正负两种输出 Example: 0 0 0 0 0 0 0 0 Positive: 1001110100 Negative: 0110001011 Disparity changes to preserve DC balance 根据不均等性结果控制输出码型保证直流均衡 If incoming disparity is positive, negative output used 不均等性为正, 输出负码型 If incoming disparity is negative, positive output used 不均等性为负, 输出正码型96Implementation应用8b/10b actually 3b/4b + 5b/6b 实际是3b/4b + 5b/6b 编码Previous data stream's disparity need be taken into account 前面数据位的不均等性要考虑进去 5b/6b output disparity affects 3b/4b disparity 5b/6b编码输出的不均等性影响3b/4b编码的不均等性 This ensures no more than 5 consecutive identical bits 保证不超过5位相同位传输6 bit Error and Disp. Check Serial Interface5b/6b Encoder 8 bit 3b/4b Encoder control4 bitData D t Serializer97Input Pattern Name输入码型名称Input pattern name is used to describe the input 8 bit data 描述8位输入码 Zx.y, where Z is control or data (D for Data, K for control), x.y is input bit stream Zx.y形式, Z位D或K, 表示数据或控制码, x.y表述输入码流 Bits [4:0] (E:A) are converted to decimal 低五位用十进制表示 Example: 00111 for (E:A) -> 7 Therefore, 00111 as data would be D7.x Bits [7:5] (H:F) are converted to decimal and added after "." 高三位用十进制表示, 放在码型名称的"."后面 Example: 001 for (H:F) -> 1 Therefore, 00100111 -> D7.1 Favorite patterns for simulation 仿真分析常用码型 K28.5: 10111100, high ISI D10.5: 10101010, highest frequency D11.4 + D3.0: 1000101100000011, "lone-bit" worst-case ISI possible98Example举例99。

AD9122器件手册

Dual, 16-Bit, 1230 MSPS,TxDAC+® Digital-to-Analog ConverterAD9122 Rev. AInformation furnished by Analresponsibility is assumed by Ana rights of third parties that may re license is granted by implication T rademarks and registered trad MA 02062-9106, U.S.A. Inc. All rights reserved.og Devices is believed to be accurate and reliable. However, nolog Devices for its use, nor for any infringements of patents or other sult from its use. Specifications subject to change without notice. No or otherwise under any patent or patent rights of Analog Devices. emarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, Tel: 781.329.4700Fax: 781.461.3113 ©2010 Analog Devices,FEATURESFlexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, R L = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidthGain and phase adjustment for sideband suppression Multiple chip synchronization interfacesHigh performance, low noise PLL clock multiplierDigital inverse sinc filterLow power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full operating conditions72-lead, exposed paddle LFCSPAPPLICATIONSWireless infrastructureW-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTEDigital high or low IF synthesisTransmit diversityWideband communications: LMDS/MMDS, point-to-point GENERAL DESCRIPTIONThe AD9122 is a dual 16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS1.Ultralow noise and intermodulation distortion (IMD)enable high quality synthesis of wideband signals frombaseband to high intermediate frequencies.2. A proprietary DAC output switching technique enhancesdynamic performance.3.The current outputs are easily configured for varioussingle-ended or differential circuit topologies.4.Flexible LVDS digital interface allows the standard 32-wirebus to be reduced to ½ or ¼ of the width.TYPICAL SIGNAL CHAINCOMPLEX BASEBANDDC COMPLEX IFf IFRFLO – f IF8281-1 Figure 1.AD9122Rev. A | Page 2 of 60TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 6 AC Specifications .......................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Differences Between the AD9122R1 and AD9122R2 ............... 18 Theory of Operation ...................................................................... 19 Serial Port Operation ................................................................. 19 Data Format ................................................................................ 19 Serial Port Pin Descriptions ...................................................... 19 Serial Port Options ..................................................................... 20 Device Configuration Register Map and Descriptions ......... 21 LVDS Input Data Ports .................................................................. 33 Word Interface Mode ................................................................. 33 Byte Interface Mode ................................................................... 33 Nibble Interface Mode ............................................................... 33 FIFO Operation .......................................................................... 33 Interface Timing ......................................................................... 35 Digital Datapath .............................................................................. 37 Premodulation ............................................................................ 37 Interpolation Filters ................................................................... 37 NCO Modulation ....................................................................... 40 Datapath Configuration ............................................................ 40 Determining Interpolation Filter Modes ................................ 41 Datapath Configuration Example ............................................ 42 Data Rates vs. Interpolation Modes ......................................... 43 Coarse Modulation Mixing Sequences .................................... 43 Quadrature Phase Correction ................................................... 44 DC Offset Correction ................................................................ 44 Inverse Sinc Filter ....................................................................... 44 DAC Input Clock Configurations ................................................ 45 DAC Input Clock Configurations ............................................ 45 Analog Outputs............................................................................... 47 Transmit DAC Operation .......................................................... 47 Auxiliary DAC Operation ......................................................... 48 Baseband Filter Implementation .............................................. 49 Driving the ADL5375-15 .......................................................... 49 Reducing LO Leakage and Unwanted Sidebands .................. 50 Device Power Dissipation .............................................................. 51 Temperature Sensor ................................................................... 52 Multichip Synchronization ............................................................ 53 Synchronization with Clock Multiplication ............................... 53 Synchronization with Direct Clocking .................................... 54 Data Rate Mode Synchronization ............................................ 54 FIFO Rate Mode Synchronization ........................................... 55 Additional Synchronization Features ...................................... 55 Interrupt Request Operation ........................................................ 57 Interrupt Service Routine .......................................................... 57 Interface Timing Validation .......................................................... 58 SED Operation ............................................................................ 58 SED Example .............................................................................. 58 Example Start-Up Routine ........................................................ 59 Outline Dimensions ....................................................................... 60 Ordering Guide .. (60)AD9122Rev. A | Page 3 of 60REVISION HISTORY3/10—Rev. 0 to Rev. AChanges to Reflect Differences Between R1 and R2Silicon................................................................................... Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Table 5 ............................................................................ 7 Change to IOVDD Rating in Table 6 .............................................. 8 Changes to Table 8 ............................................................................ 9 Changes to Figure 10 to Figure 15 ................................................ 12 Added Differences Between the AD9122R1 and AD9122R2 Section, Added Figure 36 and Figure 37; RenumberedSequentially ...................................................................................... 18 Changes to Table 10 ........................................................................ 21 Changes to Table 11 ........................................................................ 23 Changes to FIFO Operation Section ............................................ 33 Changes to Resettling the FIFO Section and Replaced Table 13; Renumbered Sequentially; Added Serial Port Initiated FIFO Reset Section, and Added FRAME Initiated Relative FIFOReset Section .................................................................................... 34 Added FRAME Initiated Absolute FIFO Reset Section andReplaced Table 14 ............................................................................ 35 Changes to Figure 54 ...................................................................... 38 Changes to Table 18 ........................................................................ 39 Changes to SED Example Section ................................................. 58 Added Example Start-Up Routine Section .................................. 59 9/09—Revision 0: Initial VersionAD9122Rev. A | Page 4 of 60FUNCTIONAL BLOCK DIAGRAMD15P—D15ND0P—D0NIOUT1P IOUT1NIOUT2P IOUT2NFSADJREFIO DCI FRAME08281-002Figure 2. AD9122 Functional Block DiagramAD9122Rev. A | Page 5 of 60SPECIFICATIONSDC SPECIFICATIONST MIN to T MAX , AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 =1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1.Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR Full-Scale Output Current 18.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V POWER CONSUMPTION 2× Mode, f DAC = 491.22 MSPS, IF = 10 MHz, PLL Off 834 mW 2× Mode, f DAC = 491.22 MSPS, IF = 10 MHz, PLL On 913 mW 8× Mode, f DAC = 800 MSPS, IF = 10 MHz, PLL Off 1135 1241 mWAVDD33 55 57 mA CVDD18 85 90 mA DVDD18 444 495 mA Power-Down Mode (Register 0x01 = 0xF1) 6.5 18.8 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V OPERATING RANGE −40 +25 +85 °C1Based on a 10 kΩ external resistor.AD9122Rev. A | Page 6 of 60DIGITAL SPECIFICATIONST MIN to T MAX , AVDD33 = 1.8 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted.1LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.DIGITAL INPUT DATA TIMING SPECIFICATIONSTable 3.Parameter Min Typ Max UnitLATENCY (DACCLK Cycles) 1× Interpolation (With or Without Modulation) 64 Cycles 2× Interpolation (With or Without Modulation) 135 Cycles 4× Interpolation (With or Without Modulation) 292 Cycles 8× Interpolation (With or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Power-Up Time 260 msAD9122Rev. A | Page 7 of 60AC SPECIFICATIONST MIN to T MAX , AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4.ParameterMin Typ Max UnitSPURIOUS-FREE DYNAMIC RANGE (SFDR) f DAC = 100 MSPS, f OUT = 20 MHz 78 dBc f DAC = 200 MSPS, f OUT = 50 MHz 80 dBc f DAC = 400 MSPS, f OUT = 70 MHz 69 dBc f DAC = 800 MSPS, f OUT = 70 MHz72 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) f DAC = 200 MSPS, f OUT = 50 MHz 84 dBc f DAC = 400 MSPS, f OUT = 60 MHz 86 dBc f DAC = 400 MSPS, f OUT = 80 MHz 84 dBc f DAC = 800 MSPS, f OUT = 100 MHz81 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f DAC = 200 MSPS, f OUT = 80 MHz −162 dBm/Hz f DAC = 400 MSPS, f OUT = 80 MHz −163 dBm/Hz f DAC = 800 MSPS, f OUT = 80 MHz−164 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f DAC = 491.52 MSPS, f OUT = 10 MHz 84 dBc f DAC = 491.52 MSPS, f OUT = 122.88 MHz 82 dBc f DAC = 983.04 MSPS, f OUT = 122.88 MHz 83 dBc W-CDMA SECOND ACLR, SINGLE CARRIER f DAC = 491.52 MSPS, f OUT = 10 MHz 88 dBc f DAC = 491.52 MSPS, f OUT = 122.88 MHz 86 dBc f DAC = 983.04 MSPS, f OUT = 122.88 MHz88dBcTable 5. Interface SpeedsBus Width Interpolation Factorf BUS (Mbps)1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 5% Nibble (4 Bits) 1×1100 1200 1230 2× (HB1) 1100 1200 1230 2× (HB2) 1100 1200 1230 4× 1100 1200 1230 8× 1100 1200 1230 Byte (8 Bits) 1×1100 1200 1230 2× (HB1) 1100 1200 1230 2× (HB2) 1100 1200 1230 4× 1100 1200 1230 8× 550 600 615 Word (16 Bits) 1×1100 1200 1230 2× (HB1) 900 1000 1000 2× (HB2) 1100 1200 1230 4× 550 600 615 8×275 300 307.5AD9122Rev. A | Page 8 of 60ABSOLUTE MAXIMUM RATINGSTHERMAL RESISTANCEThe exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead, LFCSP . The EPAD performs as an electrical and thermal connection to the board.Typical θJA , θJB , and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing θJA and θJB . Table 7. Thermal ResistancePackage θJA θJB θJC Unit Conditions 72-Lead LFCSP_VQ 20.7 10.9 1.1 °C/W EPAD solderedESD CAUTIONStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.AD9122Rev. A | Page 9 of 6008281-003D 11P D 11N D 10P D 10N D 9P D 9N D 8P D 8N D C I D C I D V D D 18D V S D 7P D 7N D 6P D 6N D 5P D 5N PIN CONFIGURATION AND FUNCTION DESCRIPTIONS12345678910111213141516CVDD18DACCLKP DACCLKNCVSS FRAMEP FRAMENIRQ D15P D15N NC IOVDD DVDD18D14P D14N D13P D13N 17D12P 18D12N 19202122232425262728293031323334P N S 3536545352515049484746454443424140393837RESET CS SCLK SDIO SDO DVDD18D0N D0P D1N D1P DVSS DVDD18D2N D2P D3N D3P D4N D4P727170696867666564636261605958575655C VD D 18C V D D 18REF C L K P R E F C L K N A V D D 33I O U T 1P I O U T 1N A V D D 33A V S S F S A D J R E F I O A V S S A V D D 33I O U T 2N I O U T 2P A V D D 33A V S S NCNOTES1. NC = NO CONNECT.2. EXPOSED PAD MUST BE CONNECTED TO AVSS.Figure 3. Pin ConfigurationAD9122Rev. A | Page 10 of 60AD9122050100150200250300350400450f OUT (MHz)TYPICAL PERFORMANCE CHARACTERISTICS0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c)08281-10150100150200250300350400450f OUT (MHz)Figure 4. Harmonics vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c )08281-10208281-1030–10–20–30–40–50–60–70–80–90–100050100150200250300350400450H A R M O N I C S (d B c )f OUT(MHz)08281-1040–10–20–30–40–50–60–70–80–90–10050100150200250300350400450H A R M O N I C S (d B c )f OUT (MHz)Figure 7. Second Harmonic vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC= 20 mA08281-1050–10–20–30–40–50–60–70–80–90–10050100150200250300350400450H A R M O N I C S (d B c )f OUT (MHz)Figure 5. Harmonics vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mAFigure 8. Third Harmonic vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC = 20 mA0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c )100200300400500600700f OUT (MHz)08281-106Figure 6. Harmonics vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA Figure 9. Second Harmonic vs. f OUT over f SC , 2× Interpolation,f DATA = 400 MSPS, Digital Scale = 0 dBFSAD9122–69–70–71–72–73–74–75–77H I G H E S T D I G I T A L S P U R (d B c )–78–79050100150200250300350400450f OUT (MHz)–7608281-10708281-110START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 500.0MHzSWEEP 6.017s (601 PTS)08281-111START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 800.0MHzSWEEP 9.634s (601 PTS)Figure 10. Highest Digital Spur vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA–60–65–70–75–80–85H I G H E S T D I G I T A L S P U R (d B c )050100150200250300350400450f OUT (MHz)08281-108Figure 11. Highest Digital Spur vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA–60–90–95–85–80–75–70–65H I G H E S T D I G I T A L S P U R (d B c )010*******400500600700f OUT (MHz)08281-109Figure 12. Highest Digital Spur vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mAFigure 13. 2× Interpolation, Single-Tone Spectrum, f DATA = 250 MSPS,f OUT= 101 MHzFigure 14. 4× Interpolation, Single-Tone Spectrum, f DATA = 200 MSPS,f OUT = 151 MHz08281-START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 800.0MHzSWEEP 9.634s (601 PTS)112Figure 15. 8× Interpolation, Single-Tone Spectrum, f DATA = 100 MSPS,f OUT = 131 MHzAD91220–90–80–70–60–50–40–30–20–10I M D (d B c )050100150200250300350400450f OUT (MHz)308281-11Figure 16. IMD vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–80–70–60–50–40–30–20–10–90I M D (d B c )050100150200250300350400450f OUT (MHz)408281-11Figure 17. IMD vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–80–70–60–50–40–30–20–10I M D (d B c )–100–90050100150200250300350400450f OUT(MHz)08281-115Figure 18. IMD vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–90–80–70–60–50–40–30–20–10050100150200250300350400450I M D (d B c )f OUT(MHz)08281-116Figure 19. IMD vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC = 20 mA–50–85–80–75–70–65–60–55050100150200250300350400450I M D (d B c )f OUT (MHz)08281-117Figure 20. IMD vs. f OUT over f SC , 2× Interpolation, f DATA = 400 MSPS,Digital Scale = 0 dBFS–40–90–85–80–75–70–65–60–55–50–45I M D (d B c)050100150200250300350400450f OUT (MHz)08281-118Figure 21. IMD vs. f OUT , PLL On vs. PLL Off, 4× Interpolation, f DATA = 200 MSPS,Digital Scale = 0 dBFS, f SC = 20 mAAD9122–152–156–154–158–160–162–164––166N S D (d B m /H z )50100150200250300350400450f OUT (MHz)908281-11Figure 22. 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL Off–154–158–156–160–162–164–166–168N S D (d B m /H z )050100150200250300350400450f OUT (MHz)08281-12Figure 23. 1-Tone NSD vs. f OUT over Digital Scale, f DATA = 200 MSPS,4× Interpolation, f SC = 20 mA, PLL Off–158–159–160–161–162–163–164–165N S D (d B m /H z )–166050100150200250300350400450f OUT (MHz)08281-121Figure 24. 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL On 161.0–165.5–165.0–164.5–164.0–163.5–163.0–162.5–162.0–161.5050100150200250300350400450N S D (d B m /H z )f OUT(MHz)08281-122Figure 25. 8-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL Off–161.0–166.5–165.5–166.0–165.0–164.5–164.0–163.5–163.0–162.5–162.0–161.5050100150200250300350400450N S D (d B m /H z )fOUT (MHz)08281-123Figure 26. 8-Tone NSD vs. f OUT over Digital Scale, f DATA = 200 MSPS,4× Interpolation, f SC = 20 mA, PLL Off–160–161–162–163–164–165–166N S D (d B m /H z)050100150200250300350400450f OUT (MHz)08281-124Figure 27. 8-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL OnAD9122–77–84–83–82–81–80–79–78A C L R (d B c )–050100150200250fOUT (MHz)50–55–60–65–70–75–80–85–900100200300400500A C L R (dB c )f OUT(MHz)08281-12508281-128Figure 28. 1-Carrier W-CDMA ACLR vs. f OUT over Digital Scale,Adjacent Channel, PLL Off–78–88–86–84–82–80–90A C L R (dB c )050100150200250fOUT (MHz)08281-126Figure 29. 1-Carrier W-CDMA ACLR vs. f OUT over f DAC ,Alternate Channel, PLL Off–70–90–85–80–75A C L R (dB c )–95050100150200250fOUT (MHz)08281-127Figure 30. 1-Carrier W-CDMA ACLR vs. f OUT over f DAC ,Second Alternate Channel, PLL Off Figure 31. 1-Carrier W-CDMA ACLR vs. f OUT , Adjacent Channel,PLL On vs. PLL Off–70–72–74–76–78–80–82–84–86–88–900100200300400500A C L R (dB c )f OUT(MHz)08281-129Figure 32. 1-Carrier W-CDMA ACLR vs. f OUT , Alternate Channel,PLL On vs. PLL Off–70–95–90–85–80–75A C L R (dB c)0100200300400500f OUT (MHz)08281-130Figure 33. 1-Carrier W-CDMA ACLR vs. f OUT , Second Alternate Channel,PLL On vs. PLL OffAD912208281-131START 133.06MHz #RES BW 30kHzVBW 30kHz STOP 166.94MHzSWEEP 143.6ms (601 PTS)START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 174.42MHzSWEEP 206.9ms (601 PTS)TOTAL CARRIER POWER –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22REF CARRIER POWER –16.89dBm/3.84000MHzLOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 1–16.92dBm 5.000MHz 3.840MHz –65.88–82.76–67.52–84.40RMS RESULTS FREQ LOWER UPPER OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.00MHz 3.840MHz –75.96–85.96–77.13–87.13–10.00dBm/10.00MHz 3.840MHz –85.33–95.33–85.24–95.253.840MHz15.00MHz2.888MHz–95.81–95.81–85.43–95.4308281-1322–16.89dBm 10.00MHz 3.840MHz –68.17–85.05–69.91–86.793–17.43dBm 15.00MHz 3.840MHz–70.42–87.31–71.40–88.284–17.64dBmFigure 35. 1-Carrier W-CDMA ACLR Performance, IF = ~150 MHzFigure 34. 4-Carrier W-CDMA ACLR Performance, IF = ~150 MHzAD9122 TERMINOLOGYIntegral Nonlinearity (INL)INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.Differential Nonlinearity (DNL)DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset ErrorThe deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1.Gain ErrorThe difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.Output Compliance RangeThe range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.Temperature DriftTemperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or T MAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius.Power Supply Rejection (PSR)The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling TimeThe time required for the output to reach and remain within a specified error band around its final value, measured fromthe start of the output transition.Spurious Free Dynamic Range (SFDR)The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output.Signal-to-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.Interpolation FilterIf the digital inputs to the DAC are sampled at a multiple rate of f DATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near f DATA/2. Images that typically appear around f DAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR)The ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image RejectionIn a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.。

LM93资料

LM93Hardware Monitor with Integrated Fan Control for Server Management1.0General DescriptionThe LM93,hardware monitor,has a two wire digital interface compatible with SMBus ing an 8-bit Σ∆ADC,the LM93measures the temperature of two remote diode con-nected transistors as well as its own die and 16power supply voltages.To set fan speed,the LM93has two PWM outputs that are each controlled by up to four temperature zones.The fan-control algorithm is lookup table based.The LM93includes a digital filter that can be invoked to smooth temperature read-ings for better control of fan speed.The LM93has four tachometer inputs to measure fan speed.Limit and status registers for all measured values are included.The LM93builds upon the functionality of previous mother-board management ASICs and uses some of the LM85’s features (i.e.smart tachometer mode).It also adds measure-ment and control support for dynamic Vccp monitoring and PROCHOT.It is designed to monitor a dual processor Xeon class motherboard with a minimum of external components.2.0Featuresn 8-bit Σ∆ADCn Monitors 16power suppliesn Monitors 2remote thermal diodes n Internal ambient temperature sensingn Programmable autonomous fan control based on temperature readings with fan boost support n Fan control based on 13-step lookup table n Temperature reading digital filtern 1.0˚C digital temperature sensor resolution n 0.5˚C temperature resolution for fan control n 2PWM fan speed control outputs n 4fan tachometer inputsnDual processor thermal throttling (PROCHOT)monitoringn Dual dynamic VID monitoring (6VIDs per processor)n 8general purpose I/Os:—4can be configured as fan tachometer inputs—2can be configured to connect to THERMTRIP from a processor—2are standard GPIOs that could be used to monitor IERR signaln 2general purpose inputs that can be used to monitor SCSI termination signalsn Limit register comparisons of all monitored values n 2-wire,SMBus 2.0compliant,serial digital interface —Supports byte/block read and write—Configurable slave address (tri-level pin selects 1of 3possible addresses)n 2.5V reference voltage output n 56-pin TSSOP package n XOR-tree test mode3.0Key Specificationsn Voltage Measurement Accuracy ±2%FS (max)n Resolution8-bits,1˚C n Temperature Sensor Accuracy ±3˚C (max)nTemperature Range:—LM93Operational0˚C to +85˚C —Remote Temp Accuracy 0˚C to +125˚C n Power Supply Voltage +3.0V to +3.6Vn Power Supply Current 0.9mA4.0Applicationsn Serversn Workstationsn Multi-Microprocessor based equipment5.0Ordering InformationOrder Number NS Package Number Transport media LM93CIMT MTD5634units in railLM93CIMTXMTD561000units in tape-and-reelI 2C is a registered trademark of the Philips Corporation.April 2004LM93Hardware Monitor with Integrated Fan Control for Server Management©2004National Semiconductor Corporation 6.0Block Diagram20068201L M 93 27.0ApplicationBaseboard management of a Dual processor server.Two LM93s may be required to manage a quad processor base-board.The block diagram of LM93hardware is illustrated below.The hardware implementation is a single chip ASIC solution.2Way Xeon Server Management20068205LM93 3Table of Contents1.0General Description .....................................................................................................................................12.0Features .......................................................................................................................................................13.0Key Specifications ........................................................................................................................................14.0Applications ..................................................................................................................................................15.0Ordering Information ....................................................................................................................................16.0Block Diagram ..............................................................................................................................................27.0Application ....................................................................................................................................................38.0Connection Diagram ....................................................................................................................................79.0Pin Descriptions ...........................................................................................................................................810.0Server Terminology ..................................................................................................................................1011.0Recommended Implementation ................................................................................................................1112.0Functional Description ..............................................................................................................................1212.1MONITORING CYCLE TIME ................................................................................................................1212.2Σ∆A/D INHERENT AVERAGING ..........................................................................................................1212.3TEMPERATURE MONITORING ...........................................................................................................1212.3.1Temperature Data Format ...............................................................................................................1212.3.2Thermal Diode Fault Status .............................................................................................................1212.4VOLTAGE MONITORING ......................................................................................................................1212.5RECOMMENDED EXTERNAL SCALING RESISTORS FOR +12V POWER RAILS ..........................1312.6RECOMMENDED EXTERNAL SCALING CIRCUIT FOR −12V POWER INPUT ................................1312.7DYNAMIC Vccp MONITORING USING VID .........................................................................................1512.8V REF OUTPUT .......................................................................................................................................1512.9PROCHOT BACKGROUND INFORMATION ........................................................................................1512.10PROCHOT MONITORING ..................................................................................................................1612.11PROCHOT OUTPUT CONTROL ........................................................................................................1612.12FAN SPEED MEASUREMENT ...........................................................................................................1712.13SMART FAN SPEED MEASUREMENT .............................................................................................1713.0Inputs/Outputs ..........................................................................................................................................1713.1ALERT OUTPUT ...................................................................................................................................1713.2RESET INPUT/OUTPUT .......................................................................................................................1713.3PWM1AND PWM2OUTPUTS .............................................................................................................1713.4SCSI_TERMx INPUTS ..........................................................................................................................1713.5VRD1_HOT AND VRD2_HOT INPUTS ................................................................................................1813.6GPIO PINS ............................................................................................................................................1813.7FAN TACH INPUTS ...............................................................................................................................1814.0SMBus Interface .......................................................................................................................................1814.1SMBUS ADDRESSING .........................................................................................................................1814.2DIGITAL NOISE EFFECT ON SMBUS COMMUNICATION .................................................................1814.3GENERAL SMBUS TIMING ..................................................................................................................1814.4SMBUS ERROR SAFETY FEATURES ................................................................................................1914.5SERIAL INTERFACE PROTOCOLS .....................................................................................................1914.5.1Address Incrementing ......................................................................................................................1914.5.2Block Command Code Summary ....................................................................................................2014.5.3Write Operations .............................................................................................................................2014.5.3.1Write Byte ...................................................................................................................................2014.5.3.2Write Word .................................................................................................................................2014.5.3.3SMBus Write Block to Any Address ...........................................................................................2114.5.3.4I 2C ™Block Write .......................................................................................................................2114.5.4Read Operations ..............................................................................................................................2214.5.4.1Read Byte ..................................................................................................................................2214.5.4.2Read Word .................................................................................................................................2214.5.4.3SMBus Block-Write Block-Read Process Call ...........................................................................2214.5.4.4Simulated SMBus Block-Write Block-Read Process Call ..........................................................2414.5.4.5SMBus Fixed Address Block Reads ..........................................................................................2414.5.4.6I 2C Block Reads .........................................................................................................................2514.6READING AND WRITING 16-BIT REGISTERS ...................................................................................2515.0Using The LM93.......................................................................................................................................2615.1POWER ON ..........................................................................................................................................2615.2RESETS ................................................................................................................................................2615.3ADDRESS SELECTION ........................................................................................................................2615.4DEVICE SETUP ....................................................................................................................................2615.5ROUND ROBIN VOLTAGE/TEMPERATURE CONVERSION CYCLE . (26)L M 934LM93Table of Contents(Continued)15.6ERROR STATUS REGISTERS (27)15.6.1ASF Mode (27)15.7MASKING,ERROR STATUS AND ALERT (27)15.8LAYOUT AND GROUNDING (27)15.9THERMAL DIODE APPLICATION (27)15.9.1Accuracy Effects of Diode Non-Ideality Factor (28)15.9.2PCB Layout for Minimizing Noise (28)15.10FAN CONTROL (28)15.10.1Automatic Fan Control Algorithm (28)15.10.2Fan Control Temperature Resolution (30)15.10.3Zone1-4to PWM1-2Binding (31)15.10.4Fan Control Duty Cycles (31)15.10.5Alternate PWM Frequencies (31)15.10.6Fan Control Priorities (31)15.10.7PWM to100%Conditions (31)15.10.8VRDx_HOT Ramp-Up/Ramp-Down (32)15.10.9PROCHOT Ramp-Up/Ramp-Down (32)15.10.10Manual PWM Override (32)15.10.11Fan Spin-Up Control (32)15.11XOR TREE TEST (33)16.0Registers (34)16.1REGISTER WARNINGS (34)16.2REGISTER SUMMARY TABLE (34)16.3FACTORY REGISTERS00h–3Fh (40)16.3.1Register00h XOR Test (40)16.3.2Register01h SMBus Test (40)16.3.3Register3Eh Manufacturer ID (40)16.3.4Register3Fh Version/Stepping (40)16.4BMC ERROR STATUS REGISTERS40h–47h (41)16.4.1Register40h B_Error Status1 (41)16.4.2Register41h B_Error Status2 (42)16.4.3Register42h B_Error Status3 (42)16.4.4Register43h B_Error Status4 (43)16.4.5Register44h B_P1_PROCHOT Error Status (43)16.4.6Register45h B_P2_PROCHOT Error Status (44)16.4.7Register46h B_GPI Error Status (44)16.4.8Register47h B_Fan Error Status (45)16.5HOST ERROR STATUS REGISTERS (45)16.5.1Register48h H_Error Status1 (45)16.5.2Register49h H_Error Status2 (46)16.5.3Register4Ah H_Error Status3 (47)16.5.4Register4Bh H_Error Status4 (48)16.5.5Register4Ch H_P1_PROCHOT Error Status (49)16.5.6Register4Dh B_P2_PROCHOT Error Status (50)16.5.7Register4Eh H_GPI Error Status (51)16.5.8Register4Fh H_Fan Error Status (52)16.6VALUE REGISTERS (52)16.6.1Registers50–53h Unfiltered Temperature Value Registers (52)16.6.2Registers54–55h Filtered Temperature Value Registers (52)16.6.3Register56–65h A/D Channel Voltage Registers (53)16.6.4Register67h Current P1_PROCHOT (53)16.6.5Register68h Average P1_PROCHOT (54)16.6.6Register69h Current P2_PROCHOT (54)16.6.7Register6Ah Average P2_PROCHOT (54)16.6.8Register6Bh GPI State (55)16.6.9Register6Ch P1_VID (55)16.6.10Register6Dh P2_VID (55)16.6.11Register6E–75h Fan Tachometer Readings (56)16.7LIMIT REGISTERS (57)16.7.1Registers78–7Fh Temperature Limit Registers (57)16.7.2Registers80–83h Fan Boost Temperature Registers (57)5Table of Contents(Continued)16.7.3Registers 90–AFh Voltage Limit Registers ...................................................................................5816.7.4Register B0–B1h PROCHOT User Limit Registers ......................................................................5916.7.5Register B2–B3h Dynamic Vccp Limit Offset Registers ...............................................................6016.7.6Register B4–BBh Fan Tach Limit Registers .................................................................................6116.8SETUP REGISTERS .............................................................................................................................6216.8.1Register BCh Special Function Control 1(Voltage Hysteresis and Fan Control Filter Enable)...6216.8.2Register BDh Special Function Control 2(Smart Tach Mode Enable and Fan Control Temperature Resolution Control).....................................................................................................................................6316.8.3Register BEh GPI/VID Level Control ............................................................................................6316.8.4Register BFh PWM Ramp Control ................................................................................................6416.8.5Register C0h Fan Boost Hysteresis (Zones 1/2)..........................................................................6416.8.6Register C1h Fan Boost Hysteresis (Zones 3/4)..........................................................................6516.8.7Register C2h Zones 1/2Spike Smoothing Control .......................................................................6516.8.8Register C3h Zones 1/2MinPWM and Hysteresis .......................................................................6616.8.9Register C4h Zones 3/4MinPWM and Hysteresis .......................................................................6616.8.10Register C5h GPO ......................................................................................................................6716.8.11Register C6h PROCHOT Override ..............................................................................................6816.8.12Register C7h PROCHOT Time Interval ......................................................................................6916.8.13Register C8h PWM1Control 1...................................................................................................7016.8.14Register C9h PWM1Control 2...................................................................................................7116.8.15Register CAh PWM1Control 3...................................................................................................7216.8.16Register CBh Special Function PWM1Control 4.......................................................................7216.8.17Register CCh PWM2Control 1...................................................................................................7316.8.18Register CDh PWM2Control 2...................................................................................................7416.8.19Register CEh PWM2Control 3...................................................................................................7516.8.20Register CFh Special Function PWM2Control 4.......................................................................7516.8.21Register D0h–D3h Zone 1to 4Base Temperatures ..................................................................7616.8.22Register D4h–DFh Lookup Table Steps —Zone 1/2and Zone 3/4Offset Temperature ...........7616.8.23Register E0h Special Function TACH to PWM Binding ..............................................................7716.8.24Register E2h LM93Status Control .............................................................................................7816.8.25Register E3h LM93Configuration ...............................................................................................7916.9SLEEP STATE CONTROL AND MASK REGISTERS ..........................................................................8016.9.1Register E4h Sleep State Control ................................................................................................8016.9.2Register E5h S1GPI Mask ...........................................................................................................8116.9.3Register E6h S1Tach Mask .........................................................................................................8116.9.4Register E7h S3GPI Mask ...........................................................................................................8216.9.5Register E8h S3Tach Mask .........................................................................................................8216.9.6Register E9h S3Temperature/Voltage Mask ................................................................................8216.9.7Register EAh S4/5GPI Mask .......................................................................................................8316.9.8Register EBh S4/5Temperature/Voltage Mask ............................................................................8316.10OTHER MASK REGISTERS ...............................................................................................................8416.10.1Register ECh GPI Error Mask .....................................................................................................8416.10.2Register EDh Miscellaneous Error Mask ....................................................................................8416.10.3Register EEh Special Function Zone 1Adjustment Offset .........................................................8516.10.4Register EFh Special Function Zone 2Adjustment Offset .........................................................8517.0Absolute Maximum Ratings .....................................................................................................................8618.0Operating Ratings ...................................................................................................................................8619.0Data Sheet Version History ......................................................................................................................9120.0Physical Dimensions .. (92)L M 93 6LM93 8.0Connection Diagram56Pin TSSOP Array20068202NS Package MTD56Top ViewNS Order Numbers:LM93CIMT(34units per rail),orLM93CIMTX(1000units per tape-and-reel)79.0Pin DescriptionsSymbol Pin #Type FunctionGPIO_0/TACH11Digital I/O (Open-Drain)Can be configured as fan tach input or a general purpose open-drain digital I/O.GPIO_1/TACH22Digital I/O (Open-Drain)Can be configured as fan tach input or a general purpose open-drain digital I/O.GPIO_2/TACH33Digital I/O (Open-Drain)Can be configured as fan tach input or a general purpose open-drain digital I/O.GPIO_3/TACH44Digital I/O (Open-Drain)Can be configured as fan tach input or a general purpose open-drain digital I/O..GPIO_4/P1_THERMTRIP 5Digital I/O (Open-Drain)A general purpose open-drain digital I/O.Can be configured to monitor a CPU’s THERMTRIP signal to mask other errors.GPIO_5/P2_THERMTRIP 6Digital I/O (Open-Drain)A general purpose open-drain digital I/O.Can be configured to monitor a CPU’s THERMTRIP signal to mask other errors.GPIO_67Digital I/O (Open-Drain)Can be used to detect the state of CPU1IERR or a general purpose open-drain digital I/OGPIO_78Digital I/O (Open-Drain)Can be used to detect the state of CPU2IERR or a general purpose open-drain digital I/O VRD1_HOT 9Digital Input CPU1voltage regulator HOT VRD2_HOT 10Digital Input CPU2voltage regulator HOTSCSI_TERM111Digital Input SCSI Channel 1termination fuse.Could also be used as a general purpose input to trigger an error event.SCSI_TERM212Digital Input SCSI Channel 2termination fuse.Could also be used as a general purpose input to trigger an error event.SMBDAT 13Digital I/O (Open-Drain)Bidirectional System Management Bus Data.Output configured as 5V tolerant open-drain.SMBus 2.0compliant.SMBCLK 14Digital Input System Management Bus Clock.Driven by an open-drain output,and is 5V tolerant.SMBus 2.0Compliant.ALERT/XtestOut15Digital Output (Open-Drain)Open-drain ALERT output used in an interrupt driven system to signal that an error event has occurred.Masked error events do not activate the ALERT output.When in XOR tree test mode,functions as XOR Tree output.RESET 16Digital I/O (Open-Drain)Open-drain reset output when power is first applied to the ed as a reset for devices powered by 3.3V stand-by.After reset,this pin becomes a reset input.See section 6.2for more information.AGND 17GROUND Input Analog GroundV REF18Analog Output 2.5V used for external ADC reference,or as a V REF reference voltageREMOTE1−19Remote Thermal Diode_1-Input (CPU 1THERMDC)This is the negative input (current sink)from the CPU1thermal diode.Connected to THERMDC pin of Pentium processor or the emitter of a diode connected MMBT3904NPN transistor.Serves as the negative input into the A/D for thermal diode voltage measurements.A 100pF capacitor is optional and can be connected between REMOTE1−and REMOTE1+.REMOTE1+20Remote Thermal Diode_1+I/O (CPU1THERMDA)This is a positive connection to the CPU1thermal diode.Serves as the positive input into the A/D for thermal diode voltagemeasurements.It also serves as a current source output thatforward biases the thermal diode.Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904NPN transistor.A 100pF capacitor is optional and can be connected between REMOTE1−and REMOTE1+.L M 93 89.0Pin Descriptions(Continued)Symbol Pin#Type FunctionREMOTE2−21Remote ThermalDiode_2-Input(CPU2THERMDC)This is the negative input(current sink)from the CPU2thermal diode.Connected to THERMDC pin of Pentium processor or the emitter of a diode connected MMBT3904NPN transistor.Serves as the negative input into the A/D for thermal diode voltage measurements.A100pF capacitor is optional and can be connected between REMOTE2−and REMOTE2+.REMOTE2+22Remote ThermalDiode_2+I/O(CPU2THERMDA)This is a positive connection to the CPU2thermal diode.Serves as the positive input into the A/D for thermal diode voltage measurements.It also serves as a current source output that forward biases the thermal diode.Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor.A100pF capacitor is optional and can be connected between REMOTE2−and REMOTE2+.AD_IN123Analog Input(+12V1)Analog Input for+12V Rail1monitoring,for CPU1voltage regulator.External attenuation resistors required such that12V is attenuatedto0.927V.AD_IN224Analog Input(+12V2)Analog Input for+12V Rail2monitoring,for CPU2voltage regulator.External attenuation resistors required such that12V is attenuatedto0.927V.AD_IN325Analog Input(+12V3)Analog Input for+12V Rail3,for Memory/3GIO slots.Externalattenuation resistors required such that12V is attenuated to0.927V.AD_IN426Analog Input(FSB_Vtt)Analog input for1.2V monitoringAD_IN527Analog Input(3GIO/PXH/MCH_Core)Analog input for1.5V monitoring.AD_IN628Analog Input(ICH_Core)Analog input for1.5V monitoring.AD_IN7(P1_Vccp)29Analog Input(CPU1_Vccp)Analog input for+Vccp(processor voltage)monitoring.AD_IN8(P2_Vccp)30Analog Input(CPU2_Vccp)Analog input for+Vccp(processor voltage)monitoring.AD_IN931Analog Input(+3.3V)Analog input for+3.3V monitoring.AD_IN1032Analog Input(+5V)Analog input for+5V monitoring silver box supply monitoring.AD_IN1133Analog Input(SCSI_Core)Analog input for+2.5V monitoring.AD_IN1234Analog Input(Mem_Core)Analog input for+1.969V monitoring.AD_IN1335Analog Input(Mem_Vtt)Analog input for+0.984V monitoring.AD_IN1436Analog Input(Gbit_Core)Analog input for+0.984V S/B monitoring.AD_IN1537Analog Input(-12V)Analog input for-12V monitoring.External resistors required to scaleto positive level.Full scale reading at1.236V.Address Select383level analog input This input selects the lower two bits of the LM93SMBus slaveaddress.LM9399.0Pin Descriptions(Continued)Symbol Pin #TypeFunctionAD_IN1639POWER (V DD )+3.3V standby powerV DD power input for LM93.Generally this is connected to +3.3V standby power.The LM93can be powered by +3.3V if monitoring in low power states is not required,but power should be applied to this input before any other pins.This pin also serves as the analog input to monitor the 3.3Vstand-by (SB)voltage.It is necessary to bypass this pin with a 0.1µF in parallel with 100pF.A bulk capacitance of 10µF should be in the near vicinity.The 100pF should be closest to the power pin.GND 40GROUNDDigital Ground.Digital ground and analog ground need to be tied together at the chip then both taken to a low noise system ground.A voltage difference between analog and digital ground may cause erroneous results.PWM141Digital Output (Open-Drain)Fan control output 1.PWM242Digital Output (Open-Drain)Fan control output 2P1_VID043Digital Input Voltage Identification signal from the processor.P1_VID144Digital Input Voltage Identification signal from the processor.P1_VID245Digital Input Voltage Identification signal from the processor.P1_VID346Digital Input Voltage Identification signal from the processor.P1_VID447Digital Input Voltage Identification signal from the processor.P1_VID548Digital Input Voltage Identification signal from the processor.P1_PROCHOT 49Digital I/O (Open-Drain)Connected to CPU1PROCHOT (processor hot)signal through a bidirectional level shifter.P2_PROCHOT 50Digital I/O (Open-Drain)Connected to CPU2PROCHOT (processor hot)signal through a bi-directional level shifter.P2_VID051Digital Input Voltage Identification signal from the processor.P2_VID152Digital Input Voltage Identification signal from the processor.P2_VID253Digital Input Voltage Identification signal from the processor.P2_VID354Digital Input Voltage Identification signal from the processor.P2_VID455Digital Input Voltage Identification signal from the processor.P2_VID556Digital InputVoltage Identification signal from the processor.The overscore indicates the signal is active low (“Not”).10.0Server TerminologyA/D Analog to Digital Converter ACPI Advanced Configuration and Power InterfaceALERTSMBus signal to bus master that an event occurred that has been flagged for attention.ASF Alert Standard Format BMC Baseboard Micro-Controller BW BandwidthDIMM Dual inline memory module DP Dual-processorECC Error checking and correcting FRU Field replaceable unit FSBFront side busFW Firmware Gb Gigabit GB Gigabyte Gbe Gigabit Ethernet GPIO General purpose I/O HW HardwareI 2C Inter integrated circuit (bus)LAN Local area networkLVDS Low-Voltage Differential Signaling Mb Megabit MB Megabyte MP Multi-processorMTBFMean time between failuresL M 9310。

分娩孕周医学英语

分娩孕周医学英语Diving into the fascinating world of childbirth, the gestational age, or the number of weeks a baby has been developing in the womb, plays a pivotal role in determining the timing and approach to delivery. From the first flutter of life at around 20 weeks, when a baby can be heard through a stethoscope, to the full-term milestone at 40 weeks, each stage is marked by distinct medical milestones and terminology.In obstetrics, the term "gestation" is measured in weeks, starting from the first day of a woman's last menstrual period. The weeks are categorized into trimesters, with each trimester encompassing a unique set of developmental stages. The first trimester, from weeks 1 to 12, is critical for organ development and is often marked by high risk due to the susceptibility of the embryo to environmental influences. The second trimester, from weeks 13 to 27, sees the baby growing rapidly, with the mother beginning to feel movements and the fetus becoming more viable outside the womb. The third trimester, from weeks 28 to 40, is the home stretch where the baby gains weight, and the mother prepares for the imminent arrival.The term "full term" refers to a baby born between 37 and 42 weeks of gestation, which is considered the optimal time for birth, offering the best chance for a healthy start in life. Preterm birth, occurring before 37 weeks, can posesignificant health risks to the newborn, necessitating specialized care. Conversely, post-term pregnancy, beyond 42 weeks, also requires close monitoring due to the potentialfor complications such as meconium aspiration or fetal macrosomia.Medical professionals use various methods to assess gestational age, including ultrasound for early estimation and the Modified Bishop Score for assessing the readiness of the cervix for labor in later stages. The language of childbirth is replete with terms like "vertex" for the baby's head presentation, "cervical dilation" for the opening of the birth canal, and "episiotomy" for the surgical incision made to enlarge the vaginal opening during delivery.Understanding the medical English of childbirth is not only essential for healthcare providers but also empowers expectant parents to be active participants in the birthing process. It bridges the gap between medical expertise and personal experience, ensuring that the journey from pregnancy to parenthood is as informed and supported as possible.。

测绘专业英语gps文章翻译

A Unit 15 The Global Positioning SystemPreamble序The Global Positioning System (GPS) is revolutionizing surveying technology. GPS正在革新着测绘技术Like its predecessor, the TRANSIT Doppler system, 像它的前任仪器，中天仪多普勒系统GPS shifts the scene of surveying operations from ground-to-ground measurements to ground-to-sky ,GPS在测量操作上正在改变着从地对地观测到地对空观测的测量环境with obvious implications: visibility of marks is no longer a criterion for their location :operations are possible in nearly all kinds of weather and can be performed during day or night ;and the skills required to utilize the technology are different both in filed operations and data processing.有一些明显的结论标志的可见性不在是定位的一个标准在几乎任何天气、不分昼夜操作都是可以进行的使用这项技术所要求的技能在野外测量和数据处理中都是不同的But GPS is not merely a replacement for TRANSIT .the simultaneous visibility of multiple satellites allows effective cancellation of the major sources of error in satellite observations, with the result that with GPS ,relative positioning accuracies of one part per million ( ppm) or better over distances from one kilometer to thousands of kilometers are possible .This means that GPS Can compete with terrestrial techniques over short distances ,and can achieve more accurate results in less time than TRANSIT observations over longer distances.但GPS不只是代替中天仪。

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PC Based Precision Timing Without GPSAttila P´asztor∗,†Darryl Veitch∗http://www.emulab.ee.mu.oz.au/∼attilahttp://www.emulab.ee.mu.oz.au/∼darryl∗CUBIN,Dept.of Electrical&Electronic Engineering,University of Melbourne.†Ericsson Hungary R&D,Budapest.Essentials of Active MeasurementSender Monitor Receiver Monitor •T est probe packets are sent from sender to source.•Arrival and Departure times,and losses,are monitored.•Measurements used to infer network characteristics and conditions.—Timestamps are a crucial aspect.—Typically different clocks at Sender and Receiver−→Synchronisation issues.Some Timing Terminology •Resolution :smallest clock increment.•Offsetθ(t):difference from true time t at time t.•Skewγ:average difference in rate from true rate.•Oscillator Stability yτ(t):variations in rate.A Simple Model of Timing Errors:θ(t)=θ0+γ∗t+ω(t),simple skew plus instability.Oscillator Stability:yτ(t)=θ(t+τ)−θ(t)τ=γ+ω(t+τ)−ω(t)τ.Studied through the Allan Variance,a scale-dependent variance estimation of the family{yτ(t)} of relative offset errors.What is Really Important in Active Measurement?The Raw Data •Arrival times:τ∗i.•Departure times:τi.•Packet sizes:p i.•Loss indications:L i.The Elements of Timing •Accurate clocks:rate synchronisation.offset synchronisation.•Fast,reliable timestamping.•Accurate senders.The Bases of Analysis Their Bases in Timing•End-to-end delay:d i=τ∗i−τi–Depends on(relative)offset at two ends.•Delay variation:δi=d i−d i−1–Depends on rate at two ends.•Inter-arrival durations:t i=τi−τi−1–Depends on rate at one end.Key Observations•Except for simple delay metrics,active probing analysis based on{δi}and{t i}.•Rate synchronisation is primordial.The Need for AccuracyReference Infrastructure over 13hops (EMULab and WAND in New Zealand)Packet Departure Time [sec]O n e W a y D e l a y [s e c ]Packet Departure Time [sec]O n e W a y D e l a y [s e c ]Delay :100’s of ms,±1ms acceptable.Delay variation &Inter-arrival times:can be sub–ms,±0.01ms needed.The Network Time Protocol(NTP)Aim:to correct clock OffsetA protocol,a Network of servers,a Set of algorithms•A protocol to communicate timing information.•A set of primary servers with reference timing(eg GPS,offset10µs).•Secondary servers connected via a network(offset>1ms).•Algorithms for the synchronisation to the input signal.•Timestamps requested,offset recommendations calculated,smoothed rate adjustments handed down to the SW.•Error bounded by the round-trip-time(and system noise).•‘Input signal’could be over a network,or from an attached reference source.A Hierarchy of Timing Accuracy•Low end:$Ethernet card,PC.Unix,Software clock,NTP,tcpdump,User sender/receiver.•‘Common’GPS solution:$$$Ethernet card,PC,GPS.Unix,GPS synchronised clock,tcpdump,User sender/receiver.•Linux–TSC solution:$Ethernet card,PC.Unix,TSC clock,driver timestamper,User sender/receiver.•RT–Linux–TSC solution:$Ethernet card,PC.Unix,TSC clock,driver timestamper,RT sender/receiver.•Our Reference solution:$$$$DAG3.2e cards,GPS,Ethernet card,PC. GPS sync’d DAG monitors,Unix,TSC clock,driver timestamper,RT sender.•High end:$$$$$All hardware solution.Obstacles to Inexpensive Accuracy‘Features’of the Low End:the SW–NTP–tcpdump solution•The Standard Software Clock(SW):•Based on two underlying oscillators with large skews.•getimeofday()has1µs resolution and takes1µs to call.•SW Synchronisation under NTP:•Offset:only bounded to≈1ms under optimal conditions.•Rate:altered to control offset!up to500PPM!!•System Noise under Unix(Linux,BSD):•Uncontrolled scheduling delays in setting,synchronising,reading,sending..•Hardware interrupt latencies.•Timestamping and Sending•tcpdump timestamps with getimeofday()after driver.•User sender tries to schedule using getimeofday()and hopes for the best.Skews in the Freerunning SW Clock (NTP off)Offsets of component clocks in SW,each showing signiﬁcant skew.•interrupt clock :timer chip on motherboard underlying periodic interrupts.•interpolation clock :TSC based counter with poor boot time period estimate.Time [sec]O f f s e t [s e c ]End-to-End Delay:does this look familiar?NTP can be bad...ad-hoc data ‘cleaning’is problematic.Original delayd e l a y (s )••••••0100002000030000400000.00.51.01.5Jumps removed and detrendedd e l a y (s )0100002000030000400000.00.050.100.150.20Adjusted to common minimumSequence numberd e l a y (s )0100002000030000400000.00.050.100.150.20Problem :how to distinguish non-obvious timing errors from delay variations?Rate Under NTPOn large time scales,NTP indeed controls offset .x 104Time [sec]O f f s e t [s e c ]Looking more closely,we see the induced rate irregularities .−4t [sec]O f f s e t [m s ]The Accuracy Gap:Low End−→ReferenceInfrastructure Offset Skew System Noise Low End1ms–....5–500PPM10µs–10ms Our Reference100ns0.01PPM<100nsThe Key to the Solution:Oscillator StabilityStability of the software clock/interrupt–clock and TSC based interpolation–clock over 24hours.x 104t [sec] τ = 1000 secy τ(t ) − γ [P P M ]1010101010101010100101τ [sec]A l l a n D e v i a t i o n o f y τ [P P M ]Rate variations Under 0.1PPM with τ=1000s .Allan deviation Simple skew model valid to τ=1000sRelative error <0.1PPM beyond 60sec.Leveraging Existing Hardware:the CPU OscillatorMonitoring p with reference infrastructure−10t [day]p − E [p ] [ µs e c / C P U c l o c k c y c l e ]The (centered)CPU period series p (i )over a 100day period ,showing a 0.1PPM stability.A TSC Based ClockThe idea:time=θ0+(TSC register value)×p Features/Advantages•1nanosecond resolution.•Stable feature of PC architecture.•Hardware updating.•Ultra fast timestamping(read register):(<50ns).•Natural smooth rate:0.1PPM over useful timescales.The Catch:–must estimate the cycle period p and offsetθ0without special hardware.Two Methods for Rate CalibrationNTP Based•Use bounded offset of NTP(access just by reading the SW).•Record SW timestamps and TSC over a long interval,then divide.Single Reference Source•Send periodic stream from accurate rate source.•Record TSC timestamps with uncalibrated accurate rate receiver.•Filter networking variations and measure slope to obtain p.Method 2:Calibration to 0.1PPM over 40Hops4Sender DAG − Packet departure time [sec]D e t r e n d e d d e l a y [s e c ]x 104−4Receiver DAG − Packet arrival time [sec]T S C o f f s e t [s e c ]A Method for Offset CalibrationNTP Based•Use NTP to gain access to reference offset.•Each node connects to their closest primary NTP server.•Accurate rate receiver and sender gets timestamps from server.•Accurate rate allows network delay variations to beﬁltered out.•Remaining ambiguity:network delay vs offset error.•Error≤asymmetry in one-way delays≤round-trip delay.Accuracy ComparisonTSC:CPU cycle register.Infrastructure Timing Accuracy MetricOffset Skew System Noise Low End1ms–....5–500PPM10µs–10ms Common GPS10µs5–50PPM10µs–10ms Linux-TSC0.1–2ms0.1PPM1µs–1msRT-Linux-TSC0.1–2ms0.1PPM1µs–10µs Our Reference100ns0.01PPM<100nsAll Hardware<100ns<0.01PPM<100ns System Noise:use TSC timestamper(in driver),and RT–Linux. Skew:use TSC with accurate remote calibration.Offset:use TSC and nearby NTP primary server timestamps.Comparison:SW–NTP–tcpdump,TSC-Linux,TSC-RT -LinuxImprovement is dramatic,scales are:10−4→10−5→10−6OffsetRate Error with τ=1ms−4O f f s e t [s e c ]x 104−6t [ms]O f f s e t [s e c ]4−5O f f s e t [s e c ]−3D i f f O ff s e t [s e c ]4−4D i f f O f f s e t [s e c ]x 104−6t [ms]D i f f O f f s e t [s e c ]Top:SW-NTP-tcpdump,Middle:TSC-Linux,Bottom:TSC-RT -Linux.Conclusions and the FutureThe Result•High accuracy timing available using existing hardware.•Rate accuracy exceeds common Low-end and GPS enhanced solutions.•Offset accuracy adequate for most purposes.•Timestamping accuracy adequate for network measurement.The Future•Optimising offset calibration.•Optimising NTP based rate calibration.•Incorporation into RIPE-NCC test boxes.•Spreading the web..•Using it for probing analysis work!20。