电子元器件ZXCT1080中文资料_数据手册_IC数据表

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ZXCT1009FTA中文资料(Diodes)中文数据手册「EasyDatasheet - 矽搜」

ZXCT1009FTA中文资料(Diodes)中文数据手册「EasyDatasheet - 矽搜」
The wide input voltage range of 20V down to as low as 2.5V make it suitable for a range of applications. A minimum operating current of just 4µA, combined with a SOT23 package make it a unique solution for portable battery equipment. The SM8 device offers an alternative package option.
RLIM(MAX) = R OUT [VIN(MIN) - (VDP + V OUT(MAX) )]/V OUT(MAX)
VIN(MIN) =最低电源工作电压 VDP =压差 VOUT(MAX) =最大工作输出电压
该器件的功耗,P PD = IOUT (V IN -V OUT ) W
D 是由下式给出:
应用信息
以下文本描述了如何扩展到的输出电压的负载电流.
VSENSE = V IN - V LOAD VOUT = 0.01 x V SENSE x ROUT 1
E.g.
1A的电流通过一个100mV的输出代表
电压:
重新排列
1 对于溃败给:
ROUT = V OUT /(V SENSE x 0.01) ROUT = 0.1 / (0.1 x 0.01) = 100Ω
芯片中文手册,看全文,戳
应用信息
锂离子电池充电器电路
(续)
上图显示支持的ZXCT1009 Benchmarq bq2954充电管理IC.大多数支持组件为bq2954 的为了清楚而省略. 这种设计还采用了发光二极管FZT789A高电流 超ßPNP作为在DC-DC升压开关晶体管 升降压转换器和FMMT451作为驱动NPN为 FZT789A.该电路可以被配置充电到4 锂离子电池在1.25A的充电电流.充电可 端接在最大电压,可选的最低 电流,或最大超时.开关的频率 PWM循环大约为120kHz.

电子元器件ZXCT1010中文资料_数据手册_IC数据表

电子元器件ZXCT1010中文资料_数据手册_IC数据表

ZXCT1010Enhanced high-side current monitorDescriptionOrdering informationThe ZXCT1010 is a high side current sense monitor. Using this device eliminates the need to disrupt the ground plane when sensing a load current.t is an enhanced version of the ZXCT1009offering reduced typical output offset and improved accuracy at low sense voltage.The wide input voltage range of 20V down to as low as 2.5V make it suitable for a range of applications. A minimum operating current of just 4␮A, combined with its SOT23-5 package make suitable for portable battery equipment.Features•Low cost, accurate high-side current sensing•Output voltage scaling •Up to 2.5V sense voltage • 2.5V – 20V supply range •300nA typical offset current • 3.5␮A quiescent current •1% typical accuracy •SOT23-5 packageApplications•Battery chargers •Smart battery packs •DC motor control •Over current monitor •Power management•Programmable current sourcePinout informationTypical application circuitDevicePackage Device marking Reel size (inches)Tape width (mm)Quantity per reel ZXCT1010E5TASOT23-5101783000https:///Pin informationAbsolute maximum ratingsOperation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability.Pin Name Description 1N/C Not connection2GND Ground connection3I OUTOutput current, proportional to V IN - V LOAD4V SENSE+Supply voltage5V SENSE-Connection to load/batteryVoltage on any pin (relative to GND pin)-0.6 to 20V (relative to GND)Continuous output current 25mAContinous sense voltageV IN + 0.5V > V SENSE > V IN - 5V Ambient operating temperature range -40 to 85°C Storage temperature -55 to 150°C Package power dissipation T amb = 25°C SOT23-5300mWhttps:///Electrical characteristicsTest conditions T amb = 25°C, V IN = 5V, R OUT = 100⍀NOTES:(a)Includes input offset voltage contribution (b)V SENSE = V IN -V LOAD(c)-20dBm = 63mVp-p into 50⍀Symbol ParameterConditionsLimits UnitMin.Typ.Max.V IN V CC range 2.520V I OUT (a)Output currentV SENSE = 0V 00.310␮A V SENSE = 10mV 85100115␮A V SENSE = 100mV 0.975 1.00 1.025mAV SENSE = 200mV 1.95 2.00 2.05mA V SENSE = 1V9.710.010.3mA I Q Ground pin current V SENSE = 0V3.58␮A V SENSE (b)Sense voltage2500mV I SENSE-V SENSE- input current 100nAAcc AccuracyR SENSE = 0.1⍀ V SENSE = 200mV-2.52.5%Gm Transconductance, I OUT /V SENSE 10000␮A/VBWBandwidthRF P IN = -20dBm (c)V SENSE = 10mV DC 300kHz VSENSE= 100mV DC 2MHzhttps:///Typical characteristicsPower dissipationThe maximum allowable power dissipation of the device Array for normal operation (P max), is a function of the packagejunction to ambient thermal resistance (⍜ja), maximumjunction temperature (Tj max), and ambient temperature(T amb), according to the expression:Pmax = (Tj max – T amb) / ⍜jaThe device power dissipation, P D is given by theexpression:P D=I OUT.(V IN-V OUT) WattsApplications informationThe following lines describe how to scale a load current to an output voltage.V SENSE = V IN - V LOADV OUT = 0.01 x V SENSE x R OUT(1)For example:https:/// A 1A current is to be represented by a 100mV output voltage:1Choose the value of R SENSE to give 50mV > V SENSE > 500mV at full load.For example V SENSE = 100mV at 1.0A. R SENSE = 0.1/1.0 => 0.1⍀.2Choose R OUT to give V OUT = 100mV, when V SENSE = 100mV.Rearranging (1)for R OUT gives:R OUT = V OUT /(V SENSE x 0.01)R OUT = 0.1 / (0.1 x 0.01) = 100⍀Schematic diagramTypical circuit applicationWhere R LOAD represents any load including DC Array motors, a charging battery or further circuitrythat requires monitoring, R SENSE can beselected on specific requirements of accuracy,size and power rating.Li-Ion charger circuitThe figure below shows the ZXCT1010 supporting the Benchmarq bq2954 charge managementIC. Most of the support components for the bq2954 are omitted for clarity. This design also usesthe Zetex FZT789A high current Super-␤ PNP as the switching transistor in the DC-DC step downconverter and the FMMT451 as the drive NPN for the FZT789A. The circuit can be configured to https:///charge up to four Li-Ion cells at a charge current of 1.25A. Charge can be terminated on maximumvoltage, selectable minimum current, or maximum time out. Switching frequency of the PWMloop is approximately 120kHz.Bi-directional current sensingThe ZXCT1010 can be used to measure current bi-Array directionally, if two devices are connected as shownopposite.If the voltage V1 is positive with respect to the voltage V2the lower device will be active, delivering a proportionaloutput current to R OUT. Due to the polarity of the voltageacross Rsense, the upper device will be inactive and will notcontribute to the current delivered to R OUT. When V2 is morepositive than V1, current will be flowing in the oppositedirection, causing the upper device to be active instead.Non-linearity will be apparent at small values of V SENSE dueto offset current contribution. Devices can use separateoutput resistors if the current direction is to be monitoredindependently.https:///Bi-directional transfer functionPCB trace shunt resistor for low cost solution The figure opposite shows output characteristics of the device when using a PCB resistive trace for a low cost solution in replacement for a conventional shunt resistor. The graph shows the linear rise in voltage across the resistor due to the PTC of the material and demonstrates how this rise in resistance value over temperature compensates for the NTC of the device. The figure below shows a PCB layout suggestion.The resistor section is 25mm x 0.25mm giving approximately 150mW using 1oz copper. The data for the normalised graph was obtained using a 1A load current and a 100W output resistor. An electronic version of the PCB layout is available at /isenseLayout shows area of shunt resistor compared to ZSOT23-5package (not actual size).https:///https:///Intentionally left blankPackage outline - SOT23-5Note: Controlling dimensions are in millimeters. Approximate dimensions are provided in inchesDIM MillimetersInchesMin.Max.Min.Max.A 0.90 1.450.03540.0570A10.000.150.000.0059A20.90 1.300.03540.0511b 0.200.500.00780.0196C 0.090.260.00350.0102D 2.70 3.100.10620.1220E 2.20 3.200.08660.1181E1 1.301.800.05110.0708e 0.95 REF 0.0374 REF e1 1.90 REF0.0748 REFL 0.100.600.00390.0236a°0°30°0°30°https:///。

ZXCD1210中文资料(Diodes)中文数据手册「EasyDatasheet - 矽搜」

ZXCD1210中文资料(Diodes)中文数据手册「EasyDatasheet - 矽搜」

应用
• 低音炮 • 家庭影院系统 • 多媒体 • 无线音箱 • 便携式音频
该图显示
THD + N与电源 剧情为一个500W关闭
环低音炮
参考设计. THD + N为0.02% 10W之间 200W是
优秀
性能.
芯片中文手册,看全文,戳
绝对最大额定值
V CC
功耗
封装热阻(JA)
工作温度范围 最高结温 存储温度范围
5
MODOL
6
N/C
7
CK
8
MODOR
9
MODIR
10
AINR
11
Sgnd
12
PWMR
13
Pgnd
14
REG9VR
15
VCC
16
REG9VL
引脚说明
PWM驱动
内部电源轨 音频输入 调制控制 调制控制 无连接
外部电容设置PWM频率
调制控制 调制控制 音频输入 信号接地
PWM驱动
电源地 内部电源轨 内部电源引脚 内部电源轨

Mute
供应Leabharlann Audioinput
PWM output
Input
缓冲 和偏见
Gate
ZXCD1210
司机
输出 桥
过滤
DC Servo
AC comp network
+ -
反馈电路 电路
ZXCDSUBEV系列架构
ZXCDSUBEV系列THD + N与电源
- 端电压相对于GND
20V 1W 55°C/W -40°C至70℃ 125°C -50°C至85°C
超出"绝对最大额定值"所列出数值可能会造成永久性损坏设备.这些压力额定值只,设备在这些功能操作或 超出规范业务部门所标明是不是暗示任何其他条件.暴露在绝对最大条件下工作会影响器件可靠性.

XTR108EVM;中文规格书,Datasheet资料

XTR108EVM;中文规格书,Datasheet资料

User's GuideSBOU014A–July2002–Revised October2005Complete evaluation tool for the XTR108:•XTR108hardware Designer's Kit–Evaluate XTR108and User’s RTD–Fully configurable•Software control for Designer's Kit:–Program XTR108for evaluation–Program XTR108and User's RTD in final module–Calibrate most types of RTDs over wide temperature ranges–Software tool helps to select resistor valuesContents1Introduction (2)2Description (3)3XTR108Sensor Interface Board Overview (4)4XTR108PC Interface Board Overview (6)5Initial Setup and Check-Out (7)6Software Overview (17)7General Operating Tips (24)8XTR108EVM PC Cable Drawing (34)9Schematics (34)Windows is a trademark of Microsoft Corporation.SPI is a trademark of Motorola,Inc.All trademarks are the property of their respective owners.1IntroductionIntroductionList of Figures1XTR108EVM Typical System Set-up ............................................................42XTR108EVM Sensor Interface Board Filter Configuration ....................................53Pin Socket Mechanical Description ..............................................................64XTR108EVM Sensor Interface Board—Factory Jumper Settings ............................75Hardware Setup -Initial Checkout ................................................................86XTR108EVM Board Control Software Start-up .................................................97Software Start-up—Main Window and Initial Program View ................................108Software Start-up:Wrong COM Port ...........................................................119Software Start-up:General Communication Problem ........................................1210COM Port Pop-up Dialog Window ..............................................................1311Load Setup Pop-up Dialog .......................................................................1412Main Window (with XTR108_DK_Test.txt file open)..........................................1513Resistor for 20mA Output ........................................................................1614Resistor for 4mA Output .........................................................................1615XTR108EVM Board Control Software:Summary Tab .......................................1716XTR108EVM Board Control Software:Find Resistors Tab ..................................1817XTR108EVM Board Control Software:Calibration Tab ......................................1918XTR108EVM Board Control Software:Registers 1,3,4,5Tab ............................2019XTR108EVM Board Control Software:Registers 6,7,8,9Tab ............................2120XTR108EVM Board Control Software:Registers 10,11,12,13,14,15Tab .............2221XTR108EVM Board Control Software:Calc CRC Box Checked ...........................2322Noise on DCR010505DC-to-DC Converter ...................................................2423Discrete Charge Pump on Sensor Interface Board ...........................................2524XTR108EVM Board Software:Run-Time Error ..............................................2625Control Panel Selection ..........................................................................2726Windows Control Panel ..........................................................................2727Regional and Language Options Window .....................................................2828Regional and Language Options:Advanced Tab View ......................................2829Regional and Language Options,Advanced Tab:Language for Non-UnicodePrograms Dialog ..................................................................................2930Restart PC Dialog .................................................................................3031Regional and Language Options Window:Regional Options Tab ..........................3032Regional and Language Options Window,Regional Options Tab:CustomizeRegional Options Dialog .........................................................................3133Regional and Language Options Window,Regional Options Tab,CustomizeRegional Options Dialog:Decimal Symbol Selected .........................................3234Regional and Language Options Window after Customized Regional Options areSelected ............................................................................................3235Windows Control Panel ..........................................................................3336XTR108EVM Cables ..............................................................................3437XTR108EVM PCI Interface Board .. (3538)XTR108EVM Sensor Interface Board (36)The XTR108EVM demonstration board was designed to provide an evaluation and test environment for the XTR1084-20mA two-wire transmitter.This document provides the and operate the XTR108evaluation module (EVM).For a more detailed description refer to the product datasheet available from the Texas Instruments web site at Additional support documents are listed in the XTR108EVM Parts List section this document,the acronym EVM and the demonstration board are synonymous with the XTR108EVM.This user's guide includes setup and configuration instructions,information regarding operating procedures and input/output connections,an electrical schematic,printed circuit board (PCB)layout drawings,and a parts list for the demonstration board.1.1XTR108EVM Parts List (XTR108EVM-US and XTR108EVM-EU)1.2XTR108Designer’s Kit Board Control Software -Operating System Compatibility2DescriptionDescriptionThe following documentation and devices provide information regarding Texas Instruments'integrated circuits used inXTR108EVM.Information regarding these items is available through the TI web site at DeviceXTR108PC Interface Board XTR108Sensor Interface BoardPC Cable (8-position RJ45plug to 9-position female DB9)DocumentLiterature Number XTR108EVM Software CDROM (Rev 1.0.5or newer)XTR108Designer’s Kit Board Control Software XTR108Designer's Kit Source Code XTR108EVM User’s ManualXTR108Quick Start System Reference Guide XTR108Data SheetThe board control software runs on Microsoft Windows™Win98,Win2000and WinXP.Additionally,the regional PC settings should be set to English (United States),with the decimal symbol set to a period (.).More information on issues related to changing regional settings is given in the Regional Settings section.Contact the factory for compatibility with other operating systems.The XTR108EVM key hardware consists of two boards (see Figure 1),the XTR108Sensor Interface Board and the XTR108PC Interface Board.The XTR108Board contains the XTR108,an external SOIC EEPROM,and several jumpers for ease of bridge sensor configuration.The XTR108PC Interface Board contains an RS-232serial interface,a PIC16F876Microcontroller,a dc-to-dc converter,and optical isolation circuitry.J2J2D T 1V I OT23XTR108Sensor Interface Board Overview3.1Input/Output3.2Jumper Configuration3.3XTR108and External SOIC-8EEPROM3.4Protection and FilteringXTR108Sensor Interface Board OverviewFigure 1.XTR108EVM Typical System Set-upSee the XTR108Sensor Interface Board Schematic (Figure 38)for additional information.The connections from the XTR108Sensor Interface Board to the XTR108PC Interface Board are provided through J1on the sensor interface board,a five-position plug.JUMP1,JUMP2,JUMP3,JUMP4,JUMP5,JUMP6and JUMP7allow flexibility in the configuration of the connection to an RTD.Specifically,the jumpers can be used to place the XTR108into voltage output mode or current output mode.U1is the XTR108for evaluation.A 4k-bit,external,SOIC-8,industry-standard SPI™,EEPROM,U2is also included on-board.The XTR108Sensor Interface Board is configured with components to prevent mis-wiring mishaps.D1is used to prevent damage from a reverse polarity connection.In some applications,it is desirable to bypass the FET transistor Q1,and apply power directly to the XTR108.In this case,it is important to be careful not to apply more than the 5V supply.Note that in the FET bypass mode of operation,the drop across the diode D1becomes significant.XTR108Sensor Interface Board Overview Input noise filtering of the zero resistor is provided by C1–C5.C9is used to filter the noise developed on the common-mode resistor,and a capacitor can be connected directly across the RTD.See Figure2.Figure2.XTR108EVM Sensor Interface Board Filter Configuration3.5Test Points and Miscellaneous Breadboard AreaThere are several test points,including several connections to I RET.I RET is common for most XTR108applications,and is provided for ease of measuring analog signals.Reserved areas with plated-through, standard-spacing,0.1in holes for miscellaneous proof-of-concept breadboarding as desired are provided for a given application.Most of the surface mount components have pin sockets associated with them.These pin sockets allow the replacement of a surface mount component with a through-hole component.4XTR108PC Interface Board Overview4.1Input/Output4.2RS-232Interface and PIC16F876Microcontroller4.3DC Power4.4DC-to-DC Converter and Optical Isolation of Digital SignalsXTR108PC Interface Board OverviewThe pin sockets provide good contact with the leads of a component without solder,enabling quick reconfiguration of the board for many different XTR108designs.See Figure 3.Figure 3.Pin Socket Mechanical DescriptionSee the XTR108PC Interface Board schematic (Figure 37)for additional information.The connections from the XTR108PC Interface Board to the XTR108Sensor Interface Board are provided through J4on the PC Interface Board.The PIC16F876Microcontroller (U5)is used to perform the SPI communications with the XTR108.The PIC firmware is factory-programmed;however,this source code is downloadable from the web for the benefit of engineers who want to develop custom firmware.RS-232communications are initiated via the serial port (RS-232)on the PC using Visual Basic software.The Visual Basic software source code is also downloadable from the web.As part of the serial port interface,an 75LBC241(U4)is used to translate the RS-232logic levels to 5V logic levels.DC power (7V to 10V)is applied to the XTR108PC Interface Board through J2.Diode D1is used to prevent inadvertent damage caused by a reverse polarity connection.Regulators U9and U2are used to convert the unregulated input power to a regulated 5V.A DCR01050dc-to-dc converter (U1)is used to convert the regulated 5V supply to an isolated regulated 5V supply.This isolated 5V supply provides power for all of the optical isolators U6,U3,AND U10.Optical isolation is used to allow the SPI signals to float to the ground reference of the XTR108(I RET ).Thisconfiguration prevents possible grounding issues where the loop supply (V LOOP )is not a floating supply.5Initial Setup and Check-Out5.1XTR108Sensor Interface Board –Factory JumperSettingsInitial Setup and Check-OutOne issue with the dc-to-dc converter is that it has a fairly noisy output voltage.The noise is generated by the switching action used to generate the isolated output voltage.If this noise is allowed to feed-through to the XTR108,it can significantly affect the device performance.To avoid this problem,the dc-to-dc converter is only turned on during communications to the XTR108.Normally the dc-to-dc converter is disabled and the digital I/O is disconnected using a 74HC4066FET switch (U7).Note that the power for the FET switch and its associated optically isolated control signal is derived from the XTR108.This power supply design allows these circuits to function without the power from the dc-to-dc converter.Confirm and/or set the jumpers on the XTR108Sensor Interface Board as shown in Figure 4.The desired jumper settings are also described in Table 1.Figure 4.XTR108EVM Sensor Interface Board—Factory Jumper SettingsTable 1.XTR108Sensor Interface Board—Factory Jumper SettingsJumper Position CommentsJUMP1I OUT Use Current Output mode JUMP2FET Use FET subregulator JUMP3FET Use FET subregulator JUMP4I OUT Use current output mode JUMP5I OUT Use current output modeJUMP6No load Do not connect load to voltage output JUMP7BypassBypass Voltage Mode Charge Pump5.2HardwareSet-upXTR108Board XTR108Designer's Kit Software7V Supply(DC 7V to 10V , 200mA)DC 5.3Board Control Software InstallationInitial Setup and Check-OutFor additional information,see Figure 5.Connect the XTR108Sensor Interface Board to the XTR108PC Interface Board.On the Board,connect a 7V DC (7V DC -10V DC )Lab Supply.Connect the XTR108EVM PC Cable from P PC (an RJ-45jack)on the XTR108PC Interface Board to an RS-232serial port on the test computer.Figure 5.Hardware Setup -Initial CheckoutInstall the EVM control software using this procedure:•The XTR108EVM Board Control Software is installed in the normal Microsoft Windows manner.Close all other applications.From Start button on the Windows taskbar,select Run .•In the Run dialog box,type:d:\setup ,where d is the letter designating the CD-ROM drive on the PC that contains the XTR108EVM Software CD-ROM.•Follow the on-screen prompts to install the software.•To remove the XTR108EVM application,use the Windows Control Panel utility,Add/Remove Software .Initial Setup and Check-Out 5.4Software Start-upStart the XTR108EVM Board Control Software by clicking on the XTR108DK Board Interface under Start /All Programs/XTR108Designer’s Kit as shown in Figure6.Figure6.XTR108EVM Board Control Software Start-up Initial Setup and Check-Out5.5Default Software Board Communication SetupOn initial software startup,a main window appears with a smaller pop-up window in the middle of the main window.If the initial software start-up does not look like Figure7,then proceed directly to Section5.7.Figure7.Software Start-up—Main Window and Initial Program View分销商库存信息: TIXTR108EVM。

电子元器件zrc500y03中文资料_数据手册_IC数据表

电子元器件zrc500y03中文资料_数据手册_IC数据表

DEVICE DESCRIPTIONThe ZRC500 uses a bandgap circuit design to achieve a precision micropower voltage reference of 5.0 volts. The device is available in small outline surface mount packages,ideal for applications where space saving is important, as well as packages for through hole requirements.The ZRC500 design provides a stable voltage without an external capacitor and is stable with capacitive loads. The ZRC500 is recommended for operation between 25µA and 5mA and so is ideally suited to low power and battery powered applications.Excellent performance is maintained to an absolute maximum of 25mA, however the rugged design and 20 volt processing allows the reference to withstand transient effects and currents up to 200mA. Superior switching capability allows the device to reach stable operating conditions in only a few microseconds.FEATURES•Small outline SOT23, SO8 and TO92style packages•No stabilising capacitor required •Low knee current, 19µA typical •Typical T C 30ppm/°C•Typical slope resistance 0.4Ω•± 3%, 2% and 1% tolerance •Industrial temperature range •Operating current 25µA to 5mA•Transient response, stable in less than 10µs•Optional extended current rangeAPPLICATIONS•Battery powered and portable equipment.•Instrumentation.•Test equipment.•Metering and measurement systems.VRPRECISION 5.0 VOLT LOW KNEE CURRENTVOLTAGE REFERENCEISSUE 3 - MARCH 1998SCHEMATIC DIAGRAMhttps://https:// https://https:// httpshttps://https:// https://wwwhttps://://https://www.ichunhttps://www.ichun://https://https://wwwhttps://https://httpshttps://ABSOLUTE MAXIMUM RATINGReverse Current 25mAForward Current25mAOperating Temperature -40 to 85°C Storage Temperature-55 to 125°CPower Dissipation (Tamb =25°C)SOT23330mW E-Line, 3 pin (TO92)500mW E-Line, 2 pin (TO92)500mW SO8625mWELECTRICAL CHARACTERISTICSTEST CONDITIONS (Unless otherwise stated) T amb=25°Chttps://httpshttps://https://www:// https://www.ichunhttps://www.ichunhttps://https://wwwhttps://httpsTYPICAL CHARACTERISTICShttps https://www:// https://www.ichunhttps://www.ichun https://https://www https://httpsCONNECTION DIAGRAMShttpshttps://https://www:// https://www.ichunhttps://www.ichunhttps://https://wwwhttps://https* E-Line 3 pin Reversed † E-Line 2 pin • E-Line 3 pinORDERING INFORMATIONhttpshttps://https://wwwhttps://:// https://www.ichunhttps://www.ichun:// https://https://wwwhttps://https://httpshttps://。

ZXCD1000中文资料(Zetex Semiconductors)中文数据手册「EasyDatasheet - 矽搜」

ZXCD1000中文资料(Zetex Semiconductors)中文数据手册「EasyDatasheet - 矽搜」

引脚名称
音频A
三角形 振荡器一
Dist Cosc OSC乙
三角乙 音频乙
Gnd 输出B Gnd2 9VB VCC 9VA 输出A 5V5
引脚说明
音频输入通道A 三角输入通道A
三角形输出 无连接 外部定时电容节点(设置开关频率)
三角形输出(从机ZXCD1000立体声应用) 三角输入通道B 音频输入通道B 小信号GND 通道B PWM输出驱动外部MOSFET桥梁 电力GND(输出驱动器) 内部电源轨(与去耦1μF帽) 电源输入端(最大值= 18V) 内部电源轨(与去耦1μF上限). 通道PWM输出驱动外部MOSFET桥梁 内部电源轨(与去耦1μF帽)
类似地,随着AudioA / B信号下降时,占空比 周期也相应地降低.因此,音频输入 脉冲宽度调制比较器输出.这项 原理如图3a,B,c和d.该 比较器输出进行缓冲,并用于驱动 OUTA和OUTB输出.反过来,这些驱动扬声器 负荷(与包含在PWM中音频信息
信号)通过片外桥式输出和单级
L-C滤波器网络.
(OUT A / B上升/下降)
内部铁路公差 内部铁路公差 输入阻抗 输入阻抗
偏置电平 偏置电平
振幅
条件
VCC = 12V VCC = 18V, 16V Cosc = 330pF Cosc = 330pF
空载 空载 负载电容
= 2200pF 1μF解耦 1μF解耦
极限
MIN TYP
12
16
150
200
芯片中文手册,看全文,戳
高 防 护 真 D类 音 频 放 大 器 解 决 方 案
ZXCD1000
描述
该ZXCD1000提供完整控制和调制功能以高效 率高性能D类开关音频放大器解决方案心脏.在与 ZetexHDMOS MOSFET器件相结合,ZXCD1000提供高性能 音频放大器,D类所有固有优势

zl38010中文资料_数据手册_IC数据表

zl38010中文资料_数据手册_IC数据表

1Features•Full duplex transcoder with four encode channels and four decode channels•32kbps, 24kbps and 16kbps ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40kbps), and ANSI T1.303-1989•Low power operation, 6.5mW typical•Asynchronous 4.096MHz master clock operation •SSI and ST-BUS interface options •Transparent PCM bypass •Transparent ADPCM bypass •Linear PCM code•No microprocessor control required •Simple interface to Codec devices •Pin selectable µ−Law or A-Law operation •Pin selectable ITU-T or signed magnitude PCM coding•Single 3.3Volts power supplyApplications•Pair gain•Voice mail systems•Wireless telephony systemsDescriptionThe Quad ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode functions per frame. Four 64kbps PCM octets are compressed into four 32, 24 or 16kbps ADPCM words,and four 32, 24 or 16 kbps ADPCM words are expanded into four 64kbps PCM octets. The 32, 24and 16kbps ADPCM transcoding algorithms utilized conform to ITU-T Recommendation G.726 (excluding 40kbps), and ANSI T1.303 - 1989.January 2007Ordering InformationZL38010DCE 28 Pin SOIC TubesZL38010DCF 28 Pin SOIC Tape & Reel ZL38010DCE128 Pin SOIC**TubesZL38010DCF128 Pin SOIC**Tape & Reel**Pb Free Matte Tin-40°C to +85°CZL38010Low Power Quad ADPCM TranscoderData SheetFigure 1 - Functional Block DiagramADPCM I/OPCM I/OControl DecodeVDD VSS PWRDN IC MS1MS2A/µFORMAT MS5MS4MS3MS6LINEAR SELTimingADPCMi ADPCMoENB1ENB2/F0odBCLK F0i MCLK C2o EN1EN2PCMo1PCMi1PCMo2PCMi2Full Duplex Quad TranscoderZL38010Data SheetSwitching, on-the-fly, between 32kbps and 24kbps ADPCM, is possible by controlling the appropriate mode select (MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to facilitate external DSP functions.Change SummaryChanges from October 2005 Issue to January 2007 Issue.Figure 2 - Pin ConnectionsPin Description Page ItemChange1Ordering Information BoxAdded Pb Free part numbers.Pin #Name Description1EN1Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance.2MCLKMaster Clock (input). This is a 4.096MHz (minimum) input clock utilized by thetranscoder function; it must be supplied in both ST-BUS and SSI modes of operation. In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is also used to control the data I/O flow on the PCM and ADPCM input/output pins according to ST-BUS requirements.In SSI mode this master clock input is derived from an external source and may beasynchronous with respect to the 8kHz frame. MCLK rates greater than 4.096MHz are acceptable in this mode since the data I/O rate is governed by BCLK.3F0i Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI operation is enabled by connecting this pin to V SS .4C2o2.048MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input divided by two, inverted, and synchronized to F0i. This output is high-impedance during SSI operation.12345678910111213141516171819202827262524232221MS1VDD MS3ICMS4FORMAT MS2PWRDN ADPCMi ADPCMo MS5MS6EN2PCMo1BCLK PCMi1LINEAR ENB2/F0odVSS C2o MCLK F0i PCMi2ENB1PCMo2EN1SEL A/µZL38010Data SheetPin #Name Description5BCLK Bit Clock (Input). 128kHz to 4096kHz bit clock input for both PCM and ADPCM ports;used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This inputmust be tied to V SS for ST-BUS operation.6PCMo1Serial PCM Stream 1 (Output). 128kbps to 4096kbps serial companded/linear PCM out-put stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out byMCLK divided by two in ST-BUS mode. See Figure 14.7PCMi1Serial PCM Stream 1 (Input). 128kbps to 4096kbps serial companded/linear PCM input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the3/4 bit position of MCLK in ST-BUS mode. See Figure 14.8V SS Digital Ground. Nominally 0 volts9LINEAR Linear PCM Select (Input). When tied to V DD the PCM I/O ports (PCM1,PCM2) are 16-bit linear PCM. Linear PCM operates only at a bit rate of 2048kbps. Companded PCM isselected when this pin is tied to V SS. See Figure 5 & Figure 8.10ENB2/F0od PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. SeeFigure 4 & Figure 6.ST-BUS operation: F0od(Output). This pin is a delayed frame strobe output. When LIN-EAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles afterF0i and when LINEAR = 1 at 128 C4 clock cycles after F0i. See Figures 7, 8, 9 & 14.11ENB1PCM B-Channel Enable Strobe 1 (Input).SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. Avalid 8-bit strobe must be present at this input for SSI operation.ST-BUS operation: When tied to V SS transparent bypass of the ST-BUS D- and C- chan-nels is enabled. When tied to V DD the ST-BUS D-channel and C-channel output timeslotsare forced to a high-impedance state.12PCMo2Serial PCM Stream 2 (Output). 128kbps to 4096kbps serial companded/linear PCM out-put stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divid-ed by two in ST-BUS mode. See Figure 14.13PCMi2Serial PCM Stream 2 (Input). 128kbps to 4096kbps serial companded/linear PCM input stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the3/4 bit position of MCLK in ST-BUS mode. See Figure 14.14SEL SELECT (Input).PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operationand when SEL=1 the PCM2 port is selected for PCM bypass operation.See Figure 6 & Figure 9.16kbps transcoding mode:SSI Operation - in 16kbps transcoding mode, the ADPCM words are assigned to the I/Otimeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.ST-BUS operation- in 16kbps transcoding mode, the ADPCM words are assigned to theB2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.ZL38010Data SheetAll unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt trigger compatible logic levels.All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).15A/µA-Law/µ−Law Select (Input). This input pin selects µ−Law companding when set to logic 0, and A-Law companding when set to logic 1. This control is for all channels.This input is ignored in Linear mode during which it may be tied to V SS or V DD .16FORMATFORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude PCM coding when low. This control is for all channels.This input is ignored in Linear mode during which it may be tied to V SS or V DD .17PWRDN Power-down (Input). An active low reset forcing the device into a low power mode where all outputs are high-impedance and device operation is halted. 18IC Internal Connection (Input). Tie to V SS for normal operation.192021MS1MS2MS3Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders.MS3MS2MS1MODE 00032kbps ADPCM 00124kbps ADPCM 01016kbps ADPCM in EN1/ENB1 when SEL=0in EN2/ENB2 when SEL=1011ADPCM Bypass for 32kbps and 24kbps 100ADPCM Bypass for 16kbps 101PCM Bypass (64kbps) to PCM1 if SEL=0, PCM2 if SEL=1110Algorithm reset (ITU-T optional reset)111ADPCMo disable 22V DD Positive Power Supply. Nominally 3.3Volts +/-10%23ADPCMiSerial ADPCM Stream (Input). 128kbps to 4096kbps serial ADPCM word input stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on the 3/4 bit edge of MCLK in ST-BUS mode.24ADPCMoSerial ADPCM Stream (Output). 128kbps to 4096kbps serial ADPCM word output stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by MCLK divided by two in ST-BUS mode.252627MS4MS5MS6Mode Selects 4, 5 and 6 (Inputs). Mode selects for all four decoders.MS6MS5MS4MODE 00032kbps ADPCM 00124kbps ADPCM 01016kbps ADPCM in EN1/ENB1 when SEL=0in EN2/ENB2 when SEL=1011ADPCM Bypass for 32kbps and 24kbps 100ADPCM Bypass for 16kbps 101PCM Bypass (64kbps) to PCM1 if SEL=0, PCM2 if SEL=1110Algorithm reset (ITU-T optional reset)111PCMo1/2 disable 28EN2Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2 PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.Pin #Name DescriptionZL38010Data Sheet Functional DescriptionThe Quad-channel ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode operations per frame. Four 64kbps channels (PCM octets) are compressed into four 32, 24 or 16kbps ADPCM channels (ADPCM words), and four 32, 24 or 16kbps ADPCM channels (ADPCM words) are expanded into four 64kbps PCM channels (PCM octets). The ADPCM transcoding algorithm utilized conforms to ITU-T recommendation G.726 (excluding 40kbps), and ANSI T1.303 - 1989. Switching on-the-fly between 32 and 24kbps transcoding is possible by toggling the appropriate mode select pins (supports T1 robbed-bit signalling). All functions supported by the device are pin selectable. The four encode functions comprise a common group controlled via Mode Select pins MS1, MS2 and MS3. Similarly, the four decode functions form a second group commonly controlled via Mode Select pins MS4, MS5 and MS6. All other pin controls are common to the entire transcoder.The device requires 6.5mWatts (MCLK= 4.096MHz) typically for four channel transcode operation. A minimum master clock frequency of 4.096MHz is required for the circuit to complete four encode channels and four decode channels per frame. For SSI operation a master clock frequency greater than 4.096MHz and asynchronous, relative to the 8kHz frame, is allowed.The PCM and ADPCM serial busses support both ST-BUS and Synchronous Serial Interface (SSI) operation. This allows serial data clock rates from 128kHz to 4096kHz, as well as compatibility with Zarlink’s standard Serial Telecom BUS (ST-BUS). For ST-BUS operation, on chip channel counters provide channel enable outputs as well as a 2048kHz bit clock output which may be used by down-stream devices utilizing the SSI bus interface.Linear coded PCM is also supported. In this mode the encoders compress, four 14-bit, two’s complement (S,S,S,12,...,1,0), uniform PCM channels into four 4, 3 or 2 bit ADPCM channels. Similarly, the decoder expands four 4, 3 or 2 bit ADPCM channels into four 16-bit, two’s complement (S,14,...,1,0), uniform PCM channels. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbps.ZL38010Data Sheet Serial (AD)PCM Data I/OSerial data transfer to/from the Quad ADPCM transcoder is provided through one ADPCM and two PCM ports (ADPCMi, ADPCMo, PCMi1, PCMo1, PCMi2, PCMo2). Data is transferred through these ports according to either ST-BUS or SSI requirements. The device determines the mode of operation by monitoring the signal applied to the F0i pin. When a valid ST-BUS frame pulse (244nSec low going pulse) is applied to the F0i pin the transcoder will assume ST-BUS operation. If F0i is tied continuously to V SS the transcoder will assume SSI operation. Pin functionality in each of these modes is described in the following sub-sections.ST-BUS ModeDuring ST-BUS operation the C2o, EN1, EN2 and F0od outputs become active and all serial timing is derived from the MCLK (C4) and F0i inputs while the BCLK input is tied to V SS. (See Figures 7, 8 & 9.)Basic Rate “D” and “C” ChannelsIn ST-BUS mode, when ENB1 is brought low, transparent transport of the ST-BUS "Basic Rate D- and C-channels" is supported through the PCMi1 and PCMo1 pins. This allows a microprocessor controlled device, connected to the PCMi/o1 pins, to access the "D" and "C" channels of a transmission device connected to the ADPCMi/o pins. When ENB1 is brought high, the “D” and “C” channel outputs are tristated. Basic Rate “D” and “C” channels are not supported in LINEAR mode.(See Figure 7.)SSI ModeDuring SSI operation the BCLK, ENB1 and ENB2/F0od inputs become active. The C2o, EN1, and EN2 outputs are forced to a high-impedance state except during LINEAR operation during which the EN1 output remains active. (See Figures 4, 5 & 6.)The SSI port is a serial data interface, including data input and data output pins, a variable rate bit clock input and two input strobes providing enables for data transfers. There are three SSI I/O ports on the Quad ADPCM; the PCMi/o1 PCM port, the PCMi/o2 PCM port, and the ADPCMi/o port. The two PCM ports may transport 8-bit companded PCM or 16-bit linear PCM. The alignment of the channels is determined by the two input strobe signals ENB1 and ENB2/F0od. The bit clock (BCLK) and input strobes (ENB1 and ENB2/F0od) are common for all three of the serial I/O ports. BCLK can be any frequency between 128kHz and 4096kHz synchronized to the input strobes. BCLK may be discontinuous outside of the strobe boundaries except when LINEAR=1. In LINEAR mode, BCLK must be 2048kHz and continuous for 64 cycles after the ENB1 rising edge and for the duration of ENB2/F0od. Mode Select Operation (MS1, MS2, MS3, MS4, MS5, MS6)Mode Select pins MS1, MS2 and MS3 program different bit rate ADPCM coding, bypass, algorithmic reset and disable modes for all four encoder functions simultaneously. When 24kbps ADPCM mode is selected bit 4 is unused while in 16kbps ADPCM mode all ADPCM channels are packed contiguously into one 8-bit octet. Mode Select pins MS4, MS5 and MS6 operate in the same manner for the four decode functions. The mode selects must be set up according to the timing constraints illustrated in Figures 16 and 17.32 kbps ADPCM ModeIn 32kbps ADPCM mode, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed into four 4-bit ADPCM words on ADPCMo. Conversely, the 4-bit ADPCM words of the B1, B2, B3 and B4 channels from ADPCMi are expanded into four 8-bit PCM octets on PCMo1 and PCMo2. The 8-bit PCM octets (A-Law or µ-Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are transferred most significant bit first starting with I1 and ending with I4 (See Figures 4 & 7). Reference ITU-T G.726 for I-bit definitions.ZL38010Data Sheet24 kbps ADPCM ModeIn 24kbps mode PCM octets are transcoded into 3-bit words rather than the 4-bit words utilized in 32kbps ADPCM. This is useful in situations where lower bandwidth transmission is required. Dynamic operation of the mode select control pins will allow switching from 32kbps mode to 24kbps mode on a frame by frame basis. The 8 bit PCM octets (A-Law or µ-Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are transferred most significant bit first starting with I1 and ending with I3 (I4 becomes don’t care). (See Figures 4 & 7.)16 kbps ADPCM ModeWhen SEL is set to 0, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed into four 2-bit ADPCM words on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS mode. Similarly, the four 2-bit ADPCM words on ADPCMi are expanded into four 8-bit PCM octets (on PCMo1 and PCMo2) during the ENB1/B1 timeslot. (See Figures 4 & 7.)When SEL is set to 1, The same conversion takes place as described when SEL = 0 except that the ENB2/B2 timeslots are utilized.A-Law or µ-Law 8-bit PCM are received and transmitted most significant bit first starting with b7 and ending with b0. ADPCM data are most significant bit first starting with I1 and ending with I2.ADPCM BYPASS (32 and 24 kbps)In ADPCM bypass mode the B1 and B2 channel ADPCM words are bypassed (with a two-frame delay) to/from the ADPCM port and placed into the most significant nibbles of the PCM1/2 port octets. Note that the SEL pin performs no function for these two modes (See Figures 6 & 9). LINEAR, FORMAT and A/µ pins are ignored in bypass mode. In 32kbps ADPCM bypass mode, Bits 1 to 4 of the B1, B2, B3 and B4 channels from PCMi1 and PCMi2 are transparently passed, with a two frame delay, to the same channels on ADPCMo. In the same manner, the B1, B2, B3 and B4 channels from ADPCMi are transparently passed, with a two frame delay, to the same channels on PCMo1 and PCMo2 pins. Bits 5 to 8 are don’t care. This feature allows two voice terminals, which utilize ADPCM transcoding, to communicate through a system without incurring unnecessary transcode conversions. This arrangement allows byte-wide or nibble-wide transport through a switching matrix.24kbps ADPCM bypass mode is the same as 32 kbps mode bypass excepting that only bits 1 to 3 are bypassed and bits 4 to 8 are don’t care.ADPCM BYPASS (16 kbps)When SEL is set to 0, only bits 1 and 2 of the B1, B2, B3 and B4 PCM octets (on PCMi1 and PCMi2) are bypassed, with a two frame delay, to the same channels on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS mode. Similarly, the four 2-bit ADPCM words on ADPCMi are transparently bypassed, with a two frame delay, to PCMo1 and PCMo2 during the ENB1 or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6 & 9.)When SEL is set to 1, the same bypass occurs as described when SEL = 0 except that the ENB2 or B2 timeslots are utilized.LINEAR, FORMAT and A/µ pins are ignored in bypass mode.ZL38010Data SheetPCM BYPASSWhen SEL is set to 0, the B1 and B2 PCM channels on PCMi1 are transparently passed, with a two-frame delay, to the same channels on the ADPCMo. Summarily, the two 8-bit words which are on ADPCMi are transparently passed, with a two-frame delay, to channels B1 and B2 of PCMo1 while PCMo2 is set to a high-impedance state.(See Figures 6 & 9.)When SEL is set to 1, the B3 and B4 channels on PCMi2 are transparently passed, with a two frame delay, to the same channels on ADPCMo. Similarly, the two 8-bit words which are on ADPCMi are transparently passed, with a two-frame delay, to channels B3 and B4 of PCMo2. In this case PCMo1 is always high-impedance if ENB1 = 0. If ENB1 = 1 during ST-BUS operation then the D and C channels are active on PCMo1.LINEAR, FORMAT and A/µ pins are ignored in bypass mode.Algorithm Reset ModeWhile an algorithmic reset is asserted the device will incrementally converge its internal variables to the 'Optional reset values' stated in G.726. Algorithmic reset requires that the master clock (MCLK) and frame pulse (ENB1/2 or F0i) remain active and that the reset condition be valid for at least four frames. Note that this is not a power down mode; see PWRDN for this function.ADPCMo & PCMo1/2 DisableWhen the encoders are programmed for ADPCMo disable (MS1 to MS3 set to 1) the ADPCMo output is set to a high impedance state and the internal encode function remains active. Therefore convergence is maintained. The decode processing function and data I/O remain active.When the decoders are programmed for PCMo1/2 disable (MS4 to MS6 set to 1) the PCMo1/2 outputs are high impedance during the B Channel timeslots and also, during ST-BUS operation, the D and C channel timeslots according to the state of ENB1. Therefore convergence is maintained. The encode processing function and data I/O remain active.Whenever any combination of the encoders or decoders are set to the disable mode the following outputs remain active. A) ST-BUS mode: ENB2/F0od, EN1, EN2 and C2o. Also the “D” and “C” channels from PCMo1 and ADPCMo remain active if ENB1 is set to 0. If ENB1 is brought high then PCMo1 and ADPCMo are fully tri-stated. B) SSI mode: When used in the 16-bit linear mode, only the EN1 output remains active. For complete chip power down see PWRDN.ZL38010Data Sheet Other Pin Controls16 Bit Linear PCMSetting the LINEAR pin to logic one causes the device to change to 16-bit linear (uniform) PCM transmission on the PCMi/o1 and PCMi/o2 ports. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbps and all decode and encode functions are affected by this pin. In SSI mode, the input channel strobes ENB1 and ENB2/F0od remain active for 8 cycles of BCLK for an ADPCM transfer. The EN1 output is high for one BCLK period at the end of the frame (i.e., during the 256th BCLK period). In ST-BUS mode, the output strobes EN1 and ENB2/F0od are adjusted to accommodate the required PCM I/O streams. The EN1 output becomes a single bit high true pulse during the last clock period of the frame (i.e., the 256th bit period) while ENB2/F0od becomes a delayed, low true frame-pulse (F0od) output occurring during the 64th bit period after the EN1 rising edge.Linear PCM on PCMi1 and PCMi2, are received as 14-bit, two’s complement data with three bits of sign extension in the most significant positions (i.e., S,S,S,12,...1,0) for a total of 16 bits. The linear PCM data transmitted from PCMo1 and PCmo2 are 16-bit, two’s complement data with one sign bit in the most significant position (i.e., S,14,13,...1,0)32 and 24 kbps ADPCM modeIn 32kbps and 24kbps linear mode, the 16-bit uniform PCM dual-octets of the B1, B2, B3 and B4 channels (from PCMi1 and PCMi2) are compressed into four 4-bit words on ADPCMo. The four 4-bit ADPCM words of the B1, B2, B3 and B4 channels from ADPCMi are expanded into four 16-bit uniform PCM dual-octets on PCMo1 and PCMo2. 16-bit uniform PCM are received and transmitted most significant bit first starting with b15 and ending with b0. ADPCM data are transferred most significant bit first starting with I1 and ending with I4 for 32kbps and ending with I3 for 24kbps operation (i.e., I4 is don’t care).(See Figures 5 & 8.)16 kbps ADPCM modeWhen SEL is set to 0, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB1 time-slot in SSI mode and during the B1 timeslot in ST-BUS mode. When SEL is set to 1, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB2 timeslot in SSI mode and during the B2 timeslot in ST-BUS mode. (See Figures 5 & 8.)PCM Law Control (A/µ, FORMAT)The PCM companding/coding law invoked by the transcoder is controlled via the A/µ and FORMAT pins. ITU-T G.711 companding curves, µ-Law and A-Law, are selected by the A/µ pin (0=µ-Law; 1=A-Law). Per sample, digital code assignment can conform to ITU-T G.711 (when FORMAT=1) or to Sign-Magnitude coding (when FORMAT=0). Table 1 illustrates these choices.ZL38010Data SheetTable 1 - Companded PCMPower DownSetting the PWRDN pin low will asynchronously cause all internal operation to halt and the device to go to a power down condition where no internal clocks are running. Output pins C2o, EN1, EN2, PCMo1, PCMo2 and ADPCMo and I/O pin F0od/ENB2 are forced to a high-impedance state. Following the reset (i.e., PWRDN pin brought high)and assuming that clocks are applied to the MCLK and BCLK pins, the internal clocks will still not begin to operate until the first frame alignment is detected on the ENB1 pin for SSI mode or on the F0i pin for ST-BUS mode. The C2o clock and EN1, EN2 pins will not start operation until a valid frame pulse is applied to the F0i pin. If the F0i pin remains low for longer than 2 cycles of MCLK then the C2o pin will top toggling and will stay low. If the F0i pin is held high then the C2o pin will continue to operate. In ST-BUS mode the EN1 and EN2 pins will stop toggling if the frame pulse (F0i) is not applied every frame.Master Clock (MCLK)A minimum 4096kHz master clock is required for execution of the transcoding algorithm. The algorithm requires 512 cycles of MCLK during one frame for proper operation. For SSI operation this input, at the MCLK pin, may be asynchronous with the 8kHz frame provided that the lowest frequency and deviation due to clock jitter still meets the strobe period requirement of a minimum of 512 t C4P - 25%t C4P (see Figure 3). For example, a system producing large jitter values can be accommodated by running an over-speed MCLK that will ensure a minimum 512 MCLK cycles per frame is obtained. The minimum MCLK period is 61nSec, which translates to a maximum frequency of 16.384MHz. Extra MCLK cycles (>512/frame) are acceptable since the transcoder is aligned by the appropriate strobe signals each frame.Figure 3 - MCLK Minimum RequirementFORMAT01PCM CodeSign-Magnitude A/µ = 0 or 1ITU-T (G.711)(A/µ = 0)(A/µ = 1)+ Full Scale 1111 11111000 00001010 1010+ Zero 1000 00001111 11111101 0101- Zero 0000 00000111 11110101 0101- Full Scale0111 11110000 00000010 1010ENB1MCLK512 t C4P - 25%t C4P MinimumZL38010Data Sheet Bit Clock (BCLK)For SSI operation the bit rate, for both ADPCM and PCM ports, is determined by the clock input at BCLK. BCLK must be eight periods in duration and synchronous with the 8kHz frame inputs at ENB1 and ENB2. Data is sampled at PCMi1/2 and at ADPCMi concurrent with the falling edge of BCLK. Data is available at PCMo1/2 and ADPCMo concurrent with the rising edge of BCLK. BCLK may be any rate between 128kHz and 4096kHz. For ST-BUS operation BCLK is ignored (tie to V SS) and the bit rate is internally set to 2048kbps.Figure 4 - SSI 8-Bit Companded PCM Relative TimingZL38010Data SheetFigure 5 - SSI 16-Bit Linear PCM Relative TimingZL38010Data SheetFigure 6 - SSI PCM and ADPCM Bypass Relative TimingZL38010Data SheetFigure 7 - ST-BUS 8-Bit Companded PCM Relative TimingZL38010Data SheetFigure 8 - ST-BUS 16-Bit Linear PCM Relative TimingZL38010Data SheetFigure 9 - ST-BUS PCM and ADPCM Bypass Relative TimingZL38010Data Sheet Processing Delay Through the DeviceIn order to accommodate variable rate PCM and ADPCM interfaces, the serial input and output streams require a complete frame to load internal shift registers. Internal frame alignment of the encoding/decoding functions are taken from either of the F0i or ENB1 & ENB2 input strobes depending upon the device operating mode (i.e., ST-BUS or SSI). The encoding/decoding of all channels then takes one frame to complete before the output buffers are loaded. This results in a two frame transcoding delay. The two frame delay also applies to the D and C channels and to the PCM and ADPCM bypass functions.(See Figure 10.)Note: When changing the relative positions of the ENB1 and ENB2 strobes, precaution must be taken to ensure that two conditions are met. They are:1.There must be at least 512 master clock cycles between consecutive rising edges of ENB1. This condition alsoholds true for ENB2.2.The ENB1 strobe must alternate with the ENB2 strobe.Violation of these requirements may cause noise on the output channels.Figure 10 - Data ThroughputApplicationsFigure 11 depicts an ISDN line card utilizing a ’U’ interface transceiver and ZL38010 ADPCM transcoder. This central office application implements the network end of a Pair-Gain system. Figure 12 shows Zarlink devices used to construct the remote Pair-Gain loop terminator.。

CX06833-44中文资料

CX06833-44中文资料
1.1 1.2 1.3 1.4 Overview ......................................................................................................................................................................... 1-1 Applications .................................................................................................................................................................... 1-2 Features .......................................................................................................................................................................... 1-4 1.3.1 General Modem Features ............................................................................................................................... 1-4 Technical Overview..................................................................
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ZXCT1080High voltage high-side current monitorDescriptionOrdering informationThe ZXCT1080 is a high side current sense monitor with a gain of 10 and a voltage output. Using this device eliminates the need to disrupt the ground plane when sensing a load current.The wide input voltage range of 60V down to as low as 3V make it suitable for a range of applications; including systems operating from industrial 24-28V rails and -48V rails.The separate supply pin (V CC ) allows the device to continue functioning under short circuit conditions, giving an end stop voltage at the output.The ZXCT1080 has an extended ambient operating temperature range of -40°C to 125°C enabling it to be used in a wide range of applications including automotive.Features•3V to 60V continuous high side voltage •Accurate high-side current sensing •-40 to 125°C temperature range •Output voltage scaling x10• 4.5V to 12V V CC range •Low quiescent current:•70µA supply pin •50µA I SENSE+•SOT23-5 package Applications•Industrial applications current measurement •Battery management •Over current monitor •Power management•Automotive current measurementPin connectionsTypical application circuitDevicePackage Part mark Reel size (inches)Tape width (mm)Quantity perreelZXCT1080E5TASOT23-51080783000https://Absolute maximum ratingsContinuous voltage on S- and S+-0.6 and 65V Voltage on all other pins-0.6V and +14VDifferential sense voltage, V SENSE 800mV Operating temperature -40 to 125°C Storage temperature-55 to 150°C Maximum junction temperature 125°CPackage power dissipation300mW * at T A = 25°COperation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability.V SENSE is defined as the differential voltage between S+ and S- pins.*Assumes ⍜JA = 420°C/WRecommended operating conditionsPin function tableParameterMin.Max.Units V IN Common-mode sense+ input range 360V V CCSupply voltage range4.512V V SENSE Differential sense input voltage range 00.15V V OUT Output voltage range 0 1.5V T AAmbient temperature range-40125°CPin Name Description1V CC This is the analogue supply and provides power to internal circuitry 2GND Ground pin3OUT Output voltage pin. NMOS source follower with 20µA bias to ground 4S+This is the positive input of the current monitor and has an input range from 60V down to 3V. The current through this pin varies with differential sense voltage5S-This is the negative input of the current monitor and has an input range from 60V down to 3Vhttps://Electrical characteristicsTest conditions T A = 25°C, V IN = 12V, V CC = 5 V, V SENSE (a) = 100mV unless otherwise stated.NOTES:(a)V SENSE = "V SENSE+" - "V SENSE-"(b)The ZXCT1080 operates from a positive power rail and the internal voltage-current converter current flow is unidirectional; these result in the output offset voltage for V SENSE = 0V always being positive.(c)For V SENSE > 10mV, the internal voltage-current converter is fully linear. This enables a true offset to be defined and used. V O(10) is expressed as the variance about an output voltage of 100mV>(d)Temperature dependent measurements are extracted from characterization and simulation results.(e)All Min and Max specifications over full temperature range are guaranteed by design and characterisationSymbol ParameterConditions T A Min (e).Typ.Max (e).Units I CC V CC supply current V CC = 12V, V SENSE (a) = 0V 25°C 4080120µAfull range 145I S+S+ input current V SENSE (a) = 0V25°C 152742µA full range 60I S-S- input current25°C 154080nA V O(0)Zero V SENSE (a) error (b)25°C 035mV V O(10)Output offset voltage (c)V SENSE (a) = 10mV 25°C -25+25mV full range -55+55Gain⌬V OUT /⌬V SENSE (a)V SENSE (a) = 10mV to150mV 25°C 9.91010.1V/V full range9.810.2V OUT TC (d)V OUT variation withtemperature 30ppm/°C Acc Total output error -33%I OH Output source current⌬V OUT = -30mV 1mA I OL Output sink current⌬V OUT = +30mV20µA PSRR V CC supply rejection ratioV CC = 4.5V to 12V 5460dB CMRR Common-mode sense rejection ratio V IN = 60V to 3V 6880dB BW-3dB small signal bandwidthV SENSE (a) (AC) = 10mV PP500kHz https://Typical characteristicsTest conditions unless otherwise stated: T A = 25°C, V CC = 5V, V SENSE+ =12V, V SENSE = 100mVTypical characteristicsTest conditions unless otherwise stated: T A = 25°C, V CC = 5V, V SENSE+ =12V, V SENSE = 100mVTypical characteristicsTest conditions unless otherwise stated: T A = 25°C, V CC = 5V, V SENSE+ =12V, V SENSE = 100mVhttps://Application informationThe ZXCT1080 has been designed to allow it to operate with 5V supply rails while sensing common mode signals up to 60V. This makes it well suited to a wide range of industrial and power supply monitoring applications that require the interface to 5V systems while sensing much higher voltages.To allow this its V CC pin can be used independently of S+.Figure 1 shows the basic configuration of the ZXCT1080.Figure 1Typical configuration of ZXCT1080Load current from the input is drawn through R SENSE developing a voltage V SENSE across the inputs of the ZXCT1080.The internal amplifier forces V SENSE across internal resistance R GT causing a current to flow through MOSFET M1. This current is then converted to a voltage by R G . A ratio of 10:1 between R G and R GT creates the fixed gain of 10. The output is then buffered by the unity gain buffer.The gain equation of the ZXCT1080 is:The maximum recommended differential input voltage, V SENSE , is 150mV; it will howeverwithstand voltages up to 800m ⍀. This can be increased further by the inclusion of a resistor, R LIM ,between S- pin and the load; typical value is of the order of 10k .V OUT I L R SENSE R GRGT---------1×I L R SENSE ×10×==https://Figure 2Protection/error sources for ZXCT1080Capacitor C D provides high frequency transient decoupling when used with R LIM ; typical values are of the order 10pFFor best performance R SENSE should be connected as close to the S+ (and SE NSE ) pins;minimizing any series resistance with R SENSE .When choosing appropriate values for R SENSE a compromise must be reached between in-line signal loss (including potential power dissipation effects) and small signal accuracy.Higher values for R SENSE gives better accuracy at low load currents by reducing the inaccuracies due to internal offsets. For best operation the ZXCT1080 has been designed to operate with V SENSE of the order of 50mV to 150mV.Current monitors' basic configuration is that of a unipolar voltage to current to voltage converter powered from a single supply rail. The internal amplifier at the heart of the current monitor may well have a bipolar offset voltage but the output cannot go negative; this results in current monitors saturating at very low sense voltages.As a result of this phenomenon the ZXCT1080 has been specified to operate in a linear manner over a V SENSE range of 10mV to 150mV range, however it will still be monotonic down to VSENSE of 0V.It is for this very reason that Zetex has specified an input offset voltage (V O(10)) at 10mV. The output voltage for any V SENSE voltage from 10mV to 150mV can be calculated as follows:Alternatively the load current can be expressed as:V OUT V SENSE ()xG V O 10()+=I L V OUT V O 10()–()GxR SENSE------------------------------------------=https://Package details - SOT23-5Note: Controlling dimensions are in millimeters. Approximate dimensions are provided in inchesDIM MillimetersInchesMin.Max.Min.Max.A - 1.00-0.0393A10.010.100.00030.0039A20.840.900.03300.0354b 0.300.450.01180.0177c 0.120.200.00470.0078D 2.90 BSC 0.114 BSCE 2.80 BSC 0.110 BSC E1 1.60 BSC 0.062 BSC e 0.95 BSC 0.0374 BSC e1 1.90 BSC0.0748 BSCL 0.300.500.01180.0196L20.25 BSC 0.010 BSC a°4°12°4°12°https://ZXCT1080DefinitionsProduct changeZetex Semiconductors reserves the right to alter, without notice, specifications, design, price or conditions of supply of any product or service. Customers are solely responsible for obtaining the latest relevant information before placing orders.Applications disclaimerThe circuits in this design/application note are offered as design ideas. It is the responsibility of the user to ensure that the circuit is fit for the user’s application and meets with the user’s requirements. No representation or warranty is given and no liability whatsoever is assumed by Zetex with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Zetex does not assume any legal responsibility or will not be held legally liable (whether in contract,tort (including negligence), breach of statutory duty, restriction or otherwise) for any damages, loss of profit, business, contract,opportunity or consequential loss in the use of these circuit applications, under any circumstances.Life supportZetex products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Zetex Semiconductors plc. As used herein:A. Life support devices or systems are devices or systems which:1.are intended to implant into the bodyor 2.support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in thelabelling can be reasonably expected to result in significant injury to the user.B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected tocause the failure of the life support device or to affect its safety or effectiveness.ReproductionThe product specifications contained in this publication are issued to provide outline information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned.Terms and ConditionsAll products are sold subjects to Zetex’ terms and conditions of sale, and this disclaimer (save in the event of a conflict between the two when the terms of the contract shall prevail) according to region, supplied at the time of order acknowledgement.For the latest information on technology, delivery terms and conditions and prices, please contact your nearest Zetex sales office.Quality of productZetex is an ISO 9001 and TS16949 certified semiconductor manufacturer.To ensure quality of service and products we strongly advise the purchase of parts directly from Zetex Semiconductors or one of our regionally authorized distributors. For a complete listing of authorized distributors please visit: /salesnetworkZetex Semiconductors does not warrant or accept any liability whatsoever in respect of any parts purchased through unauthorized sales channels.ESD (Electrostatic discharge)Semiconductor devices are susceptible to damage by ESD. Suitable precautions should be taken when handling and transporting devices.The possible damage to devices depends on the circumstances of the handling and transporting, and the nature of the device. The extent of damage can vary from immediate functional or parametric malfunction to degradation of function or performance in use over time.Devices suspected of being affected should be replaced.Green complianceZetex Semiconductors is committed to environmental excellence in all aspects of its operations which includes meeting or exceeding regulatory requirements with respect to the use of hazardous substances. Numerous successful programs have been implemented to reduce the use of hazardous substances and/or emissions.All Zetex components are compliant with the RoHS directive, and through this it is supporting its customers in their compliance with WEEE and ELV directives.Product status key:“Preview”Future device intended for production at some point. Samples may be available“Active”Product status recommended for new designs“Last time buy (LTB)”Device will be discontinued and last time buy period and delivery is in effect“Not recommended for new designs”Device is still in production to support existing designs and production“Obsolete”Production has been discontinuedDatasheet status key:“Draft version”This term denotes a very early datasheet version and contains highly provisional information, which may change in any manner without notice.“Provisional version”This term denotes a pre-release datasheet. It provides a clear indication of anticipated performance.However, changes to the test conditions and specifications may occur, at any time and without notice.“Issue”This term denotes an issued datasheet containing finalized specifications. However, changes tospecifications may occur, at any time and without notice.https://。

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