MC14069UB

(VO = 1.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Drive Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 9.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 13.5 Vdc)
(1/6 of circuit shown)
Figure 2. Circuit Schematic
PULSE GENERATOR
VDD
14 OUTPUT
INPUT
7 VSS
CL
20 ns
INPUT tPHL
OUTPUT
90% 50% 10%
90% 50% 10%
tTHL Figure 4. Switching Time Test Circuit and Waveforms
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbo VDD
− 55_C
25_C
125_C
l
Vdc Min
Max
Min
Typ (2)
Max
Min
Max
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = VDD
MARKING DIAGRAMS 14
MC14069UBCP AWLYYWWG
1
14
SOIC−14 D SUFFIX CASE 751A
14069UG AWLYWW
1
TSSOP−14 DT SUFFIX CASE 948G
14 14
069U ALYWG
G
1
SOEIAJ−14 F SUFFIX CASE 965
• Triple Diode Protection on All Inputs • Pin−for−Pin Replacement for CD4069UB • Meets JEDEC UB Specifications • Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
SOIC−14
SOIC−14 (Pb−Free)
55 Units / Rail
MC14069UBDR2
SOIC−14
MC14069UBDR2G MC14069UBDTR2
SOIC−14 (Pb−Free)
TSSOP−14*
2500 Units / Tape & Reel
MC14069UBDTR2G
TSSOP−14*
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays.
(VO = 13.5 Vdc)
“0” Level VIL
5.0
−
1.0
−
2.25
1.0
−
1.0
10
−
2.0
−
4.50
2.0
−
2.0
15
−
2.5
−
6.75
2.5
−
2.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 0.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.0 Vdc)
8 OUT 4
Figure 1. Pin Assignment
1
2
3
4
VDD = PIN 14 VSS = PIN 7
5
6
9
8
INPUT*
VDD OUTPUT
11
10
13
12
Figure 3. Logic Diagram
VSS *Double diode protection on all inputs not shown
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
“0” Level VOL
5.0
−
0.05
−
10
−
0.05
−
15
−
0.05
−
0
0.05
−
0.05
0
0.05
−
0.05
0
0.05
−
0.05
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = 0
“1” Level VOH 5.0 4.95
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

PDIP−14 P SUFFIX CASE 646
−
4.95
5.0
10 9.95
−
9.95
10
15 14.95
−
14.95
15
−
4.95
−
−
9.95
−
−
14.95
−
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 4.5 Vdc) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 9.0 Vdc)
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD.
1
October, 2006 − Rev. 8
Publication Order Number: MC14069UB/D
MC14069UB
IN 1 1 OUT 1 2
IN 2 3 OUT 2 4
IN 3 5 OUT 3 6
VSS 7
14 VDD 13 IN 6 12 OUT 6 11 IN 5 10 OUT 5 9 IN 4
“1” Level VIH
5.0
4.0
−
4.0
2.75
10
8.0
−
8.0
5.50
15 12.5
−
12.5
8.25
IOH
Source
5.0 – 3.0
−
– 2.4
– 4.2
5.0 – 0.64
−
– 0.51 – 0.88
10 – 1.6
−
– 1.3 – 2.25
15 – 4.2
−
– 3.4
– 8.8
−
*This package is inherently Pb−Free.
2
MC14069UB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
± 10
mA
PD Power Dissipation, per Package (Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range