FPGA读写i2c_verilog

parameterADD1= 4'd2;
parameterACK1= 4'd3;
parameterADD2= 4'd4;
parameterACK2= 4'd5;
parameterSTART2= 4'd6;
parameterADD3= 4'd7;
parameterACK3= 4'd8;
parameterDATA= 4'd9;
`define SCL_NEG(cnt==3'd2)//cnt=2:scl下笛?`define SCL_LOW(cnt==3'd3)//cnt=3:scl偷缙街屑?用于数据变化
always @ (posedge clk or negedge rst_n)
if(!rst_n) scl_r <= 1'b0;
end
ACK2:begin
if(/*!sda*/`SCL_NEG) begin//从机响应信号
if(!sw1_r) begin
cstate <= DATA;//写操作
db_r <= `WRITE_DATA;//写入的数据
end
else if(!sw2_r) begin
db_r <= `DEVICE_READ;//送器件地址（读操作），特定地址读需要执行该步骤以下操作
default: ;
endcase
//sda_r <= db_r[4'd7-num];//送EEPROM地址（高bit开始）
cstate <= ADD2;
end
end
//else if(`SCL_POS) db_r <= {db_r[6:0],1'b0};//器件地址左移1bit
else cstate <= ADD2;
);
input clk;// 50MHz
input rst_n;//复位信号，低有效
input sw1,sw2;//按键1、2,(1按下执行写入操作，2按下执行读操作)
output scl;// 24C02的时钟端口
inout sda;// 24C02的数据端口
output[7:0] dis_data;//数码管显示的数据
cstate <= START2;//读操作
end
end
else cstate <= ACK2;//等待从机响应
end
START2: begin//读操作起始位
if(`SCL_LOW) begin
sda_link <= 1'b1;//sda作为output
sda_r <= 1'b1;//拉高数据线sda
sw2_r <= 1'b1;
end
else if(cnt_20ms == 20'hfffff) begin
sw1_r <= sw1;//按键1值锁存
sw2_r <= sw2;//按键2值锁存
end
//---------------------------------------------
//分频部分
4'd1: sda_r <= db_r[6];
4'd2: sda_r <= db_r[5];
4'd3: sda_r <= db_r[4];
4'd4: sda_r <= db_r[3];
4'd5: sda_r <= db_r[2];
4'd6: sda_r <= db_r[1];
4'd7: sda_r <= db_r[0];
4'd3: sda_r <= db_r[4];
4'd4: sda_r <= db_r[3];
4'd5: sda_r <= db_r[2];
4'd6: sda_r <= db_r[1];
4'd7: sda_r <= db_r[0];
default: ;
endcase
//sda_r <= db_r[4'd7-num];//送器件地址，从高位开始
if(!rst_n) cnt_20ms <= 20'd0;
else cnt_20ms <= cnt_20ms+1'b1;//不断计数
always @ (posedge clk or negedge rst_n)
if(!rst_n) begin
sw1_r <= 1'b1;//键值寄存鞲次唬挥屑 贪聪率奔 刀嘉?
reg[7:0] db_r;//在IIC上传送的数据寄存器
reg[7:0] read_data;//读出EEPROM的数据寄存器
//---------------------------------------------
//读、写时序
parameterIDLE= 4'd0;
parameterSTART1= 4'd1;
if(!rst_n) cnt <= 3'd5;
else begin
case (cnt_delay)
9'd124:cnt <= 3'd1;//cnt=1:scl高电平中间,用于数据采样
9'd249:cnt <= 3'd2;//cnt=2:scl下降沿
9'd374:cnt <= 3'd3;//cnt=3:scl低电平中间,用于数据变化
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
modulபைடு நூலகம் iic_com(
clk,rst_n,
sw1,sw2,
scl,sda,
dis_data
if(num==4'd8) begin
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
cstate <= IDLE;
sda_r <= 1'b1;
sda_link <= 1'b0;
num <= 4'd0;
read_data <= 8'b0000_0000;
end
else
case (cstate)
IDLE:begin
sda_link <= 1'b1;//数据线sda为input
sda_r <= 1'b1;
if(!sw1_r || !sw2_r) begin//SW1,SW2键有一个被按下
db_r <= `DEVICE_WRITE;//送器件地址（写操作）
cstate <= START1;
if(!rst_n) cnt_delay <= 9'd0;
else if(cnt_delay == 9'd499) cnt_delay <= 9'd0;//计数到10us为scl的周期，即100KHz
else cnt_delay <= cnt_delay+1'b1;//时蛹剖?
always @ (posedge clk or negedge rst_n) begin
end
else cstate <= IDLE;//没有任何键被按下
end
START1: begin
if(`SCL_HIG) begin//scl为高电平期间
sda_link <= 1'b1;//数据线sda为output
sda_r <= 1'b0;//拉低数据线sda，产生起始位信号
cstate <= ADD1;
cstate <= START2;
end
else if(`SCL_HIG) begin//scl为高电平中间
sda_r <= 1'b0;//拉低数据线sda，产生起始位信号
cstate <= ADD3;
end
else cstate <= START2;
end
ADD3:begin//送读操作地址
if(`SCL_LOW) begin
// Module Name: iic_top
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
//需要写入24C02的地址和数据
`defineDEVICE_READ8'b1010_0001//被寻址器件地址（读操作）
`define DEVICE_WRITE8'b1010_0000//被寻址器件地址（写操作）
`defineWRITE_DATA8'b1101_0001//写入EEPROM的数据
`define BYTE_ADDR8'b0000_0011//写入/读出EEPROM的地址寄存器
sda_link <= 1'b0;//sda置为高阻态(input)
cstate <= ACK1;
end
else begin
cstate <= ADD1;