P89LPC914

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飞利浦单片机选型指南

ＸＴＡＬ１／Ｐ３．１ 2
１６字节可擦除页规格。
ＣＬＫＯＵＴ／ＸＴＡＬ２／Ｐ３．０ 3
● ２个１６位定时／计数器（ＬＰＣ９０１的定时器０可作为ＰＷＭ输出）。 ● 模拟比较器：２个（ＬＰＣ９０２／９０３／９０４），１个（ＬＰＣ９０１）。
ＲＳＴ／Ｐ１．５ 4
● ２路输入的Ａ／Ｄ转换器／１个ＤＡＣ输出，可选择参考源（ＬＰＣ９０４）。
功能部件ＵＡＲＴ，ＲＴＣ，ＫＢＩ
ＡＤＣ／ＤＡＣＣＭＰＰＷＭ
１２８Ｂ
８脚
１Ｋ
功能部件ＵＡＲＴ，ＲＴＣ，ＫＢＩ
ＡＤＣ／ＤＡＣＣＭＰＰＷＭ
ＳＰＩ、Ｉ２Ｃ
１６脚１４脚
２５６Ｂ２Ｋ１Ｋ１２８Ｂ
功能部件ＵＡＲＴ，ＲＴＣ，ＫＢＩ
ＡＤＣ／ＤＡＣＣＭＰＰＷＭ
ＳＰＩ、Ｉ２ＣＩＳＰ
８Ｋ４Ｋ２５６Ｂ２０脚２Ｋ
在程序运行时改变代码。 ● ６４脚ＬＱＦＰ封装。 ● ＤＰ－９４０１开发套件。
智能卡水表／气表“单片”解决方案
Ｐ８９ＬＰＣ９１０２／９１０３／９１０７Ｆｌａｓｈ单片机
０４ ● １２８字节ＲＡＭ数据存储器。１ｋＢ可字节擦除的Ｆｌａｓｈ程序存储器，组成２５６字节扇区和１６字节擦除页规格。
13 Ｐ０．２／ＣＩＮ２Ａ／ＫＢＩ２ 12 Ｐ０．４／ＣＩＮ１Ａ／ＫＢＩ４ 11 Ｐ０．５／ＣＭＰＲＥＦ／ＫＢＩ５ 10 ＶＤＤ
9 Ｐ１．０／ＴＸＤ
8 ＣＬＫＯＵＴ／ＸＴＡＬ２／Ｐ３．０
Ｐ２．２／ＭＯＳＩ 1 ＳＰＩＣＬＫ／Ｐ２．５ 2
● Ｆｌａｓｈ保密位可防止程序被读出。 ● 在应用中编程（ＩＡＰ－Ｌｉｔｅ）和字节擦写功能使得程序存储器可用于非易
失性数据的存储。 ● 实时时钟可作为系统定时器。 ● ２个模拟比较器。可选择输入和参考源。 ● ＳＰＩ通信端口、４个键盘中断输入。 ● 选择片内振荡和片内复位时可多达１２个Ｉ／Ｏ口。 ● １４脚ＴＳＳＯＰ和ＤＩＰ封装。

P89LPC922FDH中文资料

0
plastic dual in-line package; 20 leads (300 mil) SOT146-1
3.1 Ordering options
Table 2: Part options
Type number
Flash memory
P89LPC920FDH
2 kB
P89LPC921FDH
8-bit microcontrollers with two-clock 80C51 core
3. Ordering information
Table 1: Ordering information
Type number
Package
Name
Description
Version
P89LPC920FDH TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm
s Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be conﬁgured as an interrupt.
s Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 µA (total Power-down with voltage comparators disabled).

Philips89LPC900系列单片机的低功耗分析与设计

0引言
单片机技术已在工程实践与研究中得到广泛应
用。由于用户与市场的需要 , 设计者在关心单片机系
统的高效性与可靠性同时, 越来越关心系统的低功耗
特性。一些系统由于工作条件特殊 , 需要长期在野外或
地下工作, 必须使用电池供电 (像矿井下的数据采集系
( 解放军炮兵学院五系四十四队安徽合肥 230031 )
【摘要】以基本的CMOS电路为基础, 分析了单片机的功耗组成, 总结了低功耗系统设计的一般规律。分析了 Philips89LPC900系列单片机的功耗特性。以Philips89LPC935为例, 设计了一个低功耗数据采集系统。【关键词】单片机; 低功耗设计; 数据采集【中图分类号】 TP311 【文献标识码】 A 【文章编号】 1003- 773X( 2007) 04- 0130- 02
MOS 管组成, T1是 NMOS 型驱动管 , T2 是 FMOS 型负载管 ,
两个栅极连在一起的输出端是非的逻辑关系。在稳定状态图 1 CMOS 反相器图
时, 两管总处在一个导通 , 另一个必为截止的状态 , 这
时在门电路中没有从 Vdd 到 Vss 的通路 , 电源向反相器提供的电流为截止电流, 因此功耗很小, 而在切换状
态时 , 反相器向负载电容充电 , 或负载电容向反相器充
电, 这时的功耗大大增加。因此, CMOS 电路的功耗可
分为静态功耗和动态功耗[1][2]。电路在稳定状态时功耗
为静态功耗 P 静=Vdd I, 电路在转换状态时产生动态功

P89LPC914FDH,129,P89LPC912FDH,129,P89LPC913FDH,129, 规格书,Datasheet 资料

P89LPC912/913/9148-bit microcontrollers with two-clock 80C51 core, 1 kB 3 Vﬂash with 128-byte RAMRev. 05 — 28 September 2007Product data sheet1.General descriptionThe P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages,based on a high performance processor architecture that executes instructions in two tofour clocks, six times the rate of standard 80C51 devices. Many system-level functionshave been incorporated into the P89LPC912/913/914 in order to reduce componentcount, board space, and system cost.2.Features2.1Principal featuresI 1 kB byte-erasable ﬂash code memory organized into 256B sectors and 16B pages.Single-byte erasing allows any byte(s) to be used as non-volatile data storage.I128B RAM data memory.I Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output upontimer overﬂow or to become a PWM output.I23-bit system timer that can also be used as a RTC.I Two analog comparators with selectable inputs and reference source.I Enhanced UART with fractional baud rate generator, break detect, framing errordetection, automatic address detection and versatile interrupt capabilities(P89LPC913, P89LPC914).I SPI communication port.I Internal RC oscillator (factory calibrated to±1%) option allows operation withoutexternal oscillator components.The RC oscillator option is selectable andﬁne tunable.I 2.4V to 3.6V V DD operating range. I/O pins are 5V tolerant (may be pulled up ordriven to 5.5V).I Up to 12 I/O pins when using internal oscillator and reset options.2.2Additional featuresI14-pin TSSOP packages.I A high performance 80C51 CPU provides instruction cycle times of 111ns to 222nsfor all instructions except multiply and divide when executing at 18MHz (167ns to333ns at12MHz).This is six times the performance of the standard80C51running atthe same clock frequency.A lower clock frequency for the same performance results inpower savings and reduced EMI.I In-Application Programming(IAP-Lite)and byte erase allows code memory to be usedfor non-volatile data storage.I Serial ﬂash In-Circuit Programming (ICP) allows simple production coding withcommercial EPROM programmers. Flash security bits prevent reading of sensitive application programs.I Watchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eight values.I Low voltage reset (brownout detect) allows a graceful system shutdown when powerfails. May optionally be conﬁgured as an interrupt.I Idle and two different power-down reduced power modes. Improved wake-up fromPower-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1µA (total power-down with voltage comparators disabled).I Active-LOW reset. On-chip power-on reset allows operation without external resetcomponents. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.I Conﬁgurable on-chip oscillator with frequency range options selected by userprogrammed ﬂash conﬁguration bits. Oscillator options support frequencies from 20kHz to the maximum operating frequency of 18MHz (P89LPC912, P89LPC913).I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillatorallowing it to perform an oscillator fail detect function.I Programmable port output conﬁguration options: quasi-bidirectional, open-drain,push-pull, input-only.I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value ofthe pins match or do not match a programmable pattern.I LED drive capability (20mA) on all port pins. A maximum limit is speciﬁed for theentire chip.I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10nsminimum ramp times.I Only power and ground connections are required to operate the P89LPC912/913/914when internal reset option is selected.I Four interrupt priority levels.I Four keypad interrupt inputs.I Second data pointer.I Schmitt trigger port inputs.I Emulation support.3.Product comparisonTable 1 highlights the differences between these three devices. For a complete list of device features, please see Section 2 “Features” on page 1.4.Ordering information4.1Ordering optionsTable 1.Product comparisonType numberExternal crystal pinsX2 CLKOUT T0 PWM outputSPI with SS pinSPI without SS pinUART Max f osc (MHz)TXD RXDP89LPC912X X X X ---18P89LPC913X X --X X X 18P89LPC914--XX-XX12Table 2.Ordering informationType numberPackage NameDescriptionVersion P89LPC912FDH TSSOP14plastic thin shrink small outline package; 14leads; body width 4.4mmSOT402-1P89LPC912HDH P89LPC913FDH P89LPC914FDHTable 3.Ordering optionsType number Temperature range Frequency P89LPC912FDH −40°C to +85°C 0 MHz to 18MHz P89LPC912HDH −40°C to +125°C 0 MHz to 18MHz P89LPC913FDH −40°C to +85°C 0 MHz to 18MHz P89LPC914FDH−40°C to +85°C0 MHz to 12 MHz5.Block diagramFig 1.P89LPC912 block diagram1 kB CODE FLASHSPICMP1CIN2A CIN1A CMPREFP2[5:2]P3[1:0]P1.2, P1.5P0.2, P0[6:4]MOSI SPICLK MISO T0P89LPC912002aaa472SS128 BYTE DATA RAMPORT 3CONFIGURABLE I/O PORT 2CONFIGURABLE I/OPORT 1CONFIGURABLE I/OPORT 0CONFIGURABLE I/OKEYPAD INTERRUPTWATCHDOG TIMER AND OSCILLATORPROGRAMMABLE OSCILLATOR DIVIDERCPU clockCRYST ALORRESONATORXT AL1XT AL2CONFIGURABLE OSCILLATORON-CHIP OSCILLATORPOWER MONITOR (POWER-ON RESET, BROWNOUT RESET)ANALOG COMPARATORSTIMER 0TIMER 1REAL TIME CLOCK/SYSTEM TIMERinternal busHIGH PERFORMANCEACCELERATED 2-CLOCK 80C51 CPUFig 2.P89LPC913 block diagram1kB CODE FLASHSPICMP1CIN2A CIN1A CMPREFP2.2, P2.3, P2.5P3[1:0]P1.0, P1.1, P1.5P0.2, P0[6:4]TXDRXDMOSI SPICLK MISOP89LPC913002aaa473128 BYTE DATA RAM PORT 3CONFIGURABLE I/OPORT 2CONFIGURABLE I/OPORT 1CONFIGURABLE I/OPORT 0CONFIGURABLE I/OKEYPAD INTERRUPTWATCHDOG TIMER AND OSCILLATORPROGRAMMABLE OSCILLATOR DIVIDERCPU clockCRYSTAL ORRESONA TORXT AL1XT AL2CONFIGURABLE OSCILLATORON-CHIP OSCILLATORANALOG COMP ARATORSTIMER 0TIMER 1REAL TIME CLOCK/SYSTEM TIMERUARTHIGH PERFORMANCEACCELERATED 2-CLOCK 80C51 CPUinternal busPOWER MONITOR (POWER-ON RESET, BROWNOUT RESET)Fig 3.P89LPC914 block diagram1 kB CODE FLASHSPICMP1CIN2A CIN1A CMPREFP2[5:2]P1.5, P1[2:0]P0.2, P0[6:4]MOSI SPICLK MISO T0P89LPC914002aaa474SSTXDRXD HIGH PERFORMANCEACCELERATED 2-CLOCK 80C51 CPU128 BYTE DAT A RAM PORT 2CONFIGURABLE I/O PORT 1CONFIGURABLE I/O PORT 0CONFIGURABLE I/OKEYPAD INTERRUPTWATCHDOG TIMER AND OSCILLATORPROGRAMMABLE OSCILLATOR DIVIDERCPU clockON-CHIP OSCILLATORPOWER MONITOR (POWER-ON RESET, BROWNOUT RESET)ANALOG COMP ARATORSTIMER 0TIMER 1REAL TIME CLOCK/SYSTEM TIMERUARTinternal bus6.Functional diagramFig 4.P89LPC912 functional diagramFig 5.P89LPC913 functional diagramKBI2KBI4KBI5KBI6CIN2ACIN1A CMPREF CMP1T0RSTP89LPC912MOSIMISO SS SPICLK002aaa475V DDV SSCLKOUTXTAL2XTAL1PORT 0PORT 3PORT 1PORT 2KBI2KBI4KBI5KBI6CIN2ACIN1A CMPREF CMP1TXD RXDRSTP89LPC913MOSIMISOSPICLK002aaa476V DD V SSCLKOUTXTAL2XTAL1PORT 0PORT 3PORT 1PORT 2KBI2KBI4 KBI5 KBI6CIN2ACIN1ACMPREFCMP1TXDRXDT0RSTP89LPC914MOSIMISOSSSPICLK002aaa477V DD V SSPORT 0PORT 1PORT 2Fig 6.P89LPC914 functional diagram7.Pinning information7.1PinningFig 7.P89LPC912 TSSOP14 pin conﬁgurationFig 8.P89LPC913 TSSOP14 pin conﬁgurationFig 9.P89LPC914 TSSOP14 pin conﬁgurationP89LPC912P2.2/MOSI P2.3/MISO P2.5/SPICLKP0.2/CIN2A/KBI2P1.5/RSTP0.4/CIN1A/KBI4V SSP0.5/CMPREF/KBI5P0.6/CMP1/KBI6V DD P1.2/T0P2.4/SSP3.1/XTAL1P3.0/XTAL2/CLKOUT002aaa4781234567810912111413P89LPC913P2.2/MOSI P2.3/MISO P2.5/SPICLKP0.2/CIN2A/KBI2P1.5/RSTP0.4/CIN1A/KBI4V SSP0.5/CMPREF/KBI5P0.6/CMP1/KBI6V DD P1.1/RXD P1.0/TXDP3.1/XTAL1P3.0/XTAL2/CLKOUT002aaa4791234567810912111413P89LPC914P2.2/MOSI P2.3/MISO P2.5/SPICLKP0.2/CIN2A/KBI2P1.5/RSTP0.4/CIN1A/KBI4V SSP0.5/CMPREF/KBI5P0.6/CMP1/KBI6V DD P1.1/RXD P1.0/TXD P1.2/T0P2.4/SS002aaa48012345678109121114137.2Pin description Table 4.P89LPC912 pin descriptionSymbol Pin Type DescriptionP0.2, P0.4 to P0.6I/O Port0:Port0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port0 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port0pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt triggered inputs.Port0 also provides various special functions as described below:P0.2/CIN2A/ KBI213I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input2.P0.4/CIN1A/ KBI412I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input4.P0.5/CMPREF/ KBI511I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input5.P0.6/CMP1/ KBI65I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input6.P1.2, P1.5I/O(P1.2);I(P1.5)Port1:Port1is a2-bit I/O port with P1.2having a user-conﬁgurable output type as noted below.During reset Port1latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the P1.2 input and outputs depends upon the port conﬁguration selected. Refer to Section 8.12.1 “Port conﬁgurations”and T able13“Static characteristics”for details.P1.2is an open drain when used as an output. P1.5 is input only.All pins have Schmitt triggered inputs.Port1 also provides various special functions as described below:P1.2/T06I/O P1.2 —Port1 bit2. (Open drain when used as an output.)I/O T0 —Timer/counter0 external count input or overﬂow output. (Open drain whenused as outputs.).P1.5/RST3I P1.5 —Port1 bit5. (Input only.)I RST —External Reset input during power-on or if selected via UCFG1. Whenfunctioning as a reset input a LOW on this pin resets the microcontroller, causingI/O ports and peripherals to take on their default states, and the processor beginsexecution at address 0. Also used during a power-on sequence to force ISP mode.When using an oscillator frequency above12MHz,the reset input function ofP1.5 must be enabled. An external circuit is required to hold the device inreset at power-up until V DD has reached its speciﬁed level. When systempower is removed V DD will fall below the minimum speciﬁed operatingvoltage. When using an oscillator frequency above 12MHz, in someapplications, an external brownout detect circuit may be required to hold thedevice in reset when V DD falls below the minimum speciﬁed operatingvoltage.P2.2 to P2.5I/O Port 2:Port 2 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled.The operation of Port 2pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 2 also provides various special functions as described below:P2.2/MOSI 1I/OP2.2 —Port 2 bit 2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin is output,when conﬁgured as slave, this pin is input.P2.3/MISO 14I/O P2.3 —Port 2 bit 3.I/O MISO —SPI master in slave out. When conﬁgured as master, this pin is input,when conﬁgured as slave, this pin is output.P2.4/SS 9I/O P2.4 —Port 2 bit 4.I SS —SPI Slave select.P2.5/SPICLK 2I/O P2.5 —Port 2 bit 5.I/O SPICLK —SPI clock. When conﬁgured as master, this pin is output, whenconﬁgured as slave, this pin is input.P3.0 to P3.1I/OPort 3:Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During resetPort 3 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port 3pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 3 also provides various special functions as described below:P3.0/XT AL2/CLKOUT 8I/O P3.0 —Port 3 bit 0.OXTAL2 —Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via the ﬂash conﬁguration).O CLKOUT —CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator orexternal clock input, except when XTAL1/XT AL2 are used to generate clock sourcefor the Real-Time clock/system timer.P3.1/XT AL17I/O P3.1 —Port 3 bit 1.I XTAL1 —Input to the oscillator circuit and internal clock generator circuits (whenselected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator orwatchdog oscillator is used as the CPU clock source,and if XTAL1/XT AL2 are notused to generate the clock for the Real-Time clock/system timer.V SS 4I Ground: 0V reference.V DD 10IPower Supply:This is the power supply voltage for normal operation as well as Idleand Power-down modes.Table 4.P89LPC912 pin description …continued Symbol Pin TypeDescriptionTable 5.P89LPC913 pin descriptionSymbol Pin Type DescriptionP0.2,P0.4to P0.6I/O Port0:Port0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port0 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port0pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt triggered inputs.Port0 also provides various special functions as described below:P0.2/CIN2A/ KBI213I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input 2.P0.4/CIN1A/ KBI412I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input 4.P0.5/CMPREF/ KBI511I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input 5.P0.6/CMP1/ KBI65I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input 6.P1.0, P1.1, P1.5I/O(P1.0,P1.1);I(P1.5)Port1:Port1is a3-bit I/O port with a user-conﬁgurable output type,except for P1.5noted below.During reset Port1latches are conﬁgured in the input only mode withthe internal pull-up disabled.The operation of the conﬁgurable Port1pins as inputsand outputs depends upon the port conﬁguration selected.Each of the conﬁgurableport pins are programmed independently. Refer to Section 8.12.1 “Portconﬁgurations” and Table 13 “Static characteristics” for details. P1.5 is input only.All pins have Schmitt triggered inputs.Port1 also provides various special functions as described below:P1.0/TXD9I/O P1.0 —Port1 bit0.O TXD —T ransmitter output for the serial port.P1.1/RXD6I/O P1.1 —Port1 bit1.I RXD —Receiver input for the serial port.P1.5/RST3I P1.5 —Port1 bit5 (input only).I RST —External Reset input during Power-on or if selected via UCFG1. Whenfunctioning as a reset input, a LOW on this pin resets the microcontroller, causingI/O ports and peripherals to take on their default states, and the processor beginsexecution at address 0. Also used during a power-on sequence to force ISP mode.When using an oscillator frequency above12MHz,the reset input function ofP1.5 must be enabled. An external circuit is required to hold the device inreset at power-up until V DD has reached its speciﬁed level. When systempower is removed V DD will fall below the minimum speciﬁed operatingvoltage. When using an oscillator frequency above 12MHz, in someapplications, an external brownout detect circuit may be required to hold thedevice in reset when V DD falls below the minimum speciﬁed operatingvoltage.P2.2, P2.3,P2.5I/O Port 2: Port 2 is a 3-bit I/O port with a user-conﬁgurable output type. During reset Port 2 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port 2pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 2 also provides various special functions as described below:P2.2/MOSI 1I/OP2.2 —Port 2 bit 2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin is output,when conﬁgured as slave, this pin is input.P2.3/MISO 14I/O P2.3 —Port 2 bit 3.I/O MISO —SPI master in slave out. When conﬁgured as master, this pin is input,when conﬁgured as slave, this pin is output.P2.5/SPICLK 2I/O P2.5 —Port 2 bit 5.I/O SPICLK —SPI clock. When conﬁgured as master, this pin is output, whenconﬁgured as slave, this pin is input.P3.0 to P3.1I/OPort 3:Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During resetPort 3 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port 3pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port 3 also provides various special functions as described below:P3.0/XT AL2/CLKOUT 8I/O P3.0 —Port 3 bit 0.OXTAL2 —Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via the ﬂash conﬁguration).O CLKOUT —CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator orexternal clock input, except when XTAL1/XT AL2 are used to generate clock sourcefor the Real-Time clock/system timer.P3.1/XT AL17I/O P3.1 —Port 3 bit 1.I XTAL1 —Input to the oscillator circuit and internal clock generator circuits (whenselected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator orwatchdog oscillator is used as the CPU clock source,and if XTAL1/XT AL2 are notused to generate the clock for the Real-Time clock/system timer.V SS 4I Ground: 0V reference.V DD 10IPower Supply:This is the power supply voltage for normal operation as well as Idleand Power-down modes.Table 5.P89LPC913 pin description …continued SymbolPin Type DescriptionTable 6.P89LPC914 pin descriptionSymbol Pin Type DescriptionP0.2,P0.4to P0.6I/O Port0:Port0 is a 4-bit I/O port with a user-conﬁgurable output type. During reset Port0 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port0pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.The Keypad Interrupt feature operates with Port0 pins.All pins have Schmitt triggered inputs.Port0 also provides various special functions as described below:P0.2/CIN2A/ KBI213I/O P0.2 —Port0 bit2.I CIN2A —Comparator2 positive input A.I KBI2 —Keyboard input 2.P0.4/CIN1A/ KBI412I/O P0.4 —Port0 bit4.I CIN1A —Comparator1 positive input A.I KBI4 —Keyboard input 4.P0.5/CMPREF / KBI511I/O P0.5 —Port0 bit5.I CMPREF —Comparator reference (negative) input.I KBI5 —Keyboard input 5.P0.6/CMP1/ KBI65I/O P0.6 —Port0 bit6.O CMP1 —Comparator1 output.I KBI6 —Keyboard input 6.P1.0to P1.2, P1.5I/O(P1.0toP1.2);I(P1.5)Port1: Port1 is a 4-bit I/O port with a user-conﬁgurable output type, except forthree pins noted below. During reset Port1 latches are conﬁgured in the input onlymode with the internal pull-up disabled. The operation of the conﬁgurable Port1pins as inputs and outputs depends upon the port conﬁguration selected. Each ofthe conﬁgurable port pins are programmed independently. Refer to Section 8.12.1“Port conﬁgurations” and Table 13 “Static characteristics” for details. P1.2 is anopen drain when used as an output. P1.5 is input only.All pins have Schmitt triggered inputs.Port1 also provides various special functions as described below:P1.0/TXD9I/O P1.0 —Port1 bit0.O TXD —T ransmitter output for the serial port.P1.1/RXD6I/O P1.1 —Port1 bit1.I RXD —Receiver input for the serial port.P1.2/T07I/O P1.2 —Port1 bit2. (Open drain when used as an output.)I/O T0 —Timer/counter0 external count input or overﬂow output. (Open drain whenused as outputs.)P1.5/RST3I P1.5 —Port1 bit5 (input only).I RST —External Reset input during Power-on or if selected via UCFG1. Whenfunctioning as a reset input, a LOW on this pin resets the microcontroller, causingI/O ports and peripherals to take on their default states, and the processor beginsexecution at address 0. Also used during a power-on sequence to force ISP mode.Table 6.P89LPC914 pin description …continuedSymbol Pin Type DescriptionP2.2 to P2.5I/O Port2: Port2 is a 4-bit I/O port with a user-conﬁgurable output type. During resetPort2 latches are conﬁgured in the input only mode with the internal pull-updisabled.The operation of Port2pins as inputs and outputs depends upon the portconﬁguration selected. Each port pin is conﬁgured independently. Refer to Section8.12.1 “Port conﬁgurations” and Table 13 “Static characteristics” for details.All pins have Schmitt triggered inputs.Port2 also provides various special functions as described below:P2.2/MOSI1I/O P2.2 —Port2 bit2.I/O MOSI —SPI master out slave in. When conﬁgured as master, this pin is output,when conﬁgured as slave, this pin is input.P2.3/MISO14I/O P2.3 —Port2 bit3.I/O MISO —SPI master in slave out. When conﬁgured as master, this pin is input,when conﬁgured as slave, this pin is output.P2.4/SS8I/O P2.4 —Port 2 bit 4.I SS —SPI Slave select.P2.5/SPICLK2I/O P2.5 —Port2 bit5.I/O SPICLK —SPI clock. When conﬁgured as master, this pin is output, whenconﬁgured as slave, this pin is input.V SS4I Ground: 0V reference.V DD10I Power Supply: This is the power supply voltage for normal operation as well asIdle and Power-down modes.8.Functional descriptionRemark:Please refer to the P89LPC912/913/914 User manual for a more detailedfunctional description.8.1Special function registersRemark:SFR accesses are restricted in the following ways:•User must not attempt to access any SFR locations not deﬁned.•Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.•SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:–‘-’ Unless otherwise speciﬁed,must be written with ‘0’, but can return any valuewhen read (even if it was written with ‘0’). It is a reserved bit and may be used infuture derivatives.–‘0’must be written with ‘0’, and will return a ‘0’ when read.–‘1’must be written with ‘1’, and will return a ‘1’ when read.P89LPC912_913_914_5© NXP B.V . 2007. All rights reserved.Product data sheet Rev. 05 — 28 September 200717 of 66NXP Semiconductors P89LPC912/913/9148-bit microcontrollers with two-clock 80C51 coreTable 7.P89LPC912 Special function registers* indicates SFRs that are bit Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex BinaryBit address E7E6E5E4E3E2E1E0ACC*Accumulator E0H 000000 0000AUXR1Auxiliary function register A2H CLKLP --ENT0SRST 0-DPS 00[1]0000 00x0Bit address F7F6F5F4F3F2F1F0B* B register F0H 000000 0000CMP1Comparator 1 control register ACH --CE1-CN1OE1CO1CMF100[1]xx00 0000CMP2Comparator 2 control register ADH --CE2-CN2-CO2CMF200[1]xx00 0000DIVM CPU clock divide-by-M control95H 000000 0000DPTR Data pointer (2 bytes)DPH Data pointer high 83H 000000 0000DPL Data pointer low 82H 000000 0000FMADRH Program ﬂash address high E7H ------000000 0000FMADRL Program ﬂash address low E6H 000000 0000FMCON Program ﬂash control (Read)E4H BUSY ---HVA HVE SV OI 700111 0000Program ﬂash control (Write)FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.FMDA T A Program ﬂash data E5H 000000 0000Bit address AF AE AD AC AB AA A9A8IEN0*Interrupt enable 0A8H EA EWDRT EBO -ET1-ET0-000000 0000Bit address EF EE ED EC EB EA E9E8IEN1*Interrupt enable 1E8H ----ESPI EC EKBI -00[1]00x0 0000Bit address BF BE BD BC BB BA B9B8IP0*Interrupt priority 0B8H -PWDRT PBO -PT1-PT0-00[1]x000 0000IP0H Interrupt priority 0 high B7H -PWDRT HPBOH -PT1H -PT0H -00[1]x000 0000Bit address FF FE FD FC FB FA F9F8IP1*Interrupt priority 1F8H ----PSPI PC PKBI -00[1]00x0 0000IP1H Interrupt priority 1 high F7H ----PSPIH PCH PKBIH -00[1]00x0 0000芯天下--/P89LPC912_913_914_5© NXP B.V . 2007. All rights reserved.Product data sheet Rev. 05 — 28 September 200718 of 66NXP Semiconductors P89LPC912/913/9148-bit microcontrollers with two-clock 80C51 core KBCON Keypad control register 94H ------P ATN _SELKBIF 00[1]xxxx xx00KBMASK Keypad interrupt mask register86H 000000 0000KBP ATN Keypad pattern register 93H FF 1111 1111Bit address 8786858483828180P0*Port 080H CMP1/KB6CMPREF / KB5CIN1A/KB4CIN2A/KB2[1]Bit address 9796959493929190P1*Port 190H RST T0[1]Bit address A7A6A5A4A3A2A1A0P2*Port 2A0H SPICLK SS MISO MOSI [1]Bit address B7B6B5B4B3B2B1B0P3*Port 3B0H XTAL1XT AL2[1]P0M1Port 0 output mode 184H (P0M1.6)(P0M1.5)(P0M1.4)(P0M1.2)FF 1111 1111P0M2Port 0 output mode 285H (P0M2.6)(P0M2.5)(P0M2.4)(P0M2.2)000000 0000P1M1Port 1 output mode 191H (P1M1.2)D3[1]11x1 xx11P1M2Port 1 output mode 292H (P1M2.2)-00[1]00x0 xx00P2M1Port 2 output mode 1A4H (P2M1.5)(P2M1.4)(P2M1.3)(P2M1.2)FF 1111 1111P2M2Port 2 output mode 2A5H (P2M2.5)(P2M2.4)(P2M2.3)(P2M2.2)000000 0000P3M1Port 3 output mode 1B1H (P3M1.1)(P3M1.0)03[1]xxxx xx11P3M2Port 3 output mode 2B2H (P3M2.1)(P3M2.0)00[1]xxxx xx00PCON Power control register 87H --BOPD BOI GF1GF0PMOD1PMOD0000000 0000PCONA Power control register A B5H RTCPD -VCPD --SPPD --00[1]0000 0000Bit address D7D6D5D4D3D2D1D0PSW*Program status word D0H CY AC F0RS1RS0OV F1P 000000 0000PT0AD Port 0 digital input disable F6H --PT0AD.5PT0AD.4-PT0AD.2--00xx00 000x RSTSRC Reset source register DFH --BOF POF -R_WD R_SF R_EX [2]RTCCON Real-time clock control D1H RTCF RTCS1RTCS0---ERTC RTCEN 60[1][5]011x xx00RTCH Real-time clock register high D2H 00[5]0000 0000Table 7.P89LPC912 Special function registers …continued* indicates SFRs that are bit addressable.Name Description SFR addr.Bit functions and addresses Reset valueMSB LSB Hex Binary芯天下--/。

基于P89LPC915微处理器控制的数字化高压电源模块

控制方式。例如，了能够补偿由于温度变化为引起的光电倍增管参数变化而引起的仪器误差，器需要根据温度的变化调整提供给光电仪倍增管的高压＿，高仪器的温度稳定性。－提１］随着使用方式的改变和对电源性能要求的提高，高压电源的设计也提出了新的要求。对
收稿日期：０９Ｏ－３２０７Ｏ－
作者简介：米昶（９２，，１５一）男山东青岛，副教授，教师，硕士学位，主要研究方向：入式系统，能仪嵌智
器。
１６４６
关。在传统的电路设计中，该部分电路的实现
方式一般有两种：分立元件构成的振荡电路，例
由于在传统的高压电源模块设计中电源参数的控制一般都是通过人工调节模拟电路用电位器，若要实现智能化的自动控制须通过附加电
路的形式实现。例如使用ＤＡ控制芯片将电源电压的控制由模拟控制方式转变为数字控制方式。如果在高压电源模块中能自动实现上述功能，该类仪器的设计必将带来非常有意义的对１２系统模块功能的常规实现技术．
电路特性的限制，这类电路的频率稳定性受到定的局限而且实现ＰＷＭ控制较为困难。
另外，为一个完整的电源系统的控制部作
分，了高频信号发生电路外，除还需稳定电压输
出的电路。在由分立元件构成的电路中，由于
电路实现方法的限制，般采用高压稳压管的一方式。这种方式不但体积较大，而且电源的效率也较低。因此，现代电源的电路结构普遍在信号发生电路的基础上附加输出电压的取样电路，通过控制频率发生电路输出的方法实现稳定的直流高压输出。为了满足电源的性能和简化设计，许多在高压电源模块的设计中采用了开关集成控制器，例如Ｓ５４Ｔ４４等［。这类控制器属Ｇ３２、Ｌ９１］

P89LPC9401 中文手册

I/O P2.1
I/O P2.2
I/O MOSI SPI 主机输出/从机输入。当配置为主机时，该管脚为输出；当配置
20 63 64 BP0~BP3 S0~S31 Vss VDD VLCD 27-30 31-62 12 25 26
SPICLK SPI 时钟。当配置为主机时，该管脚为输出；当配置为从机时，
I/O SDALCD I/O SCLLCD O O I I I
BP0-3：LCD 背电极输出。 S0-S31: LCD 段输出。地: 0V 参考点。
电源: 正常操作模式、空闲模式和掉电模式时的电源。 LCD 电源：LCD 电源电压。
[1] P1.0～P1.4、P1.6、P1.7 为输入/输出口，P1.5 仅为输入口。
6. 逻辑符号
图 3 P89LPC9401 逻辑符号
5
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7. 功能描述
备注：更详细的功能描述请参考 P89LPC9401 使用指南。 7.1 特殊功能寄存器备注：对特殊功能寄存器（SFR）的访问必须遵循以下方式：用户不要试图访问任何未经定义的 SFR 地址。对任何已定义的 SFR 的访问必须符合 SFR 的功能。标注为‘-’,‘0’或‘1’的 SFR 位只能以如下方式读或写：－除非特别说明， ‘-’必须写入 0，但当读出时不返回任何确定的值（即使向其写入 0）。这是一个保留位，作为将来功能扩展之用。－‘0’必须写入 0，并且当读出时返回 0。－‘1’必须写入 1，并且当读出时返回 1。表 4 特殊功能寄存器带*的 SFR 表明可位寻址
名称定义地址位地址 ACC* AUXR1 累加器辅助功能寄存器 E0H A2H 位地址 B* BRGR0 BRGR1

基于LPC系列单片机的串口扩展器设计

基于LPC系列单片机的串口扩展器设计唐洪富【摘要】介绍了一种基于单片机 P89LPC931的 SPI 总线扩展异步串行接口UART 的装置，讲述了P89LPC931单片机的开发使用，重点详细阐明了扩展芯片GM8142的开发使用。

用户可以根据不同的应用环境灵活配置参数。

本装置成本低，可靠性高，稳定性强。

%An UART extended by SPI bus based on single chip microcomputer P89LPC931 was introduced. The development ofP89LPC931 was described, and the development of the chip GM8142 was emphatically elaborated. The configuration parameters are flexible depended on the application environment. The extender has the characters of low cost , reliability and stability.【期刊名称】《微型机与应用》【年(卷),期】2015(000)013【总页数】3页(P97-99)【关键词】LPC 单片机;GM8142;SPI 总线【作者】唐洪富【作者单位】中国电子信息产业集团有限公司第六研究所，北京 100083【正文语种】中文【中图分类】TP23随着单片机技术的不断发展，特别是网络技术在测控领域的广泛应用，由单片机构成的多机网络测控系统已成为单片机技术发展的一个方向。

单片机的应用已不仅仅局限于传统意义上的自动监测或控制，而是形成了向以网络为核心的分布式多点系统发展的趋势。

但是，大多数单片机都只有一个串行接口，在多数情况下限制了这些单片机的进一步应用。

要实现单片机在应用系统中的有效通信，就必须对单片机进行串口扩展。

TKS-932、935、936仿真器快速入门

TKS-932/935/936仿真器快速入门（2005/03/16 V2.2）注：本用户使用手册适用于TKS-932、TKS-935和TKS-936，以下统称为TKS-900。

目录一、 TKS-900技术特点和背景资料二、 TKS-900型号的分类三、 TKS-900仿真器使用前应该了解的知识四、 TKS-900在Keil中的快速操作五、使用TKS-900进行仿真六、 TKS-900的物理结构七、 TKS-900仿真头组件的使用八、 TKS-900仿真器的限制九、 TKS-900使用中的常见问题十、 TKS-900的升级十一、结束语警告：该文档的内容可能会在以后发生改变，用户需要以随机提供的电子文档为标准。

一、TKS-900技术特点和背景资料TKS-900仿真器是广州致远电子有限公司推出的系列实时在线仿真器，TKS-900完全支持PHILIPS公司P89LPC900系列芯片的仿真（TKS-932、TKS-935分别支持P89LPC932、P89LPC935以下芯片的仿真，均可有偿升级到TKS-936，支持P89LPC938以下芯片的仿真）。

在仿真性能上进行了全面的优化设计，能保证用户更加方便的操作和真实的仿真效果。

兼容Keil公司的硬件仿真环境，使用户能够在先进的编译环境下编译，同时也能在先进的仿真环境下进行硬件仿真；使用PHILIPS公司授权的专用BondOut芯片，仿真更加真实；采用更加合理的BondOut通讯方式，BondOut工作更加稳定；真实仿真LPC900的掉电模式和空闲模式；真实仿真LPC900的各种方式的复位（软件复位、看门狗复位、外部复位）；支持用户程序嵌入配置字节，使用户仿真/烧写更加方便可靠，同时在仿真中可随意观察和修改用户配置字节（等待标准制定）；内部更加可靠的保护，避免使用中误操作引起仿真器的损坏；连续单步运行速度更快；支持使用外部用户电源电压，用户提供的电源电压最低可达3.3伏；支持使用外部复位信号；仿真时多而详细的状态信息提示，帮助用户迅速查找目标系统的故障；系统内部多种检查，当系统配置错误时避免进入错误的运行状态。

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特殊功能寄存器
注 1. 2. 3. 对特殊功能寄存器的访问必须遵循以下方式用户不要试图访问任何未经定义的 SFR 地址对任何已定义的 SFR 的访问必须符合 SFR 的功能标注为 , 0 或 1 的 SFR 位只能以如下方式读或写这是一个保留位作为将来功能 - 必须写入 0 但当读出时不返回任何确定的值即使向其写入 0 扩展之用 0 1
4
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38730977
Fax: 38730925

仅为输入
RST 上电时作为外部复位输入(通过 UCFG1 选择) 作为复位管脚时输入
1,2,8,14
的低电平会使芯片复位,I/O 口和外围功能进入默认状态处理器从地址 0 开始执行另外该管脚还可用于在上电时强制进入在系统编程模式 PORT2 P2 是一个可由用户定义输出类型的 4 位 I/O 口在上电复位时 P2 锁存器配置为内部上拉禁止的仅为输入模式 P2 口由口配置寄存器设定为输出或输入模式每一位均可单独设定详细请参考 I/O 口配置和 DC 特 I/O 性部分所有管脚都具有施密特触发输入 P2 口还可提供如下特殊功能 I/O P2.2 I/O MOSI I/O P2.3 I/O MISO I/O P2.4 I SS P2 口位 2. SPI 主机输出/从机输入当配置为主机时为从机时该管脚为输入 P2 口位 3 SPI 主机输入/从机输出当配置为主机时为从机时该管脚为输出 P2 口位 4 . 该管脚为输出当配置
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38730977
Fax: 38730925

P89LPC914 单片机数据手册
概述
P89LPC914 是一款单片封装的微控制器适合于许多要求高集成度低成本的场合可以满足多方面的性能要求的成本 P89LPC914 采用了高性能的处理器结构指令执行时间只需 2 到 4 个时钟周期 6 倍于标准 80C51 器件 P89LPC914 集成了许多系统级的功能这样可大大减少元件的数目和电路板面积并降低系统
A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN_SEL
A8 E8 B8 F8 KBIF
00H 00H
1 1
00H 00H1
00H 1 00H 00H 00H FFH
1
1
键盘中断 KBCON# KBMASK# 键盘中断屏蔽 KBPATN# 键盘模式
87 P0* P1* P2* P0M1# P0M2# P1M1# P1M2# P2M1# P2M2# PCON# PCONA# PSW* PT0AD# RSTSRC# RTCCON# RTCH# RTCL# SADDR# SADEN# SBUF SCON* SSTAT# SP SPCTL# SPSTAT# SPDAT# TAMOD# TCON* TH0 TH1 TL0 TL1 TMOD TRIM# WDCON# WDL# WFEED1# WFEED2# P0 口 P1 口 P2 口 0 口输出模式选择 1 0 口输出模式选择 2 1 口输出模式选择 1 1 口输出模式选择 2 2 口输出模式选择 1 2 口输出模式选择 2 电源控制寄存器电源控制寄存器 A 程序状态字 0 口数字输入禁能复位源寄存器实时时钟控制实时时钟高字节实时时钟低字节串口地址寄存器串口地址使能串口数据缓冲区串行口控制串行口扩展状态堆栈指针 SPI 控制寄存器 SPI 状态寄存器 SPI 数据寄存器定时器 0/1 附加模式定时器 0/1 控制定时器 0 高字节定时器 1 高字节定时器 0 低字节定时器 1 低字节定时器 0/1 模式内部振荡调整寄存器看门狗控制寄存器看门狗装载看门狗清零 1 看门狗清零 2 80H 97 90H A7 A0H 84H 85H 91H 92H A4H A5H 87H B5H D0H F6H DFH D1H D2H D3H A9H B9H 99H 98H BAH 81H E2H E1H E3H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H 9F SM0/FE DBMOD SMOD1 RTCPD D7 CY RTCF
ACH ADH 95H
-
-
CE1 CE2
-
CN1 CN2
OE1 -
CO1 CO2
CMF1 CMF2
00H 00H1 00H
1
83H 82H E7H E6H
00H 00H 00H 00H
FMADRH# 编程 Flash 地址高字节 FMADRL# 编程 Flash 地址低字节
5
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1 P2.2~P2.5 14
该管脚为输入
当配置
8 2 VSS VDD 4 10
SPI 从机选择. P2.5 P2 口位 5 I/O SPICLK SPI 时钟当配置为主机时该管脚为输出 I/O 该管脚为输入 I 地: 0V 参考点 I 电源: 正常操作模式空闲模式和掉电模式时的电源
当配置为从机时
管脚描述
符号管脚号 (TSSOP14 类型 /DIP14) 名称及功能描述 PORT0 P0 是一个可由用户定义输出类型的 4 位 I/O 口在上电复位时 P0 锁存器配置为内部上拉禁止的仅为输入模式 P0 口由口配置寄存器设定为输出或输入模式每一个管脚均可单独设定详细请参考 I/O 口配置和 DC 电气特性部分 P0 口具有键盘输入中断功能所有管脚都具有施密特触发输入 P0 口还可提供如下特殊功能 P0.2 P0 口位 2 CIN2A 比较器 2 正向输入 A KBI2 键盘输入 2 P0.4 P0 口位 4 CIN1A 比较器 1 正向输入 A KBI5 键盘输入 5 P0.5 P0 口位 5 CMPREF 比较器参考输入负 KBI2 键盘输入 2 P0.6 P0 口位 6 CMP1 比较器 1 输出 KBI6 键盘输入 6 PORT1 除了下面说明的三个管脚外 P1 是一个可由用户定义输出类型的 4 位 I/O 口在上电复位时 P1 锁存器配置为内部上拉禁止的仅为输入模式 P1 口由口配置寄存器设定为输出或输入模式每一位均可单独设定详细请参考 I/O 口配置和 DC 电气特性部分 P1.2 作为输出时为开漏 P1.5 为仅为输入模式所有管脚都具有施密特触发输入 P1 口还可提供如下特殊功能 P1.0 P1 口位 0 TXD 串行口输出 P1 口位 1 串行口输入作为输出时为开漏 P1 口位 2 定时/计数器 0 外部计数输入或溢出输出作为输出时为开漏
掉电电流为 1µA 比较器关闭时的完全掉电状态
订购信息
货品号 P89LPC914BN P89LPC914BDH 封装 DIP14 TSSOP14 温度范围 0 0 +70 +70 0 0 频率 12MHz 12MHz 制定编号
逻辑符号
图1
逻辑符号
2
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名称 ACC* AUXR1# B* 累加器辅助功能寄存器 B 寄存器
必须写入 0 必须写入 1
定义
并且当读出时返回 0 并且当读出时返回 1
地址 E7 E0H A2H F0H BEH BFH BDH F7 EBRR F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 E6 E5 位功能和位地址 E4 E3 复位值 E2 E1 E0 00H 00H
1
特殊功能寄存器
00H
BRGR0#§ 波特率发生器低字节 BRGR1#§ 波特率发生器高字节 BRGCON# 波特率发生器控制
-
-
-
-
-
-
SBRGS
BRGEN
00H
%
CMP1# CMP2# DIVM# DPTR DPH DPL
比较器 1 控制比较器 2 控制 CPU 时钟分频控制数据指针 2 字节指针高字节指针低字节
编程 Flash 控制读编程 Flash 控制写编程 Flash 数据 E4H E5H AF EA EF BF FF AE EWDRT EE EST BE PWDRT PWDRTH FE PST PSTH -
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z 振荡器失效检测看门狗定时器具有独立的片内振荡器节 z 可编程 I/O 口输出模式准双向口开漏输出 z 端口输入模式匹配一个中断 z 双数据指针 DPTR z 施密特触发端口输入 z 所有口线均有 LED 驱动能力 z 最少 9 个 I/O 口 20mA 检测
z 选择内部 RC 振荡器时不需要外接振荡器件可选择 RC 振荡器选项并且其频率可进行很好的调推挽和仅为输入功能可产生
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z 串行 Flash 编程可实现简单的在电路编程 Flash 保密位可防止程序被读出 z Flash 程序存储器可实现在应用中编程 z 空闲和两种不同的掉电节电模式 z 14 脚 TSSOP 和 DIP 封装 z 仿真支持这允许在程序运行时改变代码低电平中断输入唤醒典型的提供从掉电模式中唤醒功能
当 P0 口管脚的值与一个可编程的模式匹配或者不匹配时
但整个芯片有一个最大值的限制
z 可控制口线输出斜率以降低 EMI
输出最小跳变时间约为 10ns
选择片内振荡和片内复位时可多达 12 个 I/O 口
z 当选择片内复位时 P89LPC914 只需连接电源和地
1
广州周立功单片机发展有限公司 Tel: (020)38730976