OX8541中文资料

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MAX7491中文资料

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect devic Rev 0; 7/00
Dual Universal Switched-Capacitor Filters
General Description
The MAX7490/MAX7491 consist of two identical lowpower, low-voltage, wide dynamic range, Rail-to-Rail®, 2nd-order switched-capacitor building blocks. Each of the two filter sections, together with two to four external resistors, can generate all standard 2nd-order functions: bandpass, lowpass, highpass, and notch (band reject). Three of these functions are simultaneously available. Fourth-order filters can be obtained by cascading the two 2nd-order filter sections. Similarly, higher order filters can easily be created by cascading multiple MAX7490/MAX7491s. Two clocking options are available: self-clocking (through the use of an external capacitor) or external clocking for tighter cutoff frequency control. The clockto-center frequency ratio is 100:1. Sampling is done at twice the clock frequency, further separating the cutoff frequency and Nyquist frequency. The MAX7490/MAX7491 have an internal rail splitter that establishes a precise common voltage needed for single-supply operation. The MAX7490 operates from a single +5V supply and the MAX7491 operates from a single +3V supply. Both devices feature a low-power shutdown mode and come in a 16-pin QSOP package.

智能电表的设计

四川理工学院课程设计书学院计算机学院专业物联网工程20121班课程无线传感器网络题目现代小区智能电表课程设计教师符长友学生胥玉环刘依粒胡伟杰宋治桦设计时间：2014年7月5日至2017年7月11日前言近年来，在低碳经济、绿色节能及可持续发展思想的推动下，如何进一步提高电网效率，积极应对环境挑战，提高供电可靠性和电能质量，完善电力用户服务，适应更加开放的能源及电力市场化环境需要，对未来电网的发展提出了更高的要求。

智能电网的概念应运而生并成为全球电力行业共同研究和探讨的热点，支撑中国乃至全球智能电网的将是通信技术、信息处理技术和控制技术。

智能电表作为智能电网建设的重要基础装备，加快智能电表产业链整合，促进其产业化，对于电网实现信息化、自动化和互动化具有支撑作用。

基于以上分析，本文研究旨在基于AT89C51单片机的智能电表的设计。

本次设计基于单片机AT89C51是以微处理器或微控制器芯片为核心的可以存储大量的测量信息并具有对测量结果进行实时分析、综合和做出各种判断能力的仪器。

一般具有自动测量功能，强大的数据处理能力，进行自动调零和单位换算功能，能进行简单的故障提示，具有操作面板和显示器，有简单的报警功能。

本文主要包括以下三个方面的工作：(1)智能电表的设计背景、优点及发展现状本文首先分析智能电表的设计背景，其次讨论智能电表的优点及相关的应用。

(2)智能电表的硬件和软件实现分析智能电表应该具备的功能，给出该仪表的总体设计框图；详细讨论了该电路的核心芯片选取、数据采集电路的设计、通信电路及输入输出系统的实现并给出了核心芯片．AT89C51的详细参数；使用结构化程序设计手段，利用单片机C语言程序实现按键的扫描并处理程序、数据的采集及后续的算法程序、红外或RS485通信方式的自动抄表程序、CPU卡的读写操作程序以及段式LCD的显示驱动程序。

(3)设计的结论分析、不足及未来的展望阐述了设计的测试结果并对结论进行了分析，给出了设计中的不足之处，并提出了将来的修改意见及改进之处，对智能电表的未来进行展望。

OXuPCI954_DS

External—Free ReleaseOxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210 © Oxford Semiconductor, Inc. 2007F EATURES• Four 16C950 High performance UART channels • 8-bit Pass-through Local Bus (PCI Bridge )• IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver)• Efficient 32-bit, 33 MHz, multi-function target-only PCIcontroller, fully compliant to PCI Local Bus Specification 3.0 and PCI Power Management Specification 1.1 • Software compatible with OXmPCI954• UARTs fully software compatible with 16C550-type devices • UART operation up to 60 MHz via external clock source. Up to 20 MHz with the crystal oscillator• Baud rates up to 60 Mbps in external 1x clock mode and 15 Mbps in asynchronous mode• 128-byte deep FIFO per transmitter and receiver • Flexible clock prescaler, from 1 to 31.875• Automated in-band flow control using programmable Xon/Xoff in both directions•Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#• Programmable RS485 turnaround delay• Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control• Infra-red (IrDA) receiver and transmitter operation • 9-bit data framing, as well as 5, 6, 7, and 8 bits • Detection of bad data in the receiver FIFO• Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers.• Local registers to provide status/control of device functions • 11 multi-purpose I/O pins, which can be configured as input interrupt pins or ‘wake-up’• Auto-detection of a wide range of optional MICROWIRE TM compatible EEPROMs, to re-configure device parameters • Function access , to pre-configure each function prior to handover to generic device drivers • Operation via I/O or memory mapping• 3.3 V or 5 V operation (PCI Universal Voltage)• Extended operating temperature range: -40° C to 85° C •176-pin LQFP packageD ESCRIPTIONThe OXuPCI954 is a single chip solution for PCI-based serial and parallel expansion add-in cards. It is a dual function PCI device, where function 0 offers four ultra-high performance OX16C950 UARTs, and function 1 is configurable either as an 8-bit local bus or a bi-directional parallel port.Each UART channel in the OXuPCI954 is the fastest available PC-compatible UART, offering data rates up to 15 Mbps and 128-byte deep transmitter and receiver FIFOs. The deep FIFOs reduce CPU overhead and allow utilization of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices (and compatibles), as well as the OX16C95x family of high performance UARTs. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features including automated in-band flow control, readable FIFO levels, etc.To enhance device driver efficiency and reduce interrupt latency, internal UARTs have multi-port features such as shadowed FIFO fill levels, a global interrupt source register and Good-Data Status, readable in four adjacent DWORD registers visible to logical functions in I/O space and memory space.Expansion of serial ports beyond four channels is possible using the 8-bit pass-through Local Bus function. This provides a general address/data bus and interrupt capability to a discrete UART part, such as the Oxford SemiconductorOX16C954. Other controllers could be used to provide capabilities beyond additional UART ports. The addressable space provided by the Local Bus can be increased up to 256 bytes, and divided into four chip-select regions. This flexible expansion scheme caters for cards with up to 20 serial ports using external 16C950, 16C954 or compatible devices, or composite applications such as combined serial and parallel port expansion cards. Serial port cards with up to 20 ports (or with 4 serial ports and a parallel port) can be designed without redefining any device or timing parameters.The parallel port is an IEEE 1284 compliant SPP/EPP/ECP parallel port that fully supports the existing Centronics interface. The parallel port can be enabled in place of the local bus. A n external bus transceiver is required for 5V parallel port operation if device is 3.3V sourced.For full flexibility, all the default configuration register values can be overwritten using an optional M ICROWIRE compatibleserial EEPROM. This EEPROM can also be used to provide function access to pre-configure devices on the local bus/parallel port, prior to any PCI configuration accesses and before control is handed to (generic) device drivers.The OXuPCI954 can be used to replace the OXmPCI954 in a PCI application where quad UARTs and a local bus/parallel port functionality are required.OXuPCI954 DATA SHEETIntegrated High Performance Quad UARTs,8-bit Local Bus/Parallel Port,3.3 V and 5 V (Universal Voltage) PCI Interface .Improvements of the OXuPCI954 over Discrete SolutionsHigher degree of integrationThe OXuPCI954 device offers four internal 16C950 high-performance UARTs and an 8-bit local bus or abi-directional parallel port.Multi-function deviceThe OXuPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the local bus or drivers for the internal parallel port.Quad Internal OX16C950 UARTsThe OXuPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter and receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60 Mbps.Improved access timingAccess to the internal UARTs require zero or one PCI wait state. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latencyThe OXuPCI954 device offers shadowed FIFO levels and Interrupt status registers on the internal UARTs and the MIO pins. This reduces the device driver interrupt latency. Power managementThe OXuPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input.Optional EEPROMThe OXuPCI954 device can be reconfigured from an external EEPROM to the end-user’s requirements. However, this is not required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the EEPROM controller prevents the PCI system from ‘hanging’ due to an incorrectly programmed EEPROM.R EVISION H ISTORYRevision Modification May 2007 First publication.Sep 2007 Feature revision, including removal of D3coldT ABLE OF C ONTENTS1OXuPCI954 Device Modes (6)2Block Diagram (7)3Pin Information—176-Pin LQFP (8)3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus (8)3.1.1Mode ‘1’ : Quad UARTs + Parallel Port (9)3.2Pin Descriptions (10)4Configuration and Operation (16)5PCI Target Controller (17)5.1Operation (17)5.2Configuration Space (17)5.2.1PCI Configuration Space Register Map (18)5.3Accessing Logical Functions (20)5.3.1PCI Access to Internal UARTs (21)5.3.2PCI Access to 8-bit Local Bus (22)5.3.3PCI Access to Parallel Port (22)5.4Accessing Local Configuration Registers (23)5.4.1Local Configuration and Control Register ‘LCC’ (Offset 0x00) (23)5.4.2Multi-purpose I/O Configuration Register ‘MIC’ (Offset 0x04) (24)5.4.3Local Bus Timing Parameter Register 1 ‘LT1’ (Offset 0x08) (26)5.4.4Local Bus Timing Parameter Register 2 ‘LT2’ (Offset 0x0C) (27)5.4.5UART Receiver FIFO Levels ‘URL’ (Offset 0x10) (28)5.4.6UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14) (29)5.4.7UART Interrupt Source Register ‘UIS’ (Offset 0x18) (29)5.4.8Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C) (30)5.5PCI Interrupts (31)5.6Power Management (32)5.6.1Power Management of Function 0 (32)5.6.2Power Management of Function 1 (33)5.6.3Universal Voltage (34)5.7Unique Bar Option – for Function 0 (35)6Internal OX16C950 UARTs (36)6.1Operation – Mode Selection (36)6.1.1450 Mode (36)6.1.2550 Mode (36)6.1.3Extended 550 Mode (36)6.1.4750 Mode (36)6.1.5650 Mode (36)6.1.6950 Mode (37)6.2Register Description Tables (38)6.3UART Reset Configuration (41)6.3.1Hardware Reset (41)6.3.2Software Reset (41)6.4Transmitter and Receiver FIFOs (42)6.4.1FIFO Control Register ‘FCR’ (42)6.5Line Control and Status (43)6.5.1False Start Bit Detection (43)6.5.2Line Control Register ‘LCR’ (43)6.5.3Line Status Register ‘LSR’ (44)6.6Interrupts and Sleep Mode (45)6.6.1Interrupt Enable Register ‘IER’ (45)6.6.2Interrupt Status Register ‘ISR’ (46)6.6.3Interrupt Description (46)6.6.4Sleep Mode (47)6.7Modem Interface (47)6.7.1Modem Control Register ‘MCR’ (47)6.7.2Modem Status Register ‘MSR’ (48)6.8Other Standard Registers (48)6.8.1Divisor Latch Registers ‘DLL and DLM’ (48)6.8.2Scratch Pad Register ‘SPR’ (48)6.9Automatic Flow Control (49)6.9.1Enhanced Features Register ‘EFR’ (49)6.9.2Special Character Detection (50)6.9.3Automatic In-band Flow Control (50)6.9.4Automatic Out-of-band Flow Control (50)6.10Baud Rate Generation (51)6.10.1General Operation (51)6.10.2Clock Prescaler Register ‘CPR’ (51)6.10.3Times Clock Register ‘TCR’ (51)6.10.4External 1x Clock Mode (53)6.10.5Crystal Oscillator Circuit (53)6.11Additional Features (54)6.11.1Additional Status Register ‘ASR’ (54)6.11.2FIFO Fill Levels ‘TFL and RFL’ (54)6.11.3Additional Control Register ‘ACR’ (54)6.11.4Transmitter Trigger Level ‘TTL’ (55)6.11.5Receiver Interrupt. Trigger Level ‘RTL’ (55)6.11.6Flow Control Levels ‘FCL’ and ‘FCH’ (56)6.11.7Device Identification Registers (56)6.11.8Clock Select Register ‘CKS’ (56)6.11.9Nine-bit Mode Register ‘NMR’ (57)6.11.10Modem Disable Mask ‘MDM’ (57)6.11.11Readable FCR ‘RFC’ (58)6.11.12Good-data Status Register ‘GDS’ (58)6.11.13Port Index Register ‘PIX’ (58)6.11.14Clock Alteration Register ‘CKA’ (58)6.11.15RS485 Delay Enable ‘RS485_DLYEN’ (58)6.11.16RS485 Delay Count ‘RS485_DLYCNT’ (59)7Local bus (60)7.1Overview (60)7.2Operation (60)7.3Configuration and Programming (61)8Bidirectional Parallel Port (62)8.1Operation and Mode Selection (62)8.1.1SPP Mode (62)8.1.2PS2 Mode (62)8.1.3EPP Mode (62)8.1.4ECP Mode (62)8.2Parallel Port Interrupt (63)8.3Register Description (63)8.3.1Parallel Port Data Register ‘PDR’ (64)8.3.2ECP FIFO Address / RLE (64)8.3.3Device Status Register ‘DSR’ (64)8.3.4Device Control Register ‘DCR’ (64)8.3.5EPP Address register ‘EPPA’ (65)8.3.6EPP Data Registers ‘EPPD1-4’ (65)8.3.7ECP Data FIFO (65)8.3.8Test FIFO (65)8.3.9Configuration A Register (65)8.3.10Configuration B Register (65)8.3.11Extended Control Register ‘ECR’ (65)9Serial EEPROM (66)9.1Specification (66)9.1.1Zone 0: Header (67)9.1.2Zone 1: Local Configuration Registers (68)9.1.3Zone 2: Identification Registers (69)9.1.4Zone 3: PCI Configuration Registers (69)9.1.5Zone 4: Power Management DATA (and DATA_SCALE Zone) (70)9.1.6Zone 5: Function Access (70)10Operating Conditions (72)10.1DC Electrical Characteristics (72)11AC Electrical Characteristics (76)11.1PCI Bus Timings (76)11.2Local Bus (77)11.3Serial Ports (79)12Timing Waveforms (80)13Package Information (95)13.1176-Pin LQFP (95)14Ordering Information (96)1OX U PCI954D EVICE M ODESThe OXuPCI954 supports two modes of operation. These modes are summarized in the following table.Device Mode Mode Pin Selection Functionality0 MODE = 0 Function 0 : Quad UARTs Function 1 : 8-bit local bus1 MODE = 1 Function 0 : Quad UARTs Function 1 : Parallel Port* The OXuPCI954 is not pin-compatible with the OX16PCI954 or the OXmPCI954, but is the same in all other aspects.2B LOCK D IAGRAMFIFOSELMODEAD[31:0]C/BE[3:0]#PCI_CLKFRAME#DEVSEL#IRDY#TRDY#STOP#PARPERR#IDSELRST#INTA#PME#XTLIXTLOUART_Clk_Out Local_Bus ClkEE_DIEE_CSEE_CKEE_DOSOUT[3:0]SIN[3:0]RTS[3:0]DTR[3:0]CTS[3:0]DSR[3:0]DCD[3:0]RI[3:0]MIO[10:0]PD[7:0]ACK#PEBUSYSLCTERR#SLIN#INIT#AFD#STB#LBA[7:0]LBD[7:0]LBCS[3:0]LBWR#LBRD#LBRSTDATA_DIR OXuPCI954 Block DiagramOSCDIS XTLSEL3P IN I NFORMATION—176-P IN LQFP 3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus7 NC. Do not connect these pins:23, 40, 41, 136, 137, 138, 1393.1.1Mode ‘1’ : Quad UARTs + Parallel Port15 NC. Do not connect these pins:23, 40, 41, 74, 112, 113, 114, 115, 116, 117, 124, 136, 137, 138, 1393.2Pin DescriptionsFor the actual pinouts of the OXuPCI954 device (for the various modes), refer to the Section 3, Pin Information. The I/O direction key table is on page 15.PCI Interface – All ModesPin Dir1Name Description149, 150, 151, 154, 155,157, 158, 160, 164, 165,167, 168, 169, 170, 171,174, 13, 14, 15, 17, 18, 20,24, 25, 27, 28, 31, 32, 33,34, 35, 39P_I/O AD[31:0] Multiplexed PCI Address/Data bus161, 175, 12, 26 P_I C/BE[3:0]# PCI Command/Byte enable146 P_I CLK PCI system clock (33MHz)176 P_IFRAME#CycleFrame5 P_ODEVSEL#DeviceSelect1 P_IIRDY#Initiatorready2 P_OTRDY#Targetready6 P_O STOP# Target Stop request10 P_I/OPAR Parity8 P_OSERR#Systemerror7 P_I/OPERR#Parityerror163 P_I IDSEL Initialization device select144 P_I RST# PCI system reset142 P_ODINTA# PCIinterrupt147 P_OD PME# Power management eventSerial Port Pins – All ModesPin Dir1Name Description50 I FIFOSEL FIFO select. For backward compatibility with 16C550,16C650 and 16C750 devices the UARTs’ FIFO depth is 16when FIFOSEL is low. The FIFO size is increased to 128when FIFOSEL is high. The unlatched state of this pin isreadable by software. The FIFO size may also be set to 128by setting FCR[5] when LCR[7] is set, or by putting thedevice into Enhanced mode.82, 81, 63, 62 O(h)SOUT[3:0]IrDA_Out[3:0] These four pins are present in all modes but they can serve one of two functions, as follows:UART serial data outputs.UART IrDA data output when MCR[6] of the corresponding channel is set in Enhanced mode.91, 73, 72, 55I(h) I(h) SIN[3:0]IrDA_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:UART serial data inputs.UART IrDA data input when IrDA mode is enabled (seeabove).Serial Port Pins – All ModesPin Dir1Name Description89, 76, 71, 57 I(h) DCD[3:0]# Active-low modem data-carrier-detect input 84, 79, 65, 60O(h) O(h) O(h) DTR[3:0]#485_En[3:0]Tx_Clk_Out[3:0]These four pins are present in all modes but they can serveone of three functions, as follows:Active-low modem data-terminal-ready output. If automatedDTR# flow control is enabled, the DTR# pin is asserted anddeasserted if the receiver FIFO reaches or falls below theprogrammed thresholds, respectively.In RS485 half-duplex mode, the DTR# pin may beprogrammed to reflect the state of the transmitter empty bitto automatically control the direction of the RS485transceiver buffer (see register ACR[4:3]).Transmitter 1x clock (baud rate generator output). Forisochronous applications, the 1x (or Nx) transmitter clockmay be asserted on the DTR# pins (see register CKS[5:4]).83, 80, 64, 61 O(h) RTS[3:0]# Active-low modem request-to-send output. If automatedRTS# flow control is enabled, the RTS# pin is deassertedand reasserted whenever the receiver FIFO reaches or fallsbelow the programmed thresholds, respectively.85, 78, 67, 59 I(h) CTS[3:0]# Active-low modem clear-to-send input. If automated CTS#flow control is enabled, upon deassertion of the CTS# pin,the transmitter will complete the current character and enterthe idle mode until the CTS# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the CTS# pin.86, 77, 66, 58I(h) I(h) DSR[3:0]#Rx_Clk_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:Active-low modem data-set-ready input. If automated DSR#flow control is enabled, upon deassertion of the DSR# pin,the transmitter will complete the current character and enterthe idle mode until the DSR# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the DSR# pin.External receiver clock for isochronous applications. TheRx_Clk_In is selected when CKS[1:0] = ‘01’.90, 75, 70, 56 I(h)I(h) RI[3:0]#Tx_Clk_In[3:0]Active-low modem Ring-Indicator inputExternal transmitter clock. This clock can be used by thetransmitter (and indirectly by the receiver) when CKS[6]=’1’.Clock Interface Pins – All ModesPin Dir 1 Name Description49 I/OXTLOCrystal oscillator output when OSCDIS = ‘0’.External clock source input when OSCDIS = ‘1’48 I XTLI Crystal oscillator input when OSCDIS = ‘0’, up to 20MHz.N/C when OSCDIS = ‘1’45 I OSCDIS Oscillator disable.When 0, the internal crystal oscillator is enabled and a crystal needs to be attached to XTLI/XTLO.XTLSEL must be set according to the crystal frequency that is used (up to 20Mhz).When 1, the internal crystal oscillator is disabled and an external oscillator source (up to 60MHz) can be input to XTLO. XTLI is N/C and XTLSEL must be 0130 I XTLSEL Defines the frequency of the crystal attached to XTLI/XTLO(when OSCDIS = ‘0’)0 = 1 MHz – 12 MHz 1 = 12 MHz – 20 MHz8-bit Local Bus – Mode 0Pin Dir 1 Name Description 111O UART_CLK_Out Buffered crystal output. This clock can drive external UARTsconnected to the local bus. Can be enabled / disabled by software.123 O(h) LBRST Local bus active-high reset. 124 O LBRST# Local bus active-low reset. 104 O LBDOUT Local bus data out enable. This pin can be used by externaltransceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode.74 O LBCLK Buffered PCI clock. Can be enabled / disabled by software. 114, 115, 116, 117 O(h) O(h) LBCS[3:0]# LBDS[3:0]# Local bus active-low Chip-Select (Intel mode).Local bus active-low Data-Strobe (Motorola mode).112 O O LBWR# LBRDWR# Local bus active-low write-strobe (Intel mode).Local bus Read-not-Write control (Motorola mode).113 O Z LBRD# Hi-Z Local bus active-low read-strobe (Intel mode).Permanent high impedance (Motorola mode).105, 106, 108, 109 118, 119, 120, 122 O(h) LBA[7:0] Local bus address signals. 96, 97, 98, 99 100, 101, 102, 103I/O(h) LBD[7:0] Local bus data signals.Parallel Port – Mode 1Pin Dir 1 NameDescription123 I(h) I(h) ACK#INTR#Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place.Identical function to ACK# (EPP mode).122 I(h) PEPaper Empty. Activated by printer when it runs out of paper. 120 I(h) I(h) BUSYWAIT#Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data.Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles.109 OD(h) O(h) SLIN#ADDRSTB#Select (SPP mode). Asserted by host to select the peripheral.Address strobe (EPP mode) provides address read and write strobe.119 I(h) SLCT Peripheral selected. Asserted by peripheral when selected. 118 I(h) ERR#Error. Held low by the peripheral during an error condition. 108 OD(h) O(h) INIT#INIT#Initialize (SPP mode). Commands the peripheral to initialize.Initialize (EPP mode). Identical function to SPP mode. 106 OD(h) O(h) AFD#DATASTB# Auto Feed (SPP mode, open-drain).Data strobe (EPP mode) provides data read and write strobe.105 OD(h) O(h) STB#WRITE#Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0].Write (EPP mode). Indicates a write cycle when low and a read cycle when high . 96, 97, 98, 99, 100, 101, 102, 103I/O(h) PD[7:0] Parallel data bus.104OPDOUTParallel port data out enable. This pin should be used by external transceivers for 5 V signaling; it is high when PD[7:0] are in output mode and low when they are in input mode.Multi-purpose and External Interrupt Pins – All ModesPin Dir1Name DescriptionMODE0 1135 --135I/O(h)OMIO0NCMulti-purpose I/O 0. Can drive high or low, or assert a PCIinterrupt.Output Driving ‘0’. Can be left as a No-connect.134 134 134134I/O(h)MIO1NCMulti-purpose I/O 1. Can drive high or low, or assert a PCIinterrupt (as long as LCC[6:5] = “00”).Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)Can be left as a No-Connect.133 133 133133I/O(h)IMIO2PME_InMulti-purpose I/O 2. When LCC[7] = 0, this pin can drive highor low, or assert a PCI interrupt.Input power management event. When LCC[7] is set thisinput pin can assert a function 1 PME#.93, 94, 95, 125, 126, 127, 128, 132 I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCIinterrupt.EEPROM Pins – All ModesPin Dir1Name Description53 OEE_CKEEPROMclock.52 O EE_CS EEPROM active-high Chip Select.54 IU(h) EE_DI EEPROM data in, with internal pull-up.When the serial EEPROM is connected, this pin should bepulled up using a 1-10k resistor. When the EEPROM is notused the internal pull-up is sufficient.Pin to be connected to the external EEPROM’s EE_DO pin(if used).51 O EE_DO EEPROM data out.Pin to be connected to the external EEPROM’s EE_DI pin(if used).Table 1: Pin DescriptionsI/O Direction Key P_I PCI input 3.3 V Only P_O PCI output / PCITristates 3.3 V Only P_I/O PCI bi-directional 3.3 V Only P_OD PCI open drain 3.3 V OnlyI Input LVTTL level I(h) Input LVTTL level, 5 V tolerant IU(h) Input with internal pull-up LVTTL level, 5 V tolerant I/O(h) Bi-Directional LVTTL level, 5 V tolerantO Output Standard Output O(h) Output 5 V tolerant (High Voltage BI-Direct in output mode) OD Open drain Standard Open-drain Output OD(h) Open drain 5 V tolerant (High Voltage BI-Direct in open-drain mode) NC No connectG Ground V VoltageMiscellaneous PinsPin Dir 1 NameDescription44 IMODEMode selector Pin0 : Function 0 : Quad UART. Function 1 : 8-bit local bus.1 : Function 0 : Quad UART. Function 1 : Parallel port.Power and GroundPinType Name Description19, 42, 47, 69, 88, 107, 131, 148VVDDPower Supply (3.3 V)11, 22, 36, 140, 156, 162, 173 V VIOPCI I/O Universal VoltageDefines the (clamping) voltage of the PCI I/O Buffers.To be connected to the VIO pin of the PCI connector. 3, 4, 9, 16, 21, 29, 30, 37, 38, 43, 46, 68, 87, 92, 110, 121, 129, 141, 143, 145, 152, 153, 159, 166, 172G GNDPower Supply Ground (0 V)4C ONFIGURATION AND O PERATIONThe OXuPCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 3.0 and the PCI Power Management Specification, Revision 1.1.The OXuPCI954 affords maximum configuration flexibility by treating the internal UARTs, the local bus and the parallel port as separate logical functions. Each function has its own configuration space and is therefore recognized and configured by the PCI BIOS separately. The functions used are configured by the Mode Selection Pin as shown in Section 1 OXuPCI954 Device Modes.The OXuPCI954 is configured by system start-up software during the bootstrap process that follows bus reset. The system scans the bus and reads the vendor and device identification codes from any devices it finds. It then loads device-driver software according to this information and configures the I/O, memory and interrupt resources. Device drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by PCI.Each function operates as though it was a separate device. However there are a set of Local Configuration Registers that can be used to enable signals and interrupts, configure timings, and improve the efficiency of multi-port drivers. This architecture enables separate drivers to be installed for each function. Generic port drivers can be hooked to use the functions individually, or more efficient multi-port drivers can hook both functions, accessing the Local Configuration Registers from either.All registers default after reset to suitable values for typical applications such a 4/8 port serial, or combo 4-port serial/1-port parallel add-in cards. However, all identification, control and timing registers can be redefined using an optional serial EEPROM.5PCI T ARGET C ONTROLLER5.1OperationThe OXuPCI954 responds to the following PCI transactions:-•Configuration access: The OXuPCI954 responds to type 0 configuration reads and writes if the IDSELsignal is asserted and the bus address is selecting theconfiguration registers for function 0 or 1. The devicewill respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Anyother configuration transaction will be ignored by theOXuPCI954.•I/O reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers(BARs). If the address falls within one of the assignedranges, the device will respond to the I/O transactionby asserting DEVSEL#. Data transfer follows thisaddress phase. For the UARTs and 8-bit local buscontroller, only byte accesses are possible. For I/Oaccesses to these regions, the controller comparesAD[1:0] with the byte-enable signals as defined in thePCI specification. The access is always completed;however if the correct BE signal is not present thetransaction will have no effect.•Memory reads/writes: These are treated in the same way as I/O transactions, except that the memoryranges are used. Memory access to single-byte regions is always expanded to DWORDs in theOXuPCI954. In other words, OXuPCI954 reserves aDWORD per byte in single-byte regions. The deviceallows the user to define the active byte lane usingLCC[4:3] so that in Big-Endian systems the hardwarecan swap the byte lane automatically. For Memorymapped access in single-byte regions, the OXuPCI954 compares the asserted byte-enable withthe selected byte-lane in LCC[4:3] and completes theoperation if a match occurs, otherwise the access willcomplete normally on the PCI bus, but it will have noeffect on either the internal UARTs or the local buscontroller.•All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored.The OXuPCI954 will complete all transactions as disconnect-with-data, i.e. the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signaled in response to any access while the OXuPCI954 is reading from the serial EEPROM.The OXuPCI954 performs medium-speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OXuPCI954 as a target, so a bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required.The device supports any combination of byte-enables to the PCI Configuration Registers and the Local Configuration Registers. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read.The OXuPCI954 performs parity generation and checking on all PCI bus transactions as defined by the standard. Note this is entirely unrelated to serial data parity which is handled within the UART functional modules themselves. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct.The OXuPCI954 does not support any kind of caching or data buffering in addition to that already provided within the UARTs by the transmit and receive data FIFOs. In general, registers in the UARTs and on the local bus can not be pre-fetched because there may be side-effects on read.5.2Configuration SpaceThe OXuPCI954 is a dual-function device, where each logical function has its own configuration space. All required fields in the standard header are implemented, plus the Power Management Extended Capability register set. The format of the configuration space is shown in the following tables.In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0.。

SGM8541中文资料

SGM8541 SGM8542 SGM85441.1MHz, 42µA, Rail-to-Rail I/O CMOS Operational AmplifierShengbang Microelectronics Co, LtdREV . BELECTRICAL CHARACTERISTICS : V S = +5V (At R L = 100kΩ connected to Vs/2,and V OUT= Vs/2, unless otherwise noted)Specifications subject to change without notice.PACKAGE/ORDERING INFORMATIONMODEL ORDERNUMBERPACKAGEDESCRIPTIONPACKAGEOPTIONMARKINGINFORMATIONSGM8541XN5/TR SOT23-5 Tape and Reel, 3000 8541 SGM8541SGM8541XS/TR SO-8 Tape and Reel, 2500 SGM8541XSSGM8542XS/TR SO-8 Tape and Reel, 2500 SGM8542XS SGM8542SGM8542XMS/TR MSOP-8 Tape and Reel, 3000 SGM8542XMSSGM8544XS/TR SO-16 Tape and Reel, 2500 SGM8544XS SGM8544SGM8544XTS TSSOP-16 Tape and Reel, 3000 SGM8544XTSABSOLUTE MAXIMUM RATINGS Supply Voltage, V+ to V- ........................................... 7.5 V Common-Mode Input Voltage...........................................(–V S )– 0.5 V to (+V S) +0.5V Storage Temperature Range.................. –65℃ to +150℃Junction Temperature ............................................... 150℃Operating Temperature Range ........... –55℃ to +150℃Package Thermal Resistance @ T A = 25℃SOT23-5, θJA.............................................................. 190/W℃SO-8, θJA......................................................................125/W℃MSOP-8, θJA.............................................................. 216/W℃SO-16, θJA..................................................................... 82/W℃TSSOP-16, θJA............................................................ 105/W℃Lead Temperature Range (Soldering 10 sec).....................................................260℃ESD Susceptibility HBM.. (4000V)MM (400V)NOTES1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTIONThis integrated circuit can be damaged by ESD. Shengbang Micro-electronics recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.TYPICAL PERFORMANCE CHARACTERISTICSAt T A = +25℃, V S = +5V , and R L = 100k Ω connected to Vs/2,unless otherwise noted.Small-Signal Step Response Large-Signal Step Response2µs/div 10µs/div20m V /d i v500m V /d i vG = +1C L = 100pF R L= 100K ΩG = +1C L = 100pF R L= 100K ΩTYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃, V S = +5V, and R L = 100kΩconnected to Vs/2,unless otherwise noted.TYPICAL PERFORMANCE CHARACTERISTICS At T A = +25℃, V S = +5V, and R L = 100kΩconnected to Vs/2,unless otherwise noted.Overload Recovery TimeTime(2µs/div)Vs = 5VG = -5V IN= 500mV 2.5V0V500mV0VAPPLICATION NOTESDriving Capacitive LoadsThe SGM854X can directly drive 250pF in unity-gain without oscillation. The unity-gain follower (buffer) is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers and this results in ringing or even oscillation. Applications that require greater capacitive drive capability should use an isolation resistor between the output and the capacitive load like the circuit in Figure 1. The isolation resistor R ISO and the load capacitor C L form a zero to increase stability. The bigger the R ISO resistor value, the more stable V OUT will be. Note that this method results in a loss of gain accuracy because R ISO forms a voltage divider with the R LOAD.V IN V OUTFigure 1. Indirectly Driving Heavy Capacitive LoadAn improvement circuit is shown in Figure 2, It provides DC accuracy as well as AC stability. R F provides the DC accuracy by connecting the inverting signal with the output, C F and R Iso serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback loop.V IN V OUTFigure 2. Indirectly Driving Heavy Capacitive Load with DC AccuracyFor no-buffer configuration, there are two others ways to increase the phase margin: (a) by increasing the amplifier’s gain or (b) by placing a capacitor in parallel with the feedback resistor to counteract the parasitic capacitance associated with inverting node. Power-Supply Bypassing and Layout The SGM854X family operates from either a single +2.5V to +5.5V supply or dual ±1.25V to ±2.75V supplies. For single-supply operation, bypass the power supply V DD with a 0.1µF ceramic capacitor which should be placed close to the V DD pin. For dual-supply operation, both the V DD and the V SS supplies should be bypassed to ground with separate 0.1µF ceramic capacitors. 2.2µF tantalum capacitor can be added for better performance.VnVpV SSV SS(GND)Figure 3. Amplifier with Bypass CapacitorsTypical Application Circuits Differential AmplifierThe circuit shown in Figure 4 performs the difference function. If the resistors ratios are equal ( R4 / R3 = R2 / R1 ), thenV OUT = ( Vp – Vn ) × R2 / R1 + Vref.Vn VpOUT Figure 4. Differential AmplifierInstrumentation AmplifierThe circuit in Figure 5 performs the same function as that in Figure 4 but with the high input impedance.Vn VpV OUT Figure 5. Instrumentation AmplifierLow Pass Active FilterThe low pass filter shown in Figure 6 has a DC gain of ( - R2 / R1 ) and the –3dB corner frequency is 1/2πR2C. Make sure the filter is within the bandwidth of the amplifier. The Large values of feedback resistors can couple with parasitic capacitance and cause undesired effects such as ringing or oscillation in high-speed amplifiers. Keep resistors value as low as possible and consistent with output loading consideration.V INV OUT Figure 6. Low Pass Active FilterPACKAGE OUTLINE DIMENSIONS SOT23-5PACKAGE OUTLINE DIMENSIONS SO-8PACKAGE OUTLINE DIMENSIONS MSOP-8PACKAGE OUTLINE DIMENSIONS SO-16PACKAGE OUTLINE DIMENSIONS TSSOP-16REVISION HISTORYLocation Page 11/06— Data Sheet changed from REV.A to REV.BChanges to ABSOLUTE MAXIMUM ATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 3Shengbang Microelectronics Co, LtdUnit 3, ChuangYe PlazaNo.5, TaiHu Northern Street, YingBin Road Centralized Industrial ParkHarbin Development ZoneHarbin, HeiLongJiang 150078P.R. ChinaTel.: 86-451-84348461Fax: 86-451-84308461。

电脑技术基础

②如果将CMOS中设置无错误，则不严重的故障不会影响BIOS自检的继续，而最终出现“00”或“FF”。
③一开机就出现“00”或“FF”或其它起始代码并且不变化则为板没有运行起来。
2、本表是按代码值从小到大排序，卡中出码顺序不定。
3、未定义的代码表中未列出。
4、对于不同BIOS（常用的AMI、Award、Phoenix）用同一代码所代表的意义有所不同，因此应弄清您所检测的电脑是属于哪一种类型的BIOS，您可查问你的电脑使用手册，或从主板上的BIOS芯片上直接查看，也可以在启动屏幕时直接看到。
945GC：945G的简化版，支持前端总线频率(MHz) 533/800，内存最高传输标准 DDR2 533，最大内存容量 2GB，双通道内存支持，显卡插槽 PCI Express x16，集成显卡Intel Graphics Media Accelerator 950。
内存报警：
两种BIOS报警铃声意义:
不断长声响:内存坏或未插好
不断响:电源\显示卡\显示器未连接好
重复响:电源问题
无声无显示:电源问题
AMI BIOS
1短:内存刷新失败,换内存
2短:内存ECC校验错误.在CMOS中关闭校验,选DISABLED.或换内存
3短:系统基本内存(第一个64K)错误,换内存
4短:系统时钟错误
主板认识(GIGA)
技嘉主板编号以“GA-”开头，其后紧跟数字和英文字母，用来区分具体主板的规格。编号石油“GA-”+“支持CPU类型”+“主板采用的芯片组型号”+“使用板型”+“后缀”构成
技嘉主板可以通过数字来区分主板支持的处理器类型，现在有5、6、7、8四种。例如支持Intel系列的处理器采用“6”开头（支持Pentium 4的以“8”开头），而支持AMD系列处理器的主板以数字“7”开头。接下来的英文字母代表主板采用的芯片组型号，A表示采用Ali公司的主板芯片组，现在已经很少见了、B表示的是Intel 440BX，很“经典”的产品、字母C表示采用Intel i820芯片组、D表示AMD 760芯片组、O指采用Intel i815芯片组、W表示采用Intel BX/LX/ZX芯片组，而V说明主板采用VIA芯片组、S表示采用SiS芯片组、Z最早指的是Intel 440 ZX，如今又加上了KT 133/KM 133等。第三位英文字母表示主板的版型，X表示ATX版型，（标准型）、M表示Micro ATX版型（小版型）、F是指采用Flex ATX版型（目前最小的版型）、A则代表采用Baby AT版型。最后的后缀编号，它用以区分具体主板品种，技嘉主板的后缀编号一般用1到4位的字母或数字，而且可以相互组合使用

奇冠电脑主板诊断卡--代码表

五、用户必读1、故障代码含义速查表是按代码值从小到大排序，卡中出码顺序由电脑主板上BIOS确定;2、四位代码中分为两组两位代码。

前两位（千位和百位）为一组；后两位（十位和个位）为另一组。

您分别查看这两组代码的含义说明既不仅知道被测计算机故障自检不能通过的部件（由千位和百位显示）；并且知道计算机故障自检到最后所通过的部件（由十位和个位显示）;3、未定义的代码表中未能列出;4、对于不同BIOS（常用的AMI、Award、Phoenix）同一代码所代表的意义则不同，因此应弄清您所检测的电脑是属于哪一种类型的BIOS,您可查阅您的电脑使用手册，或从电脑主板上的BIOS芯片上直接查看，也可以在启动的屏幕中直接看到;5、有少数电脑主板的PCI槽只送出一部分代码，但ISA槽则有完整自检代码输出。

且目前已发现有极个别原装机电脑主板的ISA槽无代码输出，而PCI槽则有完整代码输出，故建议您在查看代码不成功时，将本双槽卡换到另一种插槽试一下。

另外，同一块电脑主板的不同PCI槽，有的槽有完整代码送出，如DELL810台式电脑主板上只有靠近CPU的一个PCI槽有完整代码显示，一直变化到“00”或“FF”，而其它PCI槽走到“38”后则不继续变化;6、复位信号所需时间ISA与PCI不一定同步，故有可能ISA开始出代码，但PCI的复位灯还未熄，故PCI 代码停在起始代码上;7、由于电脑主板品种和结构的多样性及BIOS POST 代码不断更新，令紧接在代码后面的查找故障部件和围的准确性受到影响，故《代码含义速查表》中说明的故障部件和围只能作为参考;六、指示灯功能速查表+5V、+12V、OSC和FRAME、CLK、RUN、-5V和+3V3、-12V、BIOS和IRDY、RST灯名信号名称说明CLK 总线时钟不论ISA或PCI只要电脑（无CPU等）接通电源就应常亮，否则CLK信号坏。

BIOS 基本输入输出电脑主板运行时对BIOS有读操作时就闪亮。

常用三极管参数大全

玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理。

w79e2051_4051(中文)

8-位微控制器Publication Release Date: March 25, 2008目录-1 概述.............................................................................................................................................42 特性.............................................................................................................................................43 产品型号信息...............................................................................................................................5 3.1无铅(RoHS) 产品型号信息表列 (5)4 管脚配置......................................................................................................................................5 5 管脚描述......................................................................................................................................6 6功能描述......................................................................................................................................7 6.1 I/O 端口...........................................................................................................................7 6.2 串行 I/O...........................................................................................................................7 6.3 定时器.............................................................................................................................7 6.4 中断.................................................................................................................................7 6.5 数据指针..........................................................................................................................7 6.6CPU 架构........................................................................................................................7 6.6.1 ALU...................................................................................................................................7 6.6.2 累加器(ACC).....................................................................................................................8 6.6.3 B 寄存器............................................................................................................................8 6.6.4 程序状态字寄存器(PSW)...................................................................................................8 6.6.5 片内便签RAM....................................................................................................................8 6.6.6 堆栈指针............................................................................................................................8 7 内存组织......................................................................................................................................9 7.1 程序内存..........................................................................................................................9 7.2 数据存储器......................................................................................................................9 7.3 寄存器的映射..................................................................................................................9 7.4 工作寄存器....................................................................................................................11 7.5 位寻址区........................................................................................................................11 7.6堆栈 (11)8 特殊功能寄存器.........................................................................................................................13 9 指令...........................................................................................................................................34 9.1 指令时序........................................................................................................................42 10电源管理 (45)10.1 空闲模式........................................................................................................................45 10.2掉电模式 (45)11 复位条件 (47)11.1复位源 (47)11.1.1外部复位 (47)11.1.2上电复位 (POR) (47)11.1.3欠压复位(BOR) (47)11.1.4看门狗定时器复位 (47)11.2复位状态 (47)12INTERRUPTS (50)12.1中断源 (50)12.2中断优先级 (51)12.3中断响应时间 (52)13可编程定时器/计数器 (54)13.1定时器/计数器0&1 (54)13.2时基选择 (54)13.2.1模式0 (54)13.2.2模式1 (55)13.2.3模式2 (55)13.2.4模式3 (56)14数据存储器 (56)15看门狗定时器 (58)15.1看门狗控制 (59)15.2看门狗时钟控制 (59)16串行 (UART) (60)16.1模式 0 (60)16.2模式1 (61)16.3模式 2 (62)16.4模式 3 (63)16.5帧错误检测 (64)16.6多机通信 (64)17脉宽调制(PWM) (66)18模拟比较器 (68)18.1模拟比较器中断 (68)19时控访问保护 (70)20I/O端口配置 (72)20.1准双向端口模式配置 (72)20.2开漏端口模式配置 (73)21振荡器 (74)21.1片内RC振荡器选项 (74)21.2外部时钟输入选项 (74)22电源监视功能 (75)22.1欠压检测 (75)22.2ICP(在电路编程) FLASH 编程 (76)23配置位 (77)23.1CONFIG0 (77)23.2CONFIG1 (78)24电气特性 (79)24.1极限参数 (79)24.2DC 电气特性 (80)24.3模拟比较器电气特性 (82)24.4AC 电气特性 (83)24.5外部时钟特性 (83)24.6RC OSC 和 AC 规格 (83)25典型应用电路 (85)26封装尺寸 (86)26.120-pin SOP (86)26.220-pin DIP (87)27版本历史 (88)华邦电子（上海）集成电路有限公司（8位单片机）uC微控制器产品部上海市长宁区延安西路2299号27楼（邮编200336）电话：************传真：************Publication Release Date: March 25, 20081 概述W79E4051/2051系列是一个快速51微控制器，它有可以在系统编程的(ICP)应用程序Flash EPROM，可以使用烧写器在系统中编程。

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OCXO SERIES 4000
n FEATURES APPLICATIONS Excellent frequency stability - SATCOM
Mechanical / Electrical frequency adjustment available - BASE STATIONS
- TEST INSTRUMENTS
n ELECTRICAL PERFORMANCE
PARAMETER OCXO SERIES 4000
AT CUT CRYSTAL SC CUT CRYSTAL Supply voltage, nom. 15V, 12V, 5V ±5% Standard
Power dissipation steady state 2.5 Watt Max.
Heat up power 5 Watt Max
Heat up time. 7 min Max
Frequency range 1 To 160 MHz Standard
Frequency Adjustment:
Electrical (0 to 5V) Electrical (0 to 10V) Mechanical ±10PPM Min
±15PPM Min
±1.5PPM Min
±0.7PPM Min
±1PPM Min
±0.6 PPM Min
±0.05 PPM
±0.1 PPM
±0.002 PPM
±0.005 PPM
Freq. stability vs. temperature
LX: 0°C to 60°C
FZ: -30°C to 70°C
(Standard, contact factory for different temp ranges and stabilities) Freq. stability vs. supply
changes
±0.005 PPM Max for ±5% Change ±0.002 PPM Max for ±5% Change
Freq. stability vs. load
changes
±0.005 PPM Max for ±5% Change ±0.001 PPM Max for ±5% Change
Long term stability (Aging) ± 1.5 PPM Max for 10 Years
± 0.3 PPM Max for 1 Years
±0.002 PPM/Day Max. ±0.6 PPM Max for 10 Years ±0.05 PPM Max for 1 Years ±0.0005 PPM/Day Max.
Output HCMOS/TTL/Sine 0 to +13dBm Harmonics, Sub Harmonics -30dBc(Sine Output)
Spurious -75dBc(Sine Output)
Duty cycle 40/60% to 60/40%(HCMOS)
Rise / fall time 10nS Max. (HCMOS,10%~90%Vout, 90%~10%Vout) Short term Stability (10MHz) 1 E-10 /Sec 5 E-11 /Sec
Phase Noise typical under static conditions
(Sine Output 10MHZ) Offset Phase Noise
10Hz -95 dBc/Hz
100Hz -125 dBc/Hz
1000Hz -135 dBc/Hz
10000Hz -150 dBc/Hz
Offset Phase Noise
10Hz -115 dBc/Hz
100Hz -135 dBc/Hz
1000Hz -145 dBc/Hz
10000Hz -150 dBc/Hz
Note: All Typical parameters for a 10MHz output and 5V Supply, for different frequencies consult factory
n HOW TO ORDER (PART NUMBER)
Prefix Output Type Cut Type
Series Revision Temperature Range Stability Frequency
Supply Voltage OX
1:TTL 2:HCMOS 3:ACMOS 4:LVCMOS 5:100K ECL 6:SINE 7:10K ECL 8: PECL 9:CUSTOM
0:AT (No Vcontrol ) 1: SC (No Vcontrol ) 2: AT (Mechanical Adj) 3: SC (Mechanical Adj) 4: AT (Elect Vcontrol) 5: SC (Elect Vcontrol) 6: AT (Mech & Elect.) 7: SC (Mech & Elect.)
4X:4000 40:
Height=
1”/25.4mm
41:
Height=
2”/50.8mm
42:
Height=
4”/101.6mm
44~49:
Odd Height
A
First letter Lowest Temperature,
Second letter Highest Temperature: From A=-55°C to Z=+70°C, Then: 1=+75°C, 2=+80°C, 3=+85°C… in 5°C steps Example: LZ: +0°C to +70°C LX: +0°C to +60°C FZ: -30°C to +70°C D3: -40°C to +85°C
Value x
10E-2 in PPM
Example 28=
0.28PPM 10= 0.1PPM
In MHZ
5: 5V 12; 12V 15; 15V。