2.42寸UG-2864ASWPG01(1309驱动,连接器款)

Product Specification(Preliminary)Part Name:OEL Display ModuleCustomer Part ID:WiseChip Part ID: UG-2864ASWPG01Doc No.:SAS1-090BH-ACustomer:Approved byTopwin international corp.,limitedApproved byTopwin international corp.,limitedRevised HistoryPart Number RevisionUG-2864ASWPG01A NewRevision ContentRevised on June 6, 2012iTopwin international corp.,limitedContentsRevision History ................................................................................................................................i Contents...........................................................................................................................................ii 1. Basic Specifications................................................................................................................ 1~51.1 Display Specifications ................................................................................................................. 1 1.2 Mechanical Specifications............................................................................................................ 1 1.3 Active Area / Memory Mapping & Pixel Construction ...................................................................... 1 1.4 Mechanical Drawing.................................................................................................................... 2 1.5 Pin Definition ............................................................................................................................. 3 1.6 Block Diagram............................................................................................................................ 5 2. Absolute Maximum Ratings ........................................................................................................6 3. Optics & Electrical Characteristics ....................................................................................... 7~11 3.1 Optics Characteristics.................................................................................................................. 7 3.2 DC Characteristics ...................................................................................................................... 7 3.3 AC Characteristics....................................................................................................................... 83.3.1 68XX-Series MPU Parallel Interface Timing Characteristics.................................................... 8 3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics.................................................... 9 3.3.3 Serial Interface Timing Characteristics .............................................................................. 10 3.3.4 I2C Interface Timing Characteristics ................................................................................. 11 4. Functional Specification.....................................................................................................12~14 4.1 Commands .............................................................................................................................. 12 4.2 Power down and Power up Sequence......................................................................................... 12 4.2.1 Power up Sequence ........................................................................................................ 12 4.2.2 Power down Sequence .................................................................................................... 12 4.3 Reset Circuit ............................................................................................................................ 12 4.4 Actual Application Example........................................................................................................ 13 5. Reliability ..................................................................................................................................15 5.1 Contents of Reliability Tests ...................................................................................................... 15 5.2 Failure Check Standard ............................................................................................................. 15 6. Outgoing Quality Control Specifications ............................................................................16~19 6.1 Environment Required .............................................................................................................. 16 6.2 Sampling Plan .......................................................................................................................... 16 6.3 Criteria & Acceptable Quality Level............................................................................................. 16 6.3.1 Cosmetic Check (Display Off) in Non-Active Area............................................................... 16 6.3.2 Cosmetic Check (Display Off) in Active Area...................................................................... 18 6.3.3 Pattern Check (Display On) in Active Area......................................................................... 19 7. Package Specifications..............................................................................................................20 8. Precautions When Using These OEL Display Modules .......................................................21~23 8.1 Handling Precautions ................................................................................................................ 21 8.2 Storage Precautions.................................................................................................................. 21 8.3 Designing Precautions............................................................................................................... 22 8.4 Precautions when disposing of the OEL display modules .............................................................. 22 8.5 Other Precautions..................................................................................................................... 22 Warranty ........................................................................................................................................23 Notice .............................................................................................................................................23iiTopwin international corp.,limited1. Basic Specifications1.1 Display Specifications1) Display Mode: 2) Display Color: 3) Drive Duty:Passive Matrix Monochrome (White) 1/64 Duty1.2 Mechanical Specifications1) Outline Drawing: 2) Number of Pixels: 3) Panel Size: 4) Active Area: 5) Pixel Pitch: 6) Pixel Size: 7) Weight:According to the annexed outline drawing 128 × 64 60.50 × 37.00 × 2.00 (mm) 55.01 × 27.49 (mm) 0.43 × 0.43 (mm) 0.40 × 0.40 (mm) 8.60 (g)1.3 Active Area / Memory Mapping & Pixel Construction P0.43x128-0.03=55.01 (A/A)(0, 0)"A"Driver IC Memory Mapping (Full 128 x 64)P0.43x64-0.03=27.49 (A/A)Segment 127( Column 1 )Common 32( Row 63 )Common 63( Row 1 )0.43 0.4Detail "A" Scale (10:1)Segment 0( Column 128 )Common 0( Row 64 )Common 31( Row 2 )(127, 63)10.40.43Topwin international corp.,limited1.4 Mechanical Drawing0.5±0.5 (1.75) (2.75)"A"60.5±0.2 (Panel Size) 60.5±0.2 (Cap Size)59.5 (Polarizer) 57.01 (V/A)P0.43x128-0.03=55.01 (A/A)105Remove Tape t=0.15mm Max2±0.1(4.35)ItemDateA20120531Remark Original Drawing(2.08) (1.08) 0.5±0.58Polarizer t=0.2mmP0.43x64-0.03=27.49 (A/A) 29.49 (V/A) 31.5 (Polarizer)32.408±0.2 (Cap Size) 37±0.2 (Panel Size) (73)(34) (1.35)Active Area 2.42" 128 x 64 PixelsSegment 127 ( Column 1 )Common 32 ( Row 63 )Common 63 ( Row 1 )Segment 0 ( Column 128 )Common 0 ( Row 64 )Common 31 ( Row 2 )GlueProtective Tape 15x3.5x0.05mm8.5±0.12-φ0.8±0.125±0.2 36±0.310.4±0.12-φ 1±0.11243±0.3 6±0.2N.C. (GND) VLSS VSS N.C. VDD BS1 BS2 CS# RES# D/C# R/W# E/ R D# D0 D1 D2 D3 D4 D5 D6 D7 IREF VCOMH VCC N.C. (GND)Notes:W=0.35±0.030.5±0.1P1.0x(31-1)=11.5±0.05(24)12.5±0.21. Color: White 2. Driver IC: SSD1309 3. FPC Number: UT-0205-P05 4. Interface:8-bit 68XX/80XX Parallel, 4-wire SPI, I2C 5. General Tolerance: ±0.30 6. The total thickness (2.10 Max) is without polarizer protective film & remove tape.The actual assembled total thickness with above materials should be 2.35 Max.(2.3)Customer Approval Signature0.43 0.40.4 0.434.5±0.5 (Stiffener) Contact Side0.3±0.03Detail "A" Scale (10:1)Topwin international corp.,limitedUnless Otherwise SpecifiedUnitmmGeneral RoughnessToleranceDimension ±0.3Angle±1TitleBy DateUG-2864ASWPG01 Folding Type OEL Display Module Pixel Number: 128 x 64, Monochrome, COG PackageDrawn Dora Yang 20120531E.E. Ting-Kuo Hu20120531Panel / E. Ivy Lo20120531P.M. Tiffany Hsu 20120531PinSymbol1N.C. (GND)2VLSS3VSS4N.C.5VDD6BS17BS28CS#9RES#10D/C#11R/W#12E/RD#13D014D115D216D317D418D519D620D721IREF22VCOMH23VCC24N.C. (GND)Drawing Number DMX2864CNGFBHMaterialRev. ASoda Lime / PolyimideScale Sheet Size 1:1 1 of 1 A32Topwin international corp.,limited1.5 Pin DefinitionPin Number SymbolPower Supply5VDD3VSS23 2 Driver 21VCC VLSSIREF22 InterfaceVCOMH6BS17BS29RES#8CS#10D/C#12E/RD#11R/W#I/OFunctionPPower Supply for Logic Circuit This is a voltage supply pin. It must be connected to external source.Ground of Logic CircuitP This is a ground pin. It also acts as a reference for the logic pins. It must beconnected to external ground.Power Supply for OEL PanelP This is the most positive voltage supply pin of the chip. It must be suppliedexternally.PGround of Analog Circuit This is an analog ground pin. It should be connected to VSS externally.Current Reference for Brightness AdjustmentI This pin is segment current reference pin. A resistor should be connectedbetween this pin and VSS. Set the current at 10μA.Voltage Output High Level for COM SignalO This pin is the input pin for the voltage output high level for COM signals. Acapacitor should be connected between this pin and VSS.Communicating Protocol SelectThese pins are MCU interface selection input. See the following table:II2CBS1BS2104-wire Serial008-bit 68XX Parallel018-bit 80XX Parallel11Power Reset for Controller and DriverI This pin is reset signal input. When the pin is low, initialization of the chip isexecuted. Keep this pin pull high during normal operation.Chip SelectI This pin is the chip select input. The chip is enabled for MCU communication onlywhen CS# is pulled low.Data/Command ControlThis pin is Data/Command control pin. When the pin is pulled high, the input atD7~D0 will be interpreted as display data. When the pin is pulled low, the inputat D7~D0 will be transferred to the command register.IWhen the pin is pulled high and serial interface mode is selected, the data at SDIN will be interpreted as data. When it is pulled low, the data at SDIN will betransferred to the command register. In I2C mode, this pin acts as SA0 for slaveaddress selection.For detail relationship to MCU interface signals, please refer to the TimingCharacteristics Diagrams.Read/Write Enable or ReadThis pin is MCU interface input. When interfacing to a 68XX-seriesmicroprocessor, this pin will be used as the Enable (E) signal. Read/write operationIis initiated when this pin is pulled high and the CS# is pulled low. When connecting to an 80XX-microprocessor, this pin receives the Read (RD#)signal. Data read operation is initiated when this pin is pulled low and CS# ispulled low. When serial or I2C mode is selected, this pin must be connected to VSS.Read/Write Select or WriteThis pin is MCU interface input. When interfacing to a 68XX-seriesmicroprocessor, this pin will be used as Read/Write (R/W#) selection input. PullIthis pin to “High” for read mode and pull it to “Low” for write mode. When 80XX interface mode is selected, this pin will be the Write (WR#) input.Data write operation is initiated when this pin is pulled low and the CS# is pulledlow. When serial or I2C mode is selected, this pin must be connected to VSS.3Topwin international corp.,limited1.5 Pin Definition (Continued)Pin Number Symbol I/OFunctionInterface (Continued)13~20D0~D7Reserve 41, 24N.C. N.C. (GND)Host Data Input/Output BusThese pins are 8-bit bi-directional data bus to be connected to themicroprocessor’s data bus. When serial mode is selected, D1 will be the serialI/O data input SDIN and D0 will be the serial clock input SCLK. When I2C mode isselected, D2, D1 should be tired together and serve as SDAOUT, SDAIN in application and D0 is the serial clock input, SCL.Unused pins must be connected to VSS except for D2 in serial mode.-Reserved Pin The N.C. pin between function pins is reserved for compatible and flexible design.Reserved Pin (Supporting Pin)- The supporting pins can reduce the influences from stresses on the function pins.These pins must be connected to external ground as the ESD protection circuit.4Topwin international corp.,limited1.6 Block DiagramActive Area 2.42" 128 x 64 PixelsCommon 63 Common 32 Segment 127 Segment 0 Common 0 Common 31~~~~~SSD1309VLSS VSS VDD BS1 BS2 CS# RES# D/C# R/W# E/RD# D0 D7 IREF VCOMH VCC~C1C2R1C5C3C4MCU Interface Selection:BS1 and BS2Pins connected to MCU interface: D7~D0, E/RD#, R/W#, D/C#, RES#, and CS#C1, C3: 0.1μF C2: 4.7μF C4: 10μF C5: 4.7μF / 25V Tantalum Capacitor R1: 910kΩ, R1 = (Voltage at IREF - BGGND) / IREF5Topwin international corp.,limited2. Absolute Maximum RatingsParameterSymbolMinMaxUnitNotesSupply Voltage for Logic Supply Voltage for DisplayOperating Temperature Storage Temperature Life Time (80 cd/m2) Life Time (60 cd/m2)VDD-0.34V1, 2VCC015V1, 2TOP-4070°C3TSTG-4085°C330,000-hour450,000-hour4Note 1: All the above voltages are on the basis of “VSS = 0V”. Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of themodule may occur. Also, for normal operations, it is desirable to use this module under the conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate. Note 3: The defined temperature ranges do not include the polarizer. The maximum withstood temperature of the polarizer should be 80°C. Note 4: VCC = 13.0V, Ta = 25°C, 50% Checkerboard. Software configuration follows Section 4.4 Initialization. End of lifetime is specified as 50% of initial brightness reached. The average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions.6Topwin international corp.,limited3. Optics & Electrical Characteristics3.1 Optics CharacteristicsCharacteristicsSymbolConditionsBrightnessLbrC.I.E. (White)(x) (y)Dark Room ContrastCRNote 5 C.I.E. 1931Viewing Angle* Optical measurement taken at VDD = 2.8V, VCC = 13.0V. Software configuration follows Section 4.4 Initialization.Min Typ Max6080-0.25 0.29 0.33 0.27 0.31 0.35- >10,000:1 --Free-Unit cd/m2degree3.2 DC CharacteristicsCharacteristicsSymbolConditionsMin Typ Max UnitSupply Voltage for Logic Supply Voltage for DisplayHigh Level Input Low Level Input High Level Output Low Level Output Operating Current for VDDVDD1.652.83.3VVCCNote 512.5 13.0 13.5VVIH IOUT = 100μA, 3.3MHz 0.8×VDD-VDDVVIL IOUT = 100μA, 3.3MHz 0-0.2×VDDVVOH IOUT = 100μA, 3.3MHz 0.9×VDD-VDDVVOL IOUT = 100μA, 3.3MHz 0-0.1×VDDVIDD-180300μANote 6-18.5 23.1 mAOperating Current for VCCICCNote 7-27.1 33.9 mANote 8-42.3 52.9 mASleep Mode Current for VDD IDD, SLEEP-15μASleep Mode Current for VCC ICC, SLEEP-210μANote 5: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer’s request.Note 6: VDD = 2.8V, VCC = 13.0V, 30% Display Area Turn on. Note 7: VDD = 2.8V, VCC = 13.0V, 50% Display Area Turn on. Note 8: VDD = 2.8V, VCC = 13.0V, 100% Display Area Turn on.* Software configuration follows Section 4.4 Initialization.7Topwin international corp.,limited3.3 AC Characteristics 3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics:Symbol Descriptiontcycle tAS tAH tDW tDSW tDHW tDHR tOH tACCPWCSLClock Cycle Time Address Setup Time Address Hold Time Data Write Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (Read) Chip Select Low Pulse width (Write)PWCSHChip Select High Pulse Width (Read) Chip Select High Pulse Width (Write)tRRise TimetFFall Time* (VDD - VSS = 1.65V to 3.3V, Ta = 25°C)Min Max Unit300-ns20-ns0-ns80-ns40-ns20-ns20-ns-70ns-140ns120-ns6060-ns60-40ns-40ns8Topwin international corp.,limited3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics:Symbol Descriptiontcycle Clock Cycle TimetASAddress Setup TimetAH Address Hold TimetDW Data Write TimetDSW Write Data Setup TimetDHW Write Data Hold TimetDHR Read Data Hold TimetOH Output Disable TimetACC Access TimetPWLR Read Low TimetPWLW Write Low TimetPWHR Read High TimetPWHW Write High TimetCS Chip Select Setup TimetCSH Chip Select Hold Time to Read SignaltCSF Chip Select Hold TimetRRise TimetFFall Time* (VDD - VSS = 1.65V to 3.5V, Ta = 25°C)Min Max Unit300-ns20-ns0-ns70-ns40-ns15-ns20-ns-70ns-140ns120-ns60-ns60-ns60-ns0-ns0-ns20-ns-40ns-40ns( Read Timing )( Write Timing ) 9Topwin international corp.,limited3.3.3 Serial Interface Timing Characteristics:Symbol Descriptiontcycle Clock Cycle TimetASAddress Setup TimetAH Address Hold TimetCSS Chip Select Setup TimetCSH Chip Select Hold TimetDW Data Write TimetDSW Write Data Setup TimetDHW Write Data Hold TimetCLKL Clock Low TimetCLKH Clock High TimetRRise TimetFFall Time* (VDD - VSS = 1.65V to 3.5V, Ta = 25°C)Min Max Unit100-ns15-ns15-ns20-ns50-ns55-ns15-ns15-ns50-ns50-ns-40ns-40ns10Topwin international corp.,limited3.3.4 I2C Interface Timing Characteristics:Symbol Descriptiontcycle Clock Cycle TimetHSTART Start Condition Hold TimeData Hold Time (for “SDAOUT” Pin) tHDData Hold Time (for “SDAIN” Pin)tSD tSSTARTData Setup TimeStart Condition Setup Time (Only relevant for a repeated Start condition)tSSTOP Stop Condition Setup TimetRRise Time for Data and Clock PintFFall Time for Data and Clock PintIDLE Idle Time before a New Transmission can Start* (VDD - VSS = 1.65V to 3.5V, Ta = 25°C)Min Max Unit2.5-μs0.6-μs0-ns300100-ns0.6-μs0.6-μs300ns300ns1.3-μs11Topwin international corp.,limited4. Functional Specification4.1 Commands Refer to the Technical Manual for the SSD13094.2 Power down and Power up SequenceTo protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation.4.2.1 Power up Sequence:1. Power up VDD 2. Send Display off command 3. Initialization 4. Clear Screen 5. Power up VCC 6. Delay 100ms(When VCC is stable) 7. Send Display on command4.2.2 Power down Sequence:1. Send Display off command 2. Power down VCC 3. Delay 100ms(When VCC is reach 0 and panel is completely discharges) 4. Power down VDDVCC VDD VSS/GroundVCC VDD VSS/GroundVDD on VCC onDisplay onDisplay off VCC offVDD offNote 9:1) Since an ESD protection circuit is connected between VDD and VCC inside the driver IC, VCC becomes lower than VDD whenever VDD is ON and VCC is OFF.2) VCC should be kept float (disable) when it is OFF. 3) Power Pins (VDD, VCC) can never be pulled to ground under any circumstance. 4) VDD should not be power down before VCC power down.4.3 Reset CircuitWhen RES# input is low, the chip is initialized with the following status: 1. Display is OFF 2. 128×64 Display Mode 3. Normal segment and display data column and row address mapping (SEG0 mapped to columnaddress 00h and COM0 mapped to row address 00h) 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 0 6. Column address counter is set at 0 7. Normal scan direction of the COM outputs 8. Contrast control register is set at 7Fh 9. Normal display mode (Equivalent to A4h command)12Topwin international corp.,limited4.4 Actual Application Example Command usage and explanation of an actual example <Power up Sequence>VDD/VCC off StatePower up VDD (RES# as Low State)Power Stabilized (Delay Recommended)Set RES# as High (3μs Delay Minimum)Initialized State (Parameters as Default)Command Lock 0xFD, 0x12Set Display Off 0xAEInitial Settings ConfigurationSet Display Clock Divide Ratio/Oscillator Frequency 0xD5, 0xA0Set Multiplex Ratio 0xA8, 0x3FSet Display Offset 0xD3, 0x00Set Display Start Line 0x40Set Segment Re-Map 0xA1Set COM Output Scan Direction 0xC8Set COM Pins Hardware Configuration 0xDA, 0x12Set Current Control 0x81, 0xDFSet Pre-Charge Period 0xD9, 0x82Set VCOMH Deselect Level 0xDB, 0x34Set Entire Display On/Off 0xA4Set Normal/Inverse Display 0xA6Clear ScreenPower up VCC & Stabilized (Delay Recommended)Set Display On 0xAF(100ms Delay Recommended)Display Data SentIf the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function.<Power down Sequence>Normal OperationSet Display Off 0xAEPower down VCC (100ms Delay Recommended)Power down VDDVDD/VCC off State13Topwin international corp.,limited<Entering Sleep Mode>Normal OperationSet Display Off 0xAEPower down VCC Sleep Mode<Exiting Sleep Mode>Sleep ModePower up VCC & Stabilized (Delay Recommended)Set Display On 0xAF(100ms Delay Recommended)Normal Operation14Topwin international corp.,limited5. Reliability5.1 Contents of Reliability TestsItemConditionsHigh Temperature Operation70°C, 240 hrsLow Temperature Operation-40°C, 240 hrsHigh Temperature Storage85°C, 240 hrsLow Temperature Storage-40°C, 240 hrsHigh Temperature/Humidity Operation60°C, 90% RH, 120 hrsThermal Shock-40°C ⇔ 85°C, 24 cycles 60 mins dwell* The samples used for the above tests do not include polarizer. * No moisture condensation is observed during tests.CriteriaThe operational functions work.5.2 Failure Check StandardAfter the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 23±5°C; 55±15% RH.15Topwin international corp.,limited6. Outgoing Quality Control Specifications6.1 Environment RequiredCustomer’s test & measurement are required to be conducted under the following conditions:Temperature:23 ± 5°CHumidity:55 ± 15% RHFluorescent Lamp:30WDistance between the Panel & Lamp:≥ 50cmDistance between the Panel & Eyes of the Inspector: ≥ 30cmFinger glove (or finger cover) must be worn by the inspector.Inspection table or jig must be anti-electrostatic.6.2 Sampling Plan Level II, Normal Inspection, Single Sampling, MIL-STD-105E6.3 Criteria & Acceptable Quality LevelPartition Major MinorAQL 0.65 1.0Definition Defects in Pattern Check (Display On) Defects in Cosmetic Check (Display Off)6.3.1 Cosmetic Check (Display Off) in Non-Active AreaCheck ItemClassificationCriteriaX > 6 mm (Along with Edge) Y > 1 mm (Perpendicular to edge)XPanel General ChippingMinorY XY16Topwin international corp.,limited6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued)Check ItemClassificationCriteria Any crack is not allowable.Panel CrackMinorCopper Exposed (Even Pin or Film)Film or Trace DamageMinorNot Allowable by Naked Eye InspectionMinorTerminal Lead Prober MarkAcceptableGlue or Contamination on Pin (Couldn’t Be Removed by Alcohol)MinorInk Marking on Back Side of panel (Exclude on Film)AcceptableIgnore for Any17Topwin international corp.,limited6.3.2 Cosmetic Check (Display Off) in Active AreaIt is recommended to execute in clear room environment (class 10k) if actual in necessary.Check ItemAny Dirt & Scratch on Polarizer’s Protective FilmClassification AcceptableScratches, Fiber, Line-Shape Defect (On Polarizer)MinorDirt, Black Spot, Foreign Material, (On Polarizer)MinorCriteriaIgnore for not Affect the PolarizerW ≤ 0.1IgnoreW > 0.1, L ≤ 2n≤1L>2n=0Φ ≤ 0.1Ignore0.1 < Φ ≤ 0.25n≤10.25 < Φn=0Φ ≤ 0.5 Î Ignore if no Influence on Display0.5 < Φn=0Dent, Bubbles, White spot (Any Transparent Spot on Polarizer)MinorFingerprint, Flow Mark (On Polarizer)Minor* Protective film should not be tear off when cosmetic check. ** Definition of W & L & Φ (Unit: mm): Φ = (a + b) / 2LNot Allowableb: Minor Axis Wa: Major Axis18。