BD5354中文资料

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L934YD5V资料

SPEC NO: DSAB5495 APPROVED : J. Lu
REV NO: V.2 CHECKED :Allen Liu
DATE:MAR/15/2003 DRAWN: S.J.HOU
PAGE: 1 OF 3
元器件交易网
Selection Guide
Par t No . Dic e L en s Ty p e Iv (m c d ) V=5V Min . L-934YD-5V YELLOW(GaP) YELLOW DIFFUSED 8 Ty p . 15 V i ew i n g An g l e 2θ1/2 60 °
Note: 1. 2mm below package base.
Yello w 85 6 5 -40°C To +70°C -40°C To +85°C 260°C For 5 Seconds
Un it s mW V V
SPEC NO: DSAB5495 APPROVED : J. Lu
REV NO: V.2 CHECKED :Allen Liu
POWER CONSUMPTION.
! GENERAL ! RELIABLE ! LONG
LIFE - SOLID STATE RELIABILITY.
! AVAILABLE ON TAPE AND REEL. !5V INTERNAL RESISTOR.
Package Dimensions
Notes: 1. All dimensions are in millimeters (inches). 2. Tolerance is ±0.25(0.01") unless otherwise d. 3. Lead spacing is measured where the lead emerge package. 4. Specifications are subject to change without notice.

BCM5354中文资料

BCM5354中⽂资料OPTIMIZED 802.11G ROUTER WITH BROADRANGE?E N EF I T SThe BCM5354 achieves the lowest cost and highestperformance router system-on-chip (SoC) integration forresidential and small office, home office (SOHO) marketsTime-to-market is significantly reduced through stablekernels, board support packagesTurn-key software is code compatible with other AirForce?routers and access points (APs) enabling seamless migrationO V E R V I EWPhone: 949-450-8700Fax: 949-926-5203E-mail:info@/doc/cff2d6f2fab069dc502201a1.htmlWeb:/doc/cff2d6f2fab069dc502201a1.htmlBROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013Irvine, California 92619-70132007 by BROADCOM CORPORATION. All rights reserved.5354-PB00-R01/24/07System Block DiagramThe BCM5354 integrates a high-performance MIPS32 processor, IEEE 802.11 b/g MAC/PHY, 2.4-GHz direct conversion radio, USB 2.0 host controller, SDRAM controller, and a configurable five-port Fast Ethernet (FE) switch.The BCM5354 provides wireless LAN connectivity that supports data rates of up to 125 Mbps that is backward-compatible with standard 802.11 b/g.The BCM5354 supports a WAN connection via its configurable media interfaces. The per-port programmable four-level priority queues enable QoS (IEEE 802.1p) for guaranteed bandwidth applications, DiffServ/TOS, and L2/L3 IGMP snooping. The IEEE 802.1Q VLAN allows flexible implementation of VLAN grouping and WAN port segregation.Applications running on the BCM5354 leverage field-proven software which includes SecureEasySetup? and comprehensive wirelessnetwork security support that comprises WEP/WPA/WPA2 encryption.The BCM5354 offers the industry’s most aggressive home routerintegration and enables the lowest bill of materials (BOM) solution cost.Broadcom’s superior technology and innovation also benefitmanufacturers with faster time-to-market, and end products that are differentiated from the competition through rich features, exceptional range, and outstanding reliability.。

RTD-0524P中文资料

0505
1205
1212
0512
15.000 10.000 5.000 0.000 -5.000 -10.000
0515
1215
2405
2412
0% 20% 40% 60% Total Output current (%) 80% 100%
RTS & RTD Series
2 Watt SMD Single & Dual Output
Input Voltage (VDC) 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24
0515
2415
2412
1215
0% 20% 40% 60% Total Output current (%)
80%
100%
0% 20% 40% 60% Total Output current (%)
80%
100%
68
July-2006

元器件交易网
Deviation from Nominal (%)
15.000 10.000 5.000 0.000 -5.000 -10.000
0505
1205
15.000 10.000 5.000 0.000 -5.000 -10.000
0509
1209
2405
2409
0% 20% 40% 60% Total Output current (%)

PBSS5350SS,115;中文规格书,Datasheet资料

Fig 3. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
103
006aaa811
Zth(j-a) (K/W)
duty cycle =
PBSS5350SS_1
Product data sheet
/
Rev. 01 — 3 April 2007
© NXP B.V. 2007. All rights reserved.
4 of 14
NXP Semiconductors
PBSS5350SS
50 V, 2.7 A PNP/PNP low VCEsat (BISS) transistor
PBSS5350SS
50 V, 2.7 A PNP/PNP low VCEsat (BISS) transistor
Rev. 01 — 3 April 2007
Product data sheet
1. Product proﬁle
1.1 General description
PNP/PNP double low VCEsat Breakthrough In Small Signal (BISS) transistor in a medium power Surface-Mounted Device (SMD) plastic package.
Table 1. Product overview Type number Package
NXP PBSS5350SS SOT96-1
Name SO8
NPN/PNP complement

54ACTQ533DMQB资料

54ACTQ533Quiet Series Octal Transparent Latch with TRI-STATE ®OutputsGeneral DescriptionThe ACTQ533consists of eight latches with TRI-STATE out-puts for bus organized system applications.The flip-flops ap-pear transparent to the data when Latch Enable (LE)is HIGH.When LE is low,the data satisfying the input timing re-quirements is latched.Data appears on the bus when the Output Enable (OE)is LOW.When OE is HIGH,the bus out-put is in the high impedance state.The ACTQ533utilizes NSC Quiet Series technology to guar-antee quiet output switching and improve dynamic threshold performance.FACT Quiet Series ™features GTO ™output control and undershoot corrector in addition to a split ground bus for superior performance.Featuresn I CC and I OZ reduced by 50%n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch up immunityn Eight latches in a single packagen TRI-STATE outputs drive bus lines or buffer memory address registersn Outputs source/sink 24mAn Inverted version of the ACTQ373n 4kV minimum ESD immunityLogic SymbolsPin Names DescriptionD 0–D 7Data Inputs LE Latch Enable Input OE Output Enable Input O 0–O 7TRI-STATE Latch OutputsGTO ™is a trademark of National Semiconductor Corporation.TRI-STATE ®is a registered trademark of National Semiconductor Corporation.FACT ®is a registered trademark of Fairchild Semiconductor Corporation.FACT Quiet Series ™is a trademark of Fairchild Semiconductor Corporation.DS100241-1IEEE/IECDS100241-2August 199854ACTQ533Quiet Series Octal Transparent Latch with TRI-STATE Outputs©1998National Semiconductor Corporation Connection DiagramsFunctional DescriptionThe ACTQ533contains eight D-type latches with TRI-STATE standard outputs.When the Latch Enable (LE)input is HIGH,data on the D n inputs enters the latches.In this con-dition the latches are transparent,i.e.,a latch output will change state each time its D input changes.When LE is LOW,the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran-sition of LE.The TRI-STATE standard outputs are controlled by the Output Enable (OE)input.When OE is LOW,the stan-dard outputs are in the 2-state mode.When OE is HIGH,the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.Truth TableInputsOutputs LE OE D n O n X H X Z H L L H H L H L LLXO 0H =HIGH Voltage Level L =LOW Voltage Level Z =High Impedance X =ImmaterialO 0=Previous O 0before HIGH to Low transition of Latch EnableLogic DiagramPin Assignment for DIP and FlatpakDS100241-3Pin Assignmentfor LCCDS100241-4DS100241-5Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)−0.5V to+7.0V DC Input Diode Current(I IK)V I=−0.5V−20mA V I=V CC+0.5V+20mA DC Input Voltage(V I)−0.5V to V CC+0.5V DC Output Diode Current(I OK)V O=−0.5V−20mA V O=V CC+0.5V+20mA DC Output Voltage(V O)−0.5V to V CC+0.5V DC Output Sourceor Sink Current(I O)±50mA DC V CC or Ground Currentper Output Pin(I CC or I GND)±50mA Storage Temperature(T STG)−65˚C to+150˚C DC Latchup Sourceor Sink Current±300mA Junction Temperature(T J)CDIP175˚C Recommended Operating ConditionsSupply Voltage(V CC)’ACTQ 4.5V to5.5V Input Voltage(V I)0V to V CC Output Voltage(V O)0V to V CC Operating Temperature(T A)54ACTQ−55˚C to+125˚C Minimum Input Edge Rate∆V/∆t’ACTQ DevicesV IN from0.8V to2.0VV CC@4.5V,5.5V125mV/ns Note1:Absolute maximum ratings are those values beyond which damage to the device may occur.The databook specifications should be met,without exception,to ensure that the system design is reliable over its power supply, temperature,and output/input loading variables.National does not recom-mend operation of FACT®circuits outside databook specifications.Note2:All commercial packaging is not recommended for applications re-quiring greater than2000temperature cycles from−40˚C to+125˚C.DC Characteristics for’ACTQ Family Devices54ACTQSymbol Parameter V CC T A=Units Conditions(V)−55˚C to+125˚CGuaranteedLimitsV IH Minimum High Level 4.5 2.0V V OUT=0.1V Input Voltage 5.5 2.0or V CC−0.1VV IL Maximum Low Level 4.50.8V V OUT=0.1V Input Voltage 5.50.8or V CC−0.1VV OH Minimum High Level 4.5 4.4V I OUT=−50µA Output Voltage 5.5 5.4(Note3)V IN=V IL or V IH4.5 3.70V I OH=−24mA5.5 4.70I OH=−24mAV OL Maximum Low Level 4.50.1V I OUT=50µA Output Voltage 5.50.1(Note3)V IN=V IL or V IH4.50.50V I OL=24mA5.50.50I OL=24mAI IN Maximum Input LeakageCurrent5.5±1.0µA V I=V CC,GNDI OZ Maximum TRI-STATE 5.5±5.0µA V I=V IL,V IHLeakage Current V O=V CC,GNDI CCT Maximum 5.5 1.6mA V I=V CC−2.1VI CC/InputDC Characteristics for’ACTQ Family Devices(Continued)54ACTQSymbol Parameter V CC T A=Units Conditions(V)−55˚C to+125˚CGuaranteedLimitsI OLD Minimum Dynamic 5.550mA V OLD=1.65V MaxI OHD Output Current5.5−50mA V OHD=3.85V Min(Note4)I CC Maximum Quiescent 5.580.0µA V IN=V CCSupply Current or GND(Note5) V OLP Quiet Output 5.0 1.7V(Notes6,7) Maximum Dynamic V OLV OLV Quiet Output 5.0−1.2V(Notes6,7) Minimum Dynamic V OLNote3:All outputs loaded;thresholds on input associated with output under test.Note4:Maximum test duration2.0ms,one output loaded at a time.Note5:I CC for54ACTQ@25˚C is identical to74ACQ@25˚C.Note6:Plastic DIP package.Note7:Max number of outputs defined as(n).Data inputs are driven0V to3V.One output@GND.AC Electrical Characteristics54ACTQV CC T A=−55˚C Fig.Symbol Parameter(V)to+125˚C Units No.(Note8)C L=50pFMin Maxt PHL,t PLH Propagation Delay 5.0 1.59.0nsD n to O nt PHL,t PLH Propagation Delay 5.0 1.510.5nsLE to O nt PZL,t PZH Output Enable Time 5.0 1.510.5nst PHZ,t PLZ Output Disable Time 5.0 1.510.5nsNote8:Voltage Range5.0is5.0V±0.5V.Note9:Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The speci-fication applies to any outputs switching in the same direction,either HIGH to LOW(t OSHL)or LOW to HIGH(t OSLH).Parameter guaranteed by design.AC Operating Requirements54ACTQV CC T A=−55˚C Fig.Symbol Parameter(V)to+125˚C Units No.(Note10)C L=50pFGuaranteedMinimumt S Setup Time,HIGH or LOW 5.0 3.0nsD n to LEt H Hold Time,HIGH or LOW 5.0 1.5nsD n to LEt W LE Pulse Width,HIGH 5.0 5.0nsNote10:Voltage Range5.0is5.0V±0.5V.4CapacitanceSymbol Parameter Typ Units ConditionsC IN Input Capacitance 4.5pF V CC=OPENC PD Power Dissipation40pF V CC=5.0VCapacitance6Physical Dimensions inches(millimeters)unless otherwise noted20-Terminal Ceramic Leadless Chip Carrier(L)NS Package Number E20A20-Lead Ceramic Dual-In-Line Package(D)NS Package Number J20APhysical Dimensions inches(millimeters)unless otherwise noted(Continued)LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or(b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,canbe reasonably expected to result in a significant injuryto the user.2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system,or to affect its safety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5620-6175Fax:81-3-5620-617920-Lead Ceramic Flatpak(F)NS Package Number W20A54ACTQ533QuietSeriesOctalTransparentLatchwithTRI-STATEOutputsNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

BD5332中文资料

BD52XXG/FVE series BD53XXG/FVE seriesHigh-accuracy detection voltage Low current consumptionDescriptionFeaturesApplications VOL T AGE DETECTOR IC with adjustable delay timeBD52XXG/FVE, BD53XXG/FVE are series of high-accuracy detection voltage and low current consumption VOLTAGE DETECTOR ICs adopting CMOS process.New lineup of 152 types with delay time circuit have developed in addition to well-reputed 152 types of VOLTAGE DETECTOR ICs.Any delay time can be established by using small capacitor due to high-resistance process technology.Total 152 types of VOLTAGE DETECTOR ICs includingBD52XXG/FVE series (Nch open drain output) and BD53XXG/FVE series (CMOS output), each of which has 38 kinds in every 0.1V step (2.3~6.0V) have developed.1) Detection voltage: 0.1V step line-up 2.3~6.0V (Typ.)2) High-accuracy detection voltage:±1.5% (Max.)3) Ultra low current consumption: 0.95µA (Typ.)4) Nch open drain output (BD52XXG/FVE series), CMOS output (BD53XXG/FVE series)5) Small VSOF5(EMP5), SSOP5(SMP5C2) packageEvery kind of appliances with microcontroller and logic circuit BD52XXG/FVEBD53XXG/FVEPin No.SSOP5(SMP5C2)VSOF5(EMP5)Vout VoutV DD V DDGND GNDNC.CT SUBCT12345 Application CircuitAbsolute Maximum Ratings (Ta=25˚C)Characteristic diagram and Measurement circuitElectrical characteristics (Unless otherwise noted; Ta=-25~85˚C)1 ˚C ˚C *2 Derating: 2.1mW/˚C for operation above Ta=25˚C .(Mounted on a 70.0mmX70.0mmX16mm glass epoxy PCB.)*2 T PLH : V DD =(V DET typ.–0.5V) (V DET typ.+0.5V). Note) Please refer to the detection voltage of Line-up table.Output delay time "L H"Output delay time "H L"ΩV DET ΩCT Capacitance [µF]d e l a y t i m e [s ]CT Capacitance [µF]d e l a y t i m e [µs ]Part number and Marking of samplesBD5260PW PV PU PT PS PR PQ PP PN PM 6.0V 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V 5.2V 5.1V PB P A MV MU MT MS MR MQ MP MN 4.1V 4.0V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V 3.3V 3.2V RW RVRU RT RS RR RQ RN RM RP 6.0V 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V BD5241BD5259BD5258BD5257BD5256BD5255BD5254BD5253BD5252BD5251BD5240BD5239BD5238BD5237BD5236BD5235BD5234BD5233BD5232BD5360BD5359BD5358BD5357BD5356BD5355BD5354BD53535.2V 5.1V BD5352BD5351Marking VoltagePart No.Marking VoltagePart No.Marking VoltagePart No.Marking VoltagePart No.BD5341RB RA QV QU QT QS QR QQ QP QN 4.1V 4.0V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V 3.3V 3.2V BD5340BD5339BD5338BD5337BD5336BD5335BD5334BD5333BD5332BD5250PL PK PJ PH PG PF PE PD PC5.0V 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V 4.2VMM ML MK MJ MH MG MF ME MD3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3VRL RK RJRH RG RF RE RCRD 5.0V 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V BD5231BD5249BD5248BD5247BD5246BD5245BD5244BD5243BD5242BD5230BD5229BD5228BD5227BD5226BD5225BD5224BD5223BD5350BD5349BD5348BD5347BD5346BD5345BD5344BD53434.2VBD5342BD5331QM QL QK QJ QH QG QF QE QD3.1V3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3VBD5330BD5329BD5328BD5327BD5326BD5325BD5324BD5323Circuit current"L" output current"H" output currentI/O characteristicBD52XXG/BD53XXG : SSOP5 (SMP5C2)BD52XXFVE/BD53XXFVE : VSOF5 (EMP5)V DS [V]I O H[m A ]Timing waveformDetection voltageV D E T VVΩV ΩV V DD [V]I D D [µA ][m A ]V DS [V]I O L V DD [V]V O U T [V ]Ta [˚C][V ]V DDV DDV OUTV 0V V OHV OLV DET +∆V DETLine-up。

BD543资料

BD543, BD543A, BD543B, BD543C NPN SILICON POWER TRANSISTORS2JUNE 1973 - REVISED MARCH 1997P R O D U C T I N F O R M A T I O NNOTES:4.These parameters must be measured using pulse techniques, t p = 300 µs, duty cycle ≤ 2%.5.These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts.†Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.electrical characteristics at 25°C case temperaturePARAMETER TEST CONDITIONSMIN TYPMAXUNITV (BR)CEOCollector-emitter breakdown voltageI C = 30 mA (see Note 4)I B = 0BD543BD543A BD543B BD543C 406080100VI CESCollector-emitter cut-off current V CE = 40 VV CE = 60 V V CE = 80 V V CE =100 VV BE =0V BE =0V BE =0V BE =0BD543BD543A BD543B BD543C 0.40.40.40.4mA I CEO Collector cut-off current V CE = 30 V V CE = 60 V I B =0I B =0BD543/543A BD543B/543C0.70.7mA I EBOEmitter cut-off current V EB = 5 V I C =01mA h FEForward current transfer ratio V CE = 4 V V CE = 4 V V CE = 4 V I C = 1 A I C = 3A I C = 5A (see Notes 4 and 5)604015V CE(sat)Collector-emitter saturation voltage I B = 0.3 A I B = 1 A I B = 1.6 A I C = 3A I C = 5A I C = 8A (see Notes 4 and 5)0.50.51VV BE Base-emitter voltageV CE = 4 V I C = 5 A (see Notes 4 and 5) 1.4V h feSmall signal forward current transfer ratio V CE = 10 V I C =0.5A f = 1 kHz 20|h fe |Small signal forward current transfer ratioV CE = 10 VI C =0.5Af = 1 MHz3thermal characteristicsPARAMETERMINTYPMAX UNIT R θJC Junction to case thermal resistance 1.79°C/W R θJAJunction to free air thermal resistance62.5°C/Wresistive-load-switching characteristics at 25°C case temperaturePARAMETERTEST CONDITIONS †MIN TYP MAX UNIT t on T urn-on time I C = 6 A V BE(off) = -4 VI B(on) = 0.6 A R L = 5 ΩI B(off) = -0.6 A t p = 20 µs, dc ≤ 2%0.6µs t offT urn-off time1µs3BD543, BD543A, BD543B, BD543C NPN SILICON POWER TRANSISTORS4JUNE 1973 - REVISED MARCH 1997P R O D U C T I N F O R M A T I O NMAXIMUM SAFE OPERATING REGIONSTHERMAL INFORMATION5BD543, BD543A, BD543B, BD543C NPN SILICON POWER TRANSISTORS6JUNE 1973 - REVISED MARCH 1997P R O D U C T I N F O R M A T I O NIMPORTANT NOTICEPower Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current.PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except as mandated by government requirements.PI accepts no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination,machine, or process in which such semiconductor products or services might be or are used.PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR USE IN LIFE-SUPPORT APPLICA TIONS, DEVICES OR SYSTEMS.Copyright © 1997, Power Innovations Limited。

BD5334中文资料

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BD52XXG/FVE series BD53XXG/FVE series
High-accuracy detection voltage Low current consumption
Description
Features
Applications VOL T AGE DETECTOR IC with adjustable delay time
BD52XXG/FVE, BD53XXG/FVE are series of high-accuracy detection voltage and low current consumption VOLTAGE DETECTOR ICs adopting CMOS process.
New lineup of 152 types with delay time circuit have developed in addition to well-reputed 152 types of VOLTAGE DETECTOR ICs.Any delay time can be established by using small capacitor due to high-resistance process technology.
Total 152 types of VOLTAGE DETECTOR ICs including
BD52XXG/FVE series (Nch open drain output) and BD53XXG/FVE series (CMOS output), each of which has 38 kinds in every 0.1V step (2.3~6.0V) have developed.1) Detection voltage: 0.1V step line-up 2.3~6.0V (Typ.)2) High-accuracy detection voltage:±1.5% (Max.)3) Ultra low current consumption: 0.95µA (Typ.)4) Nch open drain output (BD52XXG/FVE series), CMOS output (BD53XXG/FVE series)
5) Small VSOF5(EMP5), SSOP5(SMP5C2) package
Every kind of appliances with microcontroller and logic circuit BD52XXG/FVE
BD53XXG/FVE
Pin No.SSOP5(SMP5C2)VSOF5(EMP5)
Vout Vout
V DD V DD
GND GND
NC.CT SUB
CT
12345 Application Circuit
Absolute Maximum Ratings (Ta=25˚C)
Characteristic diagram and Measurement circuit
Electrical characteristics (Unless otherwise noted; Ta=-25~85˚C)
1 ˚C ˚C *
2 Derating: 2.1mW/˚C for operation above Ta=25˚C .(Mounted on a 70.0mmX70.0mmX16mm glass epoxy PCB.)
*2 T PLH : V DD =(V DET typ.–0.5V) (V DET typ.+0.5V). Note) Please refer to the detection voltage of Line-up table.
Output delay time "L H"
Output delay time "H L"
Ω
V DET Ω
CT Capacitance [µF]
d e l a y t i m e [s ]
CT Capacitance [µF]
d e l a y t i m e [µs ]
Part number and Marking of samples
BD5260PW PV PU PT PS PR PQ PP PN PM 6.0V 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V 5.2V 5.1V PB P A MV MU MT MS MR MQ MP MN 4.1V 4.0V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V 3.3V 3.2V RW RV
RU RT RS RR RQ RN RM RP 6.0V 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V BD5241BD5259BD5258BD5257BD5256BD5255BD5254BD5253BD5252BD5251BD5240BD5239BD5238BD5237BD5236BD5235BD5234BD5233BD5232BD5360BD5359BD5358BD5357BD5356BD5355BD5354BD53535.2V 5.1V BD5352BD5351Marking Voltage
Part No.
Marking Voltage
Part No.
Marking Voltage
Part No.
Marking Voltage
Part No.
BD5341RB RA QV QU QT QS QR QQ QP QN 4.1V 4.0V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V 3.3V 3.2V BD5340BD5339BD5338BD5337BD5336BD5335BD5334BD5333
BD5332BD5250PL PK PJ PH PG PF PE PD PC
5.0V 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V 4.2V
MM ML MK MJ MH MG MF ME MD
3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V
RL RK RJ
RH RG RF RE RC
RD 5.0V 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V BD5231BD5249BD5248BD5247BD5246BD5245BD5244BD5243BD5242
BD5230BD5229BD5228BD5227BD5226BD5225BD5224BD5223
BD5350BD5349BD5348BD5347BD5346BD5345BD5344BD53434.2V
BD5342
BD5331QM QL QK QJ QH QG QF QE QD
3.1V
3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V
BD5330BD5329BD5328BD5327BD5326BD5325BD5324BD5323
Circuit current
"L" output current
"H" output current
I/O characteristic
BD52XXG/BD53XXG : SSOP5 (SMP5C2)
BD52XXFVE/BD53XXFVE : VSOF5 (EMP5)
V DS [V]
I O H
[m A ]
Timing waveform
Detection voltage
V D E T V
V
Ω
V Ω
V V DD [V]
I D D [µA ]
[m A ]
V DS [V]
I O L V DD [V]
V O U T [V ]
Ta [˚C]
[V ]
V DD
V DD
V OUT
V 0V V OH
V OL
V DET +∆V DET
Line-up。