CSD87353Q5D

V SWV SWV SWB GT GRT GV INV IN70758085909510024681012Output Current (A)Efficiency(%)PowerLoss(W)CSD87353Q5D SLPS285C–AUGUST2011–REVISED OCTOBER2011Synchronous Buck NexFET™Power BlockFEATURES DESCRIPTIONThe CSD87353Q5D NexFET™power block is an •V IN up to27Voptimized design for synchronous buck applications •Half-Bridge Power Block offering high current,high efficiency,and high•95%system Efficiency at25A frequency capability in a small5-mm×6-mm outline.Optimized for5V gate drive applications,this product •Up To40A Operationoffers a flexible solution capable of offering a high •High Frequency Operation(Up To1.5MHz)density power supply when paired with any5V gate •High Density–SON5-mm×6-mm Footprint drive from an external controller/driver.•Optimized for5V Gate Drive•Low Switching LossesTop View•Ultra Low Inductance Package•RoHS Compliant•Halogen Free•Pb-Free Terminal PlatingAPPLICATIONS•Synchronous Buck Converters–High Frequency ApplicationsORDERING INFORMATION –High Current,High Duty Cycle ApplicationsDevice Package Media Qty Ship •Multiphase Synchronous Buck ConvertersSON5-mm×6-mm13-Inch Tape andCSD87353Q5D2500Plastic Package Reel Reel •POL DC-DC Converters•IMVP,VRM,and VRD ApplicationsTYPICAL POWER BLOCK EFFICIENCYTYPICAL CIRCUIT and POWER LOSSPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NexFET is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©2011,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.CSD87353Q5DSLPS285C–AUGUST2011–REVISED These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.ABSOLUTE MAXIMUM RATINGST A=25°C(unless otherwise noted)(1)Parameter Conditions VALUE UNITV IN to P GND30VV SW to P GND30V Voltage Range V SW to P GND(10ns)32VT G to T GR-8to10VB G to P GND-8to10V Pulsed Current Rating,I DM120A Power Dissipation,P D12WSync FET,I D=105A,L=0.1mH551Avalanche Energy E AS mJControl FET,I D=87A,L=0.1mH378Operating Junction and Storage Temperature Range,T J,T STG-55to150°C(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated is not implied.Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.RECOMMENDED OPERATING CONDITIONST A=25°(unless otherwise noted)Parameter Conditions MIN MAX UNIT Gate Drive Voltage,V GS 4.58VInput Supply Voltage,V IN27V Switching Frequency,f SW C BST=0.1μF(min)1500kHz Operating Current40A Operating Temperature,T J125°C POWER BLOCK PERFORMANCET A=25°(unless otherwise noted)Parameter Conditions MIN TYP MAX UNITV IN=12V,V GS=5V,V OUT=3.3V,Power Loss,P LOSS(1)I OUT=25A,f SW=500kHz, 3.3WL OUT=0.68µH,T J=25ºCV IN Quiescent Current,I QVIN T G to T GR=0V,B G to P GND=0V10µA (1)Measurement made with six10µF(TDK C3216X5R1C106KT or equivalent)ceramic capacitors placed across V IN to P GND pins andusing a high current5V driver IC.THERMAL INFORMATIONT A=25°C(unless otherwise stated)THERMAL METRIC MIN TYP MAX UNIT Junction to ambient thermal resistance(Min Cu)(1)(2)102RθJAJunction to ambient thermal resistance(Max Cu)(1)(2)50°C/W Junction to case thermal resistance(Top of package)(2)20RθJCJunction to case thermal resistance(P GND Pin)(2)2(1)Device mounted on FR4material with1-inch2(6.45-cm2)Cu.(2)RθJC is determined with the device mounted on a1-inch2(6.45-cm2),2oz.(0.071-mm thick)Cu pad on a1.5-inch×1.5-inch(3.81-cm×3.81-cm),0.06-inch(1.52-mm)thick FR4board.RθJC is specified by design while RθJA is determined by the user’s boarddesign.2Submit Documentation Feedback Copyright©2011,Texas Instruments IncorporatedM0189-01M0190-01CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011ELECTRICAL CHARACTERISTICST A =25°C (unless otherwise stated)Q1Control FET Q2Sync FET PARAMETERTEST CONDITIONSMINTYPMAXMINTYPMAXUNITStatic Characteristics BV DSS Drain to Source Voltage V GS =0V,I DS =250μA 3030V Drain to Source Leakage I DSS V GS =0V,V DS =20V 11μA CurrentGate to Source Leakage I GSS V DS =0V,V GS =+10/-8V 100100nA CurrentGate to Source Threshold V GS(th)V DS =V GS ,I DS =250μA 1.1 2.10.75 1.15VVoltage V IN =12V,V GS =5V,Effective AC V OUT =3.3V,I OUT =20A,Z DS(on)(1) 2.80.9m ΩOn-Impedance f SW =500kHz,L OUT =0.68µH g fs Transconductance V DS =15V,I DS =20A135160S Dynamic CharacteristicsC ISS Input Capacitance 2660319029103490pF C OSS Output Capacitance V GS =0V,V DS =15V,1100132013201580pF f =1MHzReverse Transfer C RSS 43545168pF CapacitanceR G Series Gate Resistance 0.920.7 1.5ΩQ g Gate Charge Total (4.5V)16192024nC Gate Charge -Gate to Q gd 3 3.6nC DrainV DS =15V,I DS =20AGate Charge -Gate to Q gs 4.9 4.2nC SourceQ g(th)Gate Charge at Vth 2.8 2.4nC Q OSS Output Charge V DS =17V,V GS =0V 2226nC t d(on)Turn On Delay Time 108.5ns t r Rise Time1610ns V DS =15V,V GS =4.5V,I DS =20A,R G =2Ωt d(off)Turn Off Delay Time 2023ns t f Fall Time4 4.6ns Diode CharacteristicsV SD Diode Forward Voltage I DS =20A,V GS =0V 0.810.81V Q rr Reverse Recovery Charge 2933nC V dd =17V,I F =20A,di/dt =300A/μs t rr Reverse Recovery Time2527ns(1)Equivalent System Performance based on application testing.See page 9for details.Max R θJA =50°C/W Max R θJA =102°C/W when mounted on when mounted on 1inch 2(6.45cm 2)of minimum pad area of 2-oz.(0.071-mm thick)2-oz.(0.071-mm thick)Cu.Cu.Copyright ©2011,Texas Instruments IncorporatedSubmit Documentation Feedback 3123456789100510152025303540Output Current (A)P o w e r L o s s (W )0.40.50.60.70.80.911.11.21.31.4−50−25255075100125150Junction Temperature (ºC)P o w e r L o s s , N o r m a l i z e d5101520253035404550Ambient Temperature (ºC)O u t p u t C u r r e n t (A )Ambient Temperature (ºC)O u t p u t C u r r e n t (A )05101520253035404550020406080100120140Board Temperature (ºC)O u t p u t C u r r e n t (A )CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011TYPICAL POWER BLOCK DEVICE CHARACTERISTICSTest Conditions:V IN =12V,V GS =5V,f SW =500kHz,V OUT =3.3V,L OUT =0.68µH,I OUT =40A,T J =125°C,unless statedotherwise.Figure 1.Power Loss vs Output CurrentFigure 2.Normalized Power Loss vs TemperatureFigure 3.Safe Operating Area –PCB Vertical Mount (1)Figure 4.Safe Operating Area –PCB Horizontal Mount (1)Figure 5.Typical Safe Operating Area (1)(1)The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0”(W)×3.5”(L)x 0.062”(H)and 6copper layers of 1oz.copper thickness.See Application Section for detailed explanation.4Submit Documentation Feedback Copyright ©2011,Texas Instruments Incorporated10030050070090011001300150017000.60.70.80.911.11.21.31.41.51.6−3.4−2.6−1.7−0.90.00.91.72.63.44.35.1Switching Frequency (kHz)P o w e r L o s s , N o r m a l i z e dS O A T e m p e r a t u r e A d j (ºC )3579111315171921230.60.70.80.911.11.21.31.41.51.6−3.5−2.6−1.8−0.90.00.91.82.63.54.45.3Input Voltage (V)P o w e r L o s s , N o r m a l i z e dS O A T e m p e r a t u r e A d j (ºC )0.511.522.533.544.555.560.60.70.80.911.11.21.31.41.51.6−3.2−2.4−1.6−0.800.81.62.43.24.14.9Output Voltage (V)P o w e r L o s s , N o r m a l i z e dS O A T e m p e r a t u r e A d j (ºC )0.20.40.60.81 1.2 1.4 1.61.820.60.70.80.911.11.21.31.41.51.6−3.5−2.7−1.8−0.900.91.82.73.54.45.3Output Inductance (µH)P o w e r L o s s , N o r m a l i z e dS O A T e m p e r a t u r e A d j (ºC )CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)Test Conditions:V IN =12V,V GS =5V,f SW =500kHz,V OUT =3.3V,L OUT =0.68µH,I OUT =40A,T J =125°C,unless stated otherwise.Figure 6.Normalized Power Loss vs Switching FrequencyFigure 7.Normalized Power Loss vs Input VoltageFigure 8.Normalized Power Loss vs.Output Voltage Figure 9.Normalized Power Loss vs.Output InductanceCopyright ©2011,Texas Instruments Incorporated Submit Documentation Feedback501020304050607080V DS - Drain-to-Source Voltage - V I D S - D r a i n -t o -S o u r c e C u r r e n t - A010********607080V DS - Drain-to-Source Voltage - VI D S - D r a i n -t o -S o u r c e C u r r e n t - A0.0010.010.1110100I D S - D r a i n -t o -S o u r c e C u r r e n t - A0.0010.010.1110100I D S - D r a i n -t o -S o u r c e C u r r e n t - A012345678051015202530Q g - Gate Charge - nC (nC)V G S - G a t e -t o -S o u r c e V o l t a g e (V )01234567805101520253035Q g - Gate Charge - nC (nC)V G S - G a t e -t o -S o u r c e V o l t a g e (V )CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011TYPICAL POWER BLOCK MOSFET CHARACTERISTICST A =25°C,unless stated otherwise.Figure 10.Control MOSFET SaturationFigure 11.Sync MOSFET SaturationFigure 12.Control MOSFET TransferFigure 13.Sync MOSFET Transfer Figure 14.Control MOSFET Gate Charge Figure 15.Sync MOSFET Gate Charge6Submit Documentation Feedback Copyright ©2011,Texas Instruments Incorporated0.0010.010.111051015202530V DS - Drain-to-Source Voltage - V C − C a p a c i t a n c e − n F0.0010.010.111051015202530V DS - Drain-to-Source Voltage - VC − C a p a c i t a n c e − n F00.20.40.60.811.21.41.6T C - Case Temperature - ºC V G S (t h ) - T h r e s h o l d V o l t a g e - V00.20.40.60.811.21.41.6T C - Case Temperature - ºCV G S (t h ) - T h r e s h o l d V o l t a g e - V012345678V GS - Gate-to- Source Voltage - V R D S (o n ) - O n -S t a t e R e s i s t a n c e - m Ω012345678V GS - Gate-to- Source Voltage - VR D S (o n ) - O n -S t a t e R e s i s t a n c e - m ΩCSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)T A =25°C,unless stated otherwise.Figure 16.Control MOSFET CapacitanceFigure 17.Sync MOSFET CapacitanceFigure 18.Control MOSFET V GS(th)Figure 19.Sync MOSFET V GS(th)Figure 20.Control MOSFET R DS(on)vs V GS Figure 21.Sync MOSFET R DS(on)vs V GSCopyright ©2011,Texas Instruments Incorporated Submit Documentation Feedback 700.20.40.60.811.21.41.61.8−75−252575125175T C - Case Temperature - ºC N o r m a l i z e d O n -S t a t e R e s i s t a n c e00.20.40.60.811.21.41.61.8−75−252575125175T C - Case Temperature - ºCN o r m a l i z e d O n -S t a t e R e s i s t a n c e0.00010.0010.010.1110100V SD − Source-to-Drain Voltage - V I S D − S o u r c e -t o -D r a i n C u r r e n t - A0.00010.0010.010.1110100V SD − Source-to-Drain Voltage - VI S D − S o u r c e -t o -D r a i n C u r r e n t - At (AV ) - Time in Avalanche - ms1101001000t (AV ) - Time in Avalanche - msI (A V ) - P e a k A v a l a n c h e C u r r e n t - A CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)T A =25°C,unless stated otherwise.Figure 22.Control MOSFET Normalized R DS(on)Figure 23.Sync MOSFET Normalized R DS(on)Figure 24.Control MOSFET Body DiodeFigure 25.Sync MOSFET Body DiodeFigure 26.Control MOSFET Unclamped InductiveFigure 27.Sync MOSFET Unclamped Inductive SwitchingSwitching8Submit Documentation Feedback Copyright ©2011,Texas Instruments IncorporatedCSD87353Q5D SLPS285C–AUGUST2011–REVISED OCTOBER2011APPLICATION INFORMATIONEquivalent System PerformanceMany of today’s high performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency.This has created a major emphasis on improving the conversion efficiency of today’s Synchronous Buck Topology.In particular,there has been an emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this Application(see Figure28).As such,optimization of the power semiconductors in these applications,needs to go beyond simply reducing R DS(ON).Figure28.The CSD87353Q5D is part of TI’s Power Block product family which is a highly optimized product for use in a synchronous buck topology requiring high current,high efficiency,and high frequency.It incorporates TI’s latest generation silicon which has been optimized for switching performance,as well as minimizing losses associated with Q GD,Q GS,and Q RR.Furthermore,TI’s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the Control FET and Sync FET connections(see Figure29).A key challenge solved by TI’s patented packaging technology is the system level impact of Common Source Inductance(CSI).CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency.As a result,the effects of CSI need to be considered during the MOSFET selection process.In addition,standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI.Further details behind the effects of CSI and modification of switching loss equations are outlined in TI’s Application Note SLPA009.Figure29.Copyright©2011,Texas Instruments Incorporated Submit Documentation Feedback986889092949698051015202530354045Output Current (A)E f f i c i e n c y (%)0123456789101112051015202530354045Output Current (A)P o w e r L o s s (W )CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011The combination of TI ’s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard MOSFET chipsets of similar R DS(ON)and MOSFET chipsets with lower R DS(ON).Figure 30and Figure 31compare the efficiency and power loss performance of the CSD87353Q5D versus industry standard MOSFET chipsets commonly used in this type of application.This comparison purely focuses on the efficiency and generated loss of the power semiconductors only.The performance of CSD87353Q5D clearly highlights the importance of considering the Effective AC On-Impedance (Z DS(ON))during the MOSFET selection process of any new design.Simply normalizing to traditional MOSFET R DS(ON)specifications is not an indicator of the actual in-circuit performance when using TI ’s Power Block technology.Figure 30.Figure 31.The chart below compares the traditional DC measured R DS(ON)of CSD87353Q5D versus its Z DS(ON).This comparison takes into account the improved efficiency associated with TI ’s patented packaging technology.As such,when comparing TI ’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a standard package,the in-circuit switching performance of the solution must be considered.In this example,individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC measured R DS(ON)values that are equivalent to CSD87353Q5D ’s Z DS(ON)value in order to have the same efficiency performance at full load.Mid to light-load efficiency will still be lower with individually packaged discrete MOSFETs or dual MOSFETs in a standard package.Comparison of R DS(ON)vs.Z DS(ON)HSLSParameterTyp Max Typ Max Effective AC On-Impedance Z DS(ON)(V GS =5V)2.8-0.9-DC Measured R DS(ON)(V GS =4.5V)2.83.42.12.610Submit Documentation Feedback Copyright ©2011,Texas Instruments IncorporatedCSD87353Q5D SLPS285C–AUGUST2011–REVISED OCTOBER2011The CSD87353Q5D NexFET™power block is an optimized design for synchronous buck applications using5V gate drive.The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency.As a result,a new rating method is needed which is tailored towards a more systems centric environment.System level performance curves such as Power Loss,Safe Operating Area,and normalized graphs allow engineers to predict the product performance in the actual application.Power Loss CurvesMOSFET centric parameters such as R DS(ON)and Q gd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers,Texas Instruments has provided measured power loss performance curves.Figure1plots the power loss of the CSD87353Q5D as a function of load current.This curve is measured by configuring and running the CSD87353Q5D as it would be in the final application(see Figure32).The measured power loss is the CSD87353Q5D loss and consists of both input conversion loss and gate drive loss.Equation1is used to generate the power loss curve.(V IN x I IN)+(V DD x I DD)–(V SW_AVG x I OUT)=Power Loss(1) The power loss curve in Figure1is measured at the maximum recommended junction temperatures of125°C under isothermal test conditions.Safe Operating Curves(SOA)The SOA curves in the CSD87353Q5D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss.Figure3to Figure5outline the temperature and airflow conditions required for a given load current.The area under the curve dictates the safe operating area.All the curves are based on measurements made on a PCB design with dimensions of4”(W)x 3.5”(L)x0.062”(T)and6copper layers of1oz.copper thicknessNormalized CurvesThe normalized curves in the CSD87353Q5D data sheet provides guidance on the Power Loss and SOA adjustments based on their application specific needs.These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions.The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve.The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve.Figure32.Typical ApplicationCSD87353Q5DSLPS285C–AUGUST2011–REVISED Calculating Power Loss and SOAThe user can estimate product loss and SOA boundaries by arithmetic means(see Design Example).Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions,the following procedure will outline the steps the user should take to predict product performance for any set of system conditions.Design ExampleOperating Conditions:•Output Current=25A•Input Voltage=5V•Output Voltage=1V•Switching Frequency=800kHz•Inductor=0.2µHCalculating Power Loss•Power Loss at25A=4.2W(Figure1)•Normalized Power Loss for input voltage≈0.94(Figure7)•Normalized Power Loss for output voltage≈0.9(Figure8)•Normalized Power Loss for switching frequency≈1.2(Figure6)•Normalized Power Loss for output inductor≈1.05(Figure9)•Final calculated Power Loss=4.2W x0.94x0.9x1.2x1.05≈4.48WCalculating SOA Adjustments•SOA adjustment for input voltage≈-0.7ºC(Figure7)•SOA adjustment for output voltage≈-0.8ºC(Figure8)•SOA adjustment for switching frequency≈1.2ºC(Figure6)•SOA adjustment for output inductor≈0.45ºC(Figure9)•Final calculated SOA adjustment=(-0.7)+(-0.8)+1.2+0.45≈0.15ºCIn the design example above,the estimated power loss of the CSD87353Q5D would increase to4.48W.In addition,the maximum allowable board and/or ambient temperature would have to decrease by0.15ºC. Figure33graphically shows how the SOA curve would be adjusted accordingly.1.Start by drawing a horizontal line from the application current to the SOA curve.2.Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.3.Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.In the design example,the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of0.15°C.In the event the adjustment value is a negative number,subtracting the negative number would yield an increase in allowable board/ambient temperature.Figure33.Power Block SOACSD87353Q5D SLPS285C–AUGUST2011–REVISED OCTOBER2011RECOMMENDED PCB DESIGN OVERVIEWThere are two key system-level parameters that can be addressed with a proper PCB design:Electrical and Thermal performance.Properly optimizing the PCB layout will yield maximum performance in both areas.A brief description on how to address each parameter is provided.Electrical PerformanceThe Power Block has the ability to switch voltages at rates greater than10kV/µs.Special care must be then taken with the PCB layout design and placement of the input capacitors,Driver IC,and output inductor.•The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the highest priority during the component placement routine.It is critical to minimize these node lengths.As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins(see Figure34).The example in Figure34uses6x10µF ceramic capacitors(TDK Part#C3216X5R1C106KT or equivalent).Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers.In terms of priority of placement next to the Power Block,C5,C7,C19,and C8 should follow in order.•The Driver IC should be placed relatively close to the Power Block Gate pins.T G and B G should connect to the outputs of the Driver IC.The T GR pin serves as the return path of the high-side gate drive circuitry and should be connected to the Phase pin of the IC(sometimes called LX,LL,SW,PH,etc.).The bootstrap capacitor for the Driver IC will also connect to this pin.•The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.•The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.In the event the switch node waveform exhibits ringing that reaches undesirable levels,the use of a Boost Resistor or RC snubber can be an effective way to reduce the peak ring level.The recommended Boost Resistor value will range between1Ωto4.7Ωdepending on the output characteristics of Driver IC used in conjunction with the Power Block.The RC snubber values can range from0.5Ωto2.2Ωfor the R and330pF to2200pF for the C.Refer to TI App Note SLUP100for more details onhow to properly tune the RC snubber values.The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure34(1)(1)Keong W.Kam,David Pommerenke,“EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”,University ofMissouri–RollaVPOutput Inductor Input CapacitorsPower BlockInput CapacitorsOutput Capacitors Driver ICBottom LayerTop LayerPower Block Location on TopLayerCSD87353Q5DSLPS285C–AUGUST2011–REVISED Thermal PerformanceThe Power Block has the ability to use the GND planes as the primary thermal path.As such,the use of thermal vias is an effective way to pull away heat from the device and into the system board.Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:•Intentionally space out the vias from each other to avoid a cluster of holes in a given area.•Use the smallest drill size allowed in the design.The example in Figure34uses vias with a10mil drill hole and a16mil capture pad.•Tent the opposite side of the via with solder-mask.In the end,the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.Figure34.Recommended PCB Layout(Top Down View)M0187-01cTop View Front ViewSide View PinoutPositionDesignationPin 1V INPin 2V IN Pin 3T G Pin 4T GR Pin 5B G Pin 6V SW Pin 7V SW Pin 8V SW Pin 9P GNDCSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011MECHANICAL DATAQ5D Package DimensionsMILLIMETERSINCHESDIM MIN MAX MIN MAX a 1.40 1.50.0550.059b 0.3600.4600.0140.018c 0.1500.2500.0060.010c10.1500.2500.0060.010d 1.630 1.7300.0640.068d10.2800.3800.0110.015d20.2000.3000.0080.012d30.2910.3910.0120.015D1 4.900 5.1000.1930.201D2 4.269 4.3690.1680.172E 4.900 5.1000.1930.201E1 5.900 6.1000.2320.240E2 3.1063.2060.1220.126e 1.27TYP0.050f 0.3960.4960.0160.020L 0.5100.7100.0200.028θ0.00–––K0.8120.032M0188-01M0208-010.300 (0.012)CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011Land Pattern RecommendationNOTE:Dimensions are in mm (inches).Stencil RecommendationNOTE:Dimensions are in mm (inches).For recommended circuit layout for PCB designs,see application note SLPA005–Reducing Ringing Through PCB Layout Techniques .A0 = 5.30 ±0.10B0 = 6.50 ±0.10K0 = 1.90 ±0.10M0191-01CSD87353Q5DSLPS285C –AUGUST 2011–REVISED OCTOBER 2011Q5D Tape and Reel InformationNOTES:1.10-sprocket hole-pitch cumulative tolerance ±0.22.Camber not to exceed 1mm in 100mm,noncumulative over 250mm3.Material:black static-dissipative polystyrene4.All dimensions are in mm,unless otherwise specified.5.Thickness:0.30±0.05mm6.MSL1260°C (IR and convection)PbF reflow compatibleREVISION HISTORYChanges from Original (August 2011)to Revision A Page•Changed Application bullet From:High Current,Low Duty Cycle Applications To:High Current,High Duty CycleApplications ...........................................................................................................................................................................1•Remove Z DS(on)Max ..............................................................................................................................................................3•Deleted the Z DS(on)Max values in the Comparison table ....................................................................................................10•Add Electrical Performance bullet (13)Changes from Revision A (September 2011)to Revision B Page•Change Sync FET UIS From:500mJ To:551mJ .................................................................................................................2•Change Control FET UIS From:245mJ To:378mJ .............................................................................................................2•Change Control FET Rg values ............................................................................................................................................3•Change Sync FET Rg values ...............................................................................................................................................3•Updated Figure 26 (8)Changes from Revision B (September 2011)to Revision C Page•Changed the ROC table,Operating Current Max value From:25A To:40A (2)。