数字通信系统设计实验报告

实验1:用 Verilog HDL 程序实现乘法器1实验要求:(1) 编写乘法器的 Veirlog HDL 程序.(2) 编写配套的测试基准.(3) 通过 QuartusII 编译下载到目标 FPGA器件中进行验证(4) 注意乘法逻辑电路的设计.2 试验程序：Module multiplier(input rst,input clk,input [3:0]multiplicand,input [3:0]multiplier,input start_sig,output done_sig,output [7:0]result); reg [3:0]i;reg [7:0]r_result;reg r_done_sig;reg [7:0]intermediate;always @ ( posedge clk or negedge rst )if( !rst )begini<=4'b0;r_result<=8'b0;endelseif(start_sig)begincase(i)0:beginintermediate<={4'b0,multiplicand};r_result<=8'b0;i<=i+1;end1,2,3,4:beginif(multiplier[i-1])beginr_result<=r_result+intermediate;endintermediate<={intermediate[6:0],1'b0};i<=i+1;end5:beginr_done_sig<=1'b1;i<=i+1;end6:beginr_done_sig<=1'b0;i<=1'b0;endendcaseendassign result=r_done_sig?r_result:8'bz; assign done_sig=r_done_sig;endmodule3测试基准：`timescale 1 ps/ 1 psmodule multiplier_simulation();reg clk;reg rst;reg [3:0]multiplicand;reg [3:0]multiplier;reg start_sig;wire done_sig;wire [7:0]result;/***********************************/ initialbeginrst = 0; #10; rst = 1;clk = 1; forever #10 clk = ~clk;end/***********************************/ multiplier U1(.clk(clk),.rst(rst),.multiplicand(multiplicand),.multiplier(multiplier),.result(result),.done_sig(done_sig),.start_sig(start_sig));reg [3:0]i;always @ ( posedge clk or negedge rst ) if( !rst )begini <= 4'd0;start_sig <= 1'b0;multiplicand <= 4'd0;multiplier <= 4'd0;endelsecase( i )0: // multiplicand = 10 , multiplier = 2if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin multiplicand <= 4'd10; multiplier <= 4'd2; start_sig <= 1'b1; end1: // multiplicand = 15 , multiplier = 15if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin multiplicand <= 4'd15; multiplier <= 4'd15; start_sig <= 1'b1; end2: // multiplicand = 0 , multiplier = 0if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin multiplicand <= 4'd0; multiplier <= 4'd1; start_sig <= 1'b1; end3: // multiplicand = 7 , multiplier = 11if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin multiplicand <= 4'd7; multiplier <= 4'd11; start_sig <= 1'b1; end4:begin i <= i; endendcaseendmodule4仿真图形：实验2:用 Verilog HDL 程序实现二分频1实验要求:(1) 编写二分频的 Veirlog HDL 程序.(2) 编写配套的测试基准.(3) 掌握分频时序逻辑电路的设计方法(4) 学习时序逻辑电路的设计方法2 试验程序：module frequency_divider(input clk,input rst,output out_clk); reg r_out_clk;always@(posedge clk or negedge rst)if(!rst)beginr_out_clk<=1'b0;endelsebeginr_out_clk<=~r_out_clk;endassign out_clk=r_out_clk;endmodule3 测试基准：`timescale 1 ps/ 1 psmodule frequency_divider_simulation();reg clk;reg rst;wire out_clk;initialbeginrst = 0; #10; rst = 1;clk = 1; forever #10 clk = ~clk;endfrequency_divider U1(.clk(clk),.rst(rst),.out_clk(out_clk));endmodule4 仿真图形：实验3:用 Verilog HDL 程序实现一位四选一多路选择器1实验要求:(1) 编写一位四选一多路选择器的 Veirlog HDL 程序.(2) 编写配套的测试基准.(3) 通过 QuartusII 编译下载到目标 FPGA器件中进行验证.(4) 学会其逻辑时序的设计方法.2 试验程序：module data_selector(input clk,input rst,input [1:0]address,input [3:0]data,output out_data);reg r_out_data;always@(posedge clk or negedge rst)if(!rst)beginr_out_data<=1'bz;endelsebeginr_out_data<=data[address];endassign out_data=r_out_data;endmodule3 测试基准：module data_selector_simulation();reg clk;reg rst;reg [1:0]address;reg [3:0]data;wire out_data;initialbeginrst = 0; #10; rst = 1;clk = 1; forever #10 clk = ~clk;enddata_selector U1(.clk(clk),.rst(rst),.address(address),.data(data),.out_data(out_data));reg [3:0]i;always @ ( posedge clk or negedge rst ) if( !rst )begini <= 4'd0;endelsecase( i )0:begindata<=4'b1010;address<=2'd0;i<=i+1;end1:begindata<=4'b1010;address<=2'd1;i<=i+1;end2:begindata<=4'b1010;address<=2'd2;i<=i+1;end3:begindata<=4'b1010;address<=2'd3;i<=i+1;end4:begin i <= 4'd4; endendcaseendmodule4 仿真图形：实验4:用 Verilog HDL 程序实现四位加法器1实验要求:(1) 编写四位加法器的 Veirlog HDL 程序.(2) 编写配套的测试基准.(3) 通过 QuartusII 编译下载到目标 FPGA器件中进行验证.(4) 注意逻辑时序的描述设计方法2 试验程序：module adder(input rst,input clk,input [3:0]adder1,input [3:0]adder2,input start_sig,output [4:0]out_adder,output done_sig);reg [4:0]r_out_adder;reg [2:0]i;reg r_done_sig;always@(posedge clk or negedge rst)if(!rst)begini<=3'b0;r_out_adder=5'b0;endelsebeginif(start_sig)case(i)0:beginr_out_adder<={1'b0,adder1};i<=i+1;end1:beginr_out_adder<=r_out_adder+{1'b0,adder2};r_done_sig<=1'b1;i<=i+1;end2:begini<=0;r_done_sig<=1'b0;endendcaseendassign done_sig=r_done_sig;assign out_adder=i?5'bz:r_out_adder;endmodule3 测试基准：`timescale 1 ps/ 1 psmodule adder_simulation();reg clk;reg rst;reg [3:0]adder1;reg [3:0]adder2;reg start_sig;wire done_sig;wire [4:0]out_adder;/***********************************/initialbeginrst = 0; #10; rst = 1;clk = 1; forever #10 clk = ~clk;end/***********************************/adder U1(.clk(clk),.rst(rst),.adder1(adder1),.adder2(adder2),.out_adder(out_adder),.done_sig(done_sig),.start_sig(start_sig));reg [3:0]i;always @ ( posedge clk or negedge rst )if( !rst )begini <= 4'd0;start_sig <= 1'b0;adder1 <= 4'd0;adder2 <= 4'd0;endelsecase( i )0: // adder1 = 10 , adder2 = 2if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin adder1 <= 4'd10; adder2 <= 4'd2; start_sig <= 1'b1; end 1: // adder1= 15 , adder2 = 15if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin adder1 <= 4'd15; adder2 <= 4'd15; start_sig <= 1'b1; end 2: // adder1 = 0 , adder2 = 0if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin adder1 <= 4'd0; adder2 <= 4'd1; start_sig <= 1'b1; end3: // adder1 = 7 , adder2 = 11if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; endelse begin adder1 <= 4'd7; adder2 <= 4'd11; start_sig <= 1'b1; end4:begin i <= i; endendcaseendmodule4仿真图形：。