HCF4095BM1中文资料

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飞克 404E、406E、405、408和410激光距离计技术数据说明书

-10℃ to 60℃
Ingress protection
IP54
IP65
Drop test
1m
1m
Size
50 mm × 115mm × 29mm
52 mm × 116mm × 28mm
Weight
100g
110g
* Temperature for specified accuracy is 25°C ** Favorable conditions: white and diffuse reflection objects (white painted walls) ,low background illumination and moderate temperature *** Unfavorable conditions: objects with low or high reflectivity, high background illumination or the temperature is at the upper or lower limit of the specific temperature range
TECHNICAL DATA
Fluke 404E, 406E, 405, 408 and 410
Laser Distance Meter
Features and beneﬁts
● Quickly measure distance, calculate area / volume / pythagoras ● Auto level and height ● Built to withstand rainy or dusty conditions : 1-meter drop tested

EM4095中文资料

4 5 6 7 8
EM4095
13 12 11 10 9
µP
UPLINK
Signal on Transceiver coil Signal on Transponder coil
DOWNLINK
Signal on Transceiver coil Signal on Transponder coil
RDY/CLK
1 2 3 16 15 14
-
Data transmission by Amplitude Modulation with externally adjustable modulation index using single ended driver Multiple transponder protocol compatibility (Ex: EM400X, EM4050, EM4150, EM4070, EM4170, EM4069….) Sleep mode 1µA USB compatible power supply range 40 to +85°C temperature range Small outline plastic package SO16 Applications Car immobiliser Hand held reader Low cost reader
EM4095 P4095
13 12 11 10 9
µP
DVDD DVSS ANT2 VDD DEMOD_IN
Fig. 1
Fig. 3
Read/Write Mode
RDY/CLK
1 2 3 16 15 14
CDC2 CFCAP SHD DEMOD_OUT MOD CAGND CDEC

全自动冷库控制器说明书

冰山嘉德全自动冷库控制器（V1.0）●控制和人机交互界面采用独立的分体式设计，便于灵活配置。

●3个控制风机运行的继电器输出。

●1个控制供液电磁阀的继电器输出。

●1个控制回气电磁阀的继电器输出。

●1个控制旁通电磁阀的继电器输出。

●1个控制热氨冲霜电磁阀的继电器输出。

●1个控制水冲霜电磁阀继电器输出。

●1个控制排水管加热的继电器输出。

●1路用于自动控制的压力传感器或湿度传感器（4~20mA）信号输入。

●2路或4路（回风、出风）温度传感器信号输入。

●1路风机电流信号输入（电流互感器二次输出电流0~5A，可选）。

●9个用于控制和安全保护的开关量输入。

●控制器供电电源：24Vdc。

●控制部分有两个完全独立的RS485通信端口。

COMA用于和显示器相连，COMB为今后扩展备用。

●显示部分也有两个完全独立的RS485通信端口。

一个用于和控制器相连，另一个用于和上位机通信，进行远程控制和管理。

●通信采用RS485 Modbus RTU协议。

运行手册概述全自动冷库控制器（以下简称控制器）作为冰山嘉德公司因应当今信息化大潮提出的透明冷库概念的一部分，具有网络通信和远程控制功能。

该控制器可根据冷库运行状况实行对冷库的相关设备进行自动控制。

除此之外，它可以经过通信网络将冷库运行的工作状态及相关数据送往上位机，以便进行远程监控。

本手册是控制器的使用及操作说明，在手册中详细的说明了控制器的使用场合、功能用途、外部接线方式、参数设定方法、具体操作步骤、按钮功能说明、故障信息解释等内容。

使用控制器前，用户务必先详细阅读并了解本手册的内容。

一、工作原理全自动冷库控制器是一种利用微处理器数字控制技术对冷库进行全自动控制的装置。

它实时地对回风及出风温度进行跟踪采样，对冷库冷设备的工作状态进行检测，并按照设定的控制参数和控制逻辑对冷库设备（风机、加热器、供液、冲霜）进行控制。

全自动冷库控制器由两部分组成：GC1719-LCS控制单元和CAM1-LCS操作显示单元。

HCF4094B_04资料

1/13March 2004s3-STATE PARALLEL OUTPUTS FOR CONNECTION TO COMMON BUS sSEPARATE SERIAL OUTPUTSSYNCHRONOUS TO BOTH POSITIVE AND NEGATIVE CLOCK EDGES FOR CASCADINGs MEDIUM SPEED OPERATION 5MHz at 10V sQUIESCENT CURRENT SPECIFIED UP TO 20VsSTANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICSs 5V,10V AND 15V PARAMETRIC RATINGS sINPUT LEAKAGE CURRENTI I =100nA (MAX)AT V DD =18V T A =25°C s100%TESTED FOR QUIESCENT CURRENTDESCRIPTIONThe HCF4094B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages.The HCF4094B is an 8stages serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs.The parallel outputs may be connected directly to common bus lines.Data is shifted on positive clock transition.The data in each shift register stage is transferred to thestorage register when the STROBE input is high.Data in the storage register appears at the outputs whenever the OUTPUT-ENABLE signal is high.Two serial outputs are available for cascading a number of HCF4094B devices.Data is available at the Q S serial output terminal on positive clock edges to allow for high speed operation in cascaded system in which the clock rise time is fast.The same serial information,available at the Q’S terminal on the next negative clock edge,provides a means for cascading HCF4094B devices when the clock rise time is slow.HCF4094B8STAGE SHIFT AND STORE BUS REGISTERWITH 3-STATEOUTPUTSORDER CODESPACKAGE TUBE T &R DIP HCF4094BEY SOPHCF4094BM1HCF4094M013TRHCF4094B2/13IINPUT EQUIVALENT CIRCUITPIN DESCRIPTIONFUNCTIONAL DIAGRAMTRUTH TABLEOC :Open Circuit*At the positive clock edge information on the 7th shift register stage is transferred to the 8th register stage and the Q S output.PIN N°SYMBOL NAME AND FUNCTION 2DATA Data Input 1STROBE Strobe Input 3CLOCK Clock Input 9,10Q S ,Q’S Serial Outputs 4,5,6,7,14,13,12,11Q1to Q8Parallel Outputs 15OUTPUT ENABLE Output Enable Input 8V SS Negative Supply Voltage 16V DDPositive Supply VoltageHCF4094B3/13LOGIC DIAGRAMTIMINGCHARTHCF4094B4/13ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these conditions is not implied.All voltage values are referred to V SS pin voltage.(*)500mW at 65°C;derate to 300mW by 10mW/°C from 65°C to 85°CRECOMMENDED OPERATING CONDITIONSSymbol ParameterValue Unit V DD Supply Voltage -0.5to +22V V I DC Input Voltage -0.5to V DD +0.5V I I DC Input Current±10mA P D Power Dissipation per Package500(*)mW Power Dissipation per Output Transistor 100mW T op Operating Temperature -55to +125°C T stgStorage Temperature-65to +150°CSymbol ParameterValue Unit V DD Supply Voltage 3to 20V V I Input Voltage0to V DD V T opOperating Temperature-55to 125°CHCF4094B5/13DC SPECIFICATIONSThe Noise Margin for both "1"and "0"level is:1V min.with V DD =5V,2V min.with V DD =10V,2.5V min.with V DD =15VSymbolParameterTest ConditionValue UnitV I (V)V O (V)|I O |(µA)V DD (V)T A =25°C -40to 85°C -55to 125°C Min.Typ.Max.Min.Max.Min.Max.I LQuiescent Current0/550.045150150µA0/10100.0410*******/15150.04206006000/20200.0810030003000V OHHigh Level Output Voltage0/5<15 4.95 4.95 4.95V0/10<1109.959.959.950/15<11514.9514.9514.95V OLLow Level Output Voltage 5/0<150.050.050.05V10/0<1100.050.050.0515/0<1150.050.050.05V IHHigh Level Input Voltage 0.5/4.5<15 3.5 3.5 3.5V1/9<1107771.5/13.5<115111111V ILLow Level Input Voltage 4.5/0.5<15 1.5 1.5 1.5V9/1<11033313.5/1.5<115444I OHOutput Drive Current0/5 2.55-1.36-3.2-1.1-1.1mA0/5 4.65-0.44-1-0.36-0.360/109.510-1.1-2.6-0.9-0.90/1513.515-3.0-6.8-2.4-2.4I OLOutput Sink Current0/50.450.4410.360.36mA 0/100.510 1.1 2.60.90.90/15 1.515 3.06.8 2.42.4I IInput Leakage Current0/18Any Input 18±10-5± 0.1± 1± 1µA I OH,I OL 3-State OutputLeakage Current 0/180/1818±10-4± 0.4± 12±12µA C IInput Capacitance Any Input57.5pFHCF4094B6/13DYNAMIC ELECTRICAL CHARACTERISTICS (T amb =25°C,C L =50pF,R L =200K Ω,t r =t f =20ns)(*)Typical temperature coefficient for all V DD value is 0.3%/°C.SymbolParameterTest ConditionValue (*)UnitV DD (V)Min.Typ.Max.t PLH t PHL Propagation Delay Time(Clock to serial Output Q S )5300600ns 101252501595190t PLH t PHL Propagation Delay Time(Clock to serial Output Q’S )5230460ns101102201575150t PLH t PHL Propagation Delay Time(Clock to Parallel Output)5420840ns1019539015135270t PLH t PHL Propagation Delay Time(Strobe to Parallel Output)5290580ns1014529015100200t PZL,t PZH Propagation Delay TimeOutput Enable to Parallel Out:Output High to High Impedance 5140280ns10751501555110t PHZ t PLZ Propagation Delay TimeOutput Enable to Parallel Out:Output Low to High Impedance 5225450ns10951901570140t WStrobe Pulse Width5200100ns108040157035t WClock Pulse Width5200100ns1010050158340t setupData Setup Time512560ns105530153520t holdMinimum Hold Time5000ns1000015000t TLH t THL Transition Time5100200ns1050100154080t r,t fClock input Rise or Fall Time515µs105155f maxMaximum Clock Input Frequency5 1.25 2.5MHz10 2.551536HCF4094B7/13TYPICAL APPLICATION (REMOTE CONTROL HOLDING REGISTER)TEST CIRCUITC L =50pF or equivalent (includes jig and probe capacitance)R L =200K ΩR T =Z OUT of pulse generator (typically 50Ω)TESTSWITCH t PLH ,t PHL Open t PZL ,t PLZ V CC t PZH ,t PHZGNDHCF4094B8/13WAVEFORM 1:PROPAGATION DELAY TIMES,PULSE WIDTH (CLOCK),SETUP AND HOLD TIME (DATA IN TO CLOCK)(f=1MHz;50%duty cycle)WAVEFORM 2:PROPAGATION DELAY TIME,PULSE WIDTH (STROBE),SETUP AND HOLD TIME (STROBE TO CLOCK)(f=1MHz;50%dutycycle)HCF4094B9/13WAVEFORM 3:OUTPUT ENABLE AND DISABLE TIME (f=1MHz;50%dutycycle)HCF4094B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.13/13。

HEF4094BT中文资料

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges.
mA
−65
+150
°C
−40
+125
°C
[1] -
750
mW
[2] -
Hale Waihona Puke 500mWPpower dissipation
per output
-
100
mW
[1] For DIP16 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K. [2] For SO16 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K.
Symbol Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current

湖北标准电压互感器规格

湖北标准电压互感器规格湖北标准电压互感器规格湖北标准电压互感器，也称为高压互感器，是一种在高压端口上安装的电工仪表，通常用来测量电力系统中的电压，从而获得电压值或相关信息。

湖北标准电压互感器是一种安全、可靠和经济的仪表设备，广泛应用于各种电力系统的高压/低压/负荷测量等。

它有多种不同的规格，可以满足不同系统的需求。

一般情况下，湖北标准电压互感器规格是按照不同的阻抗来定义的，基本规格如下：1、电压互感器按其所接端口的电压来确定，根据主要有35kV、10kV、6kV、3kV、1.5kV等，例如35kV型号为WD35A-4002。

2、额定电流有2A、5A、10A、15A、20A、25A、50A等多种，一般以K型号表示，例如2A型号为K2A。

3、额定阻抗分为B类、C类、D类、F类等，一般以SH、SC、SD、SF等数字表示，例如B类阻抗为SH0.2。

4、额定频率分为50Hz、60Hz、400Hz等，一般以HZ型号表示，例如50Hz型号为HZ50。

此外，根据不同规格，还可以确定电压互感器的其它性能参数，如绝缘电阻、反响时间、分度值等。

比如湖北标准电压互感器的分度值一般为2.5、5、10、25、50、100等，一般以KV型号表示，例如KV2.5表示将电压值精确分割为2.5等份。

湖北标准电压互感器产品质量达到业界领先水平，可以满足不同类型电力系统高压/低压/负荷测量的需求。

它采用优质材料，拥有良好的阻燃、耐腐蚀、耐高温性能，可满足长期运行使用。

同时它还采用高精度和高稳定性特殊传感器，保证输出精确可靠，确保安全可靠测量。

U4091BM-R资料

Features Array•Speech Circuit with Anti-clipping•Tone-ringer Interface with DC/DC Converter•Speaker Amplifier with Anti-distortion•Power-supply Management (Regulated and Unregulated) and a Special Supply for Electret Microphone•Voice Switch•Interface for Answering Machine and Cordless Phone Array Applications•Feature Phone•Answering Machine•Fax Machine•Speaker Phone•Cordless PhoneBenefits•No Piezoelectric Transducer Necessary for Tone Ringing•Complete System Integration of Analog Signal Processing on One Chip•Very Few External Components1.DescriptionThe programmable telephone audio processor U4091BM-R is a linear integrated cir-cuit for use in feature phones, answering machines and fax machines. It contains the speech circuit, tone-ringer interface with DC/DC converter, sidetone equivalent and ear-protection rectifiers. The circuit is line-powered and contains all components nec-essary for signal amplification and adaptation to the line. The U4091BM-R can also be supplied via an external power supply. An integrated voice switch with loudspeakeramplifier enables hands-free or open-listening operation. With an anti-feedback func-tion, acoustic feedback during open listening can be reduced significantly. Thegenerated supply voltage is suitable for a wide range of peripheral circuits.24872A–CORD–08/05U4091BM-RFigure 1-1.Block Diagram34872A–CORD–08/05U4091BM-RFigure 1-2.Detailed Block Diagram42.Pin Configuration Figure 2-1.Pinning SSO4454872A–CORD–08/05U4091BM-RTable 2-1.Pin DescriptionPinSymbolFunction1RECIN Receive amplifier input (1)2TXACL Time constant adjustment for transmit anti-clipping 3MIC3Microphone input for hands-free operation4MIC2Input of symmetrical microphone amplifier with high common-mode rejection ratio 5MIC1Input of symmetrical microphone amplifier with high common-mode rejection ratio 6RECO2Output of the receive amplifier7RECO1Output of the receive amplifier, also used for sidetone network8IND The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A resistor connected to ground may be used to adjust the DC mask 9VL Positive supply-voltage input to the device in speech mode 10SENSE Input for sensing the available line current 11GND Ground, reference point for DC and AC signals 12VB Unstabilized supply voltage for speech network 13SAO2Negative output of speaker amplifier (push-pull only)14SAO1Positive output of speaker amplifier (single-ended and push-pull operation)15VMPS Unregulated supply voltage for the microcontroller (via series regulator to VMP)16VMP Regulated output voltage for supplying the microcontroller (typically 3.3V/6 mA in speech mode)17VMIC Reference node for microphone amplifier, supply for electret microphones 18TSACL Time constant for speaker amplifier anti-clipping 19VRING Input for ringer supply20IMP A Input for adjusting the ringer input impedance 21COSC 70-kHz oscillator for ringing power converter 22SWOUT Output for driving the external switch resistor 23INT Interrupt line for serial bus 24SCL Clock input for serial bus 25SDA Data line for serial bus 26OSCIN Input for 3.58-MHz oscillator 27RESET Reset output for the microcontroller 28OSCOUT Clock output for the microcontroller 29ES Input for external supply indication 30ADIN Input of A/D converter31BNMR Output of background-noise monitor receive 32BNMT Output of background-noise monitor transmit 33CT Time constant for mode switching of voice switch 34TLDR Time constant of receive-level detector 35INLDR Input of receive-level detector 36INLDT Input of transmit-level detector37TLDT Time constant of transmit-level detector 38IMPSW Switch for additional line impedance 39MICOMicrophone preamplifier outputNote:1.The protection device at pin RECIN is disconnected.64872A–CORD–08/05U4091BM-R3.DC Line Interface and Supply-voltage GenerationThe DC line interface consists of an electronic inductance and a dual-port output stage which charges the capacitors at VMPS and VB. The value of the equivalent inductance is given by:The U4091BM-R contains two identical series regulators which provide a supply voltage VMP of3.3V suitable for a microprocessor. In speech mode, both regulators are active because VMPS and VB are charged simultaneously by the DC line interface. The output current is 6 mA. The capacitor at VMPS is used to provide the microcomputer with sufficient power during long line interruptions. Thus, long flash pulses can be bridged or an LCD display can be turned on for more than 2 seconds after going on-hook. When the system is in ringing mode, VB is charged by the on-chip ringing power converter. In this mode, only one regulator is used to supply VMP with maximum 3 mA.4.Supply Structure of the ChipA main benefit of the U4091BM is the easy implementation of various applications due to the flexible system structure of the chip.Possible applications:•Group listening phone •Hands-free phone•Phones which feature ringing with the built-in speaker amplifier •Answering machine with external supplyThe special supply topology for the various functional blocks is shown in Figure 4-1 on page 7.There are four major supply states:1.Speech conditionIn speech condition, the system is supplied by the line current. If the LIDET block detects a line voltage above approximately 2V , the internal signal VLON is activated. This is detected via the serial bus, all the blocks which are needed have to be switched on via the serial bus.For line voltages below 2V , the switches remain in quiescent state as shown in the diagram.40AMPB Input for playback signal of answering machine 41AMREC Output for recording signal of answering machine 42STO Output for connecting the sidetone network 43STC Input for sidetone network 44STRCInput for sidetone networkTable 2-1.Pin DescriptionPinSymbolFunctionNote:1.The protection device at pin RECIN is disconnected.L 2R SENSE ×C IND R DC R 30×()××R DC R 30+()------------------------------------------------------------------------------------------=74872A–CORD–08/05U4091BM-R2.Power down (pulse dialing)When the chip is in power-down mode (bit LOMAKE), for example, during pulse dialing, all internal blocks are disabled via the serial bus. In this condition, the voltage regula-tors and their internal band gap are the only active blocks.3.RingingDuring ringing, the supply for the system is fed into VB via the Ringing Power Converter (RPC). Normally, the speaker amplifier in single-ended mode is used for ringing. The frequency for the melody is generated by the DTMF/Melody generator.4.External supplyIn an answering machine, the chip is powered by an external supply via pin VB. The answering machine connections can be directly made to U4091BM-R. The answering machine is connected to the pin AMREC. For the output AMREC, an AGC function is selectable via the serial bus. The output of the answering machine will be connected to the pin AMPB, which is directly connected to the switching matrix. This enables the sig-nal to be switched to every desired output.Figure 4-1.Supply Generator5.Ringing Power Converter (RPC)The RPC transforms the input power at VRING (high voltage/low current) into an equivalent out-put power at VB (low voltage/high current) which is capable of driving the low-ohmic loudspeaker. The input impedance at VRING is adjustable from 3 k Ω to 12 k Ω by R IMPA (Z RING = R IMPA / 100) and the efficiency of the step-down converter is approximately 65%.6.Ringing Frequency Detector (RFD)The U4091BM-R provides an output signal for the microcontroller. This output signal is always double the value of the input signal (ringing frequency). It is generated by a current comparator with hysteresis. The levels for the on-threshold are programmable in 16 steps, the off-level is fixed. Every change of the comparator output generates a high level at the interrupt output INT. The information can then be read out by means of a serial bus with either normal or fast read mode. The block RFD is always enabled.84872A–CORD–08/05U4091BM-R7.Clock Output Divider AdjustmentThe pin OSCOUT is a clock output which is derived from the crystal oscillator. It can be used to drive a microcontroller or another remote component and thereby reduces the number of crys-tals required. The oscillator frequency can be divided by 1, 8, 16, or 32. During power-on reset, the divider will be reset to 1 until it is changed by setting the serial bus.8.Serial Bus InterfaceThe circuit is controlled by an external microcontroller through the serial bus.The serial bus is a bi-directional system consisting of a single-directional clock line (SCL) which is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the microcontroller as well as by the U4091BM-R (see Figure 20-1 on page 37).The serial bus requires external pull-up resistors as only pull-down transistors (pin SDA) are integrated.8.1WRITEThe data is a 12-bit word:A0-A3: address of the destination register (0 to 15) D0-D7: content of the registerThe data line must be stable when the clock is high. Data must be shifted serially. After 12 clock periods, the write indication is sent. Then, the transfer to the destination register is (internally) generated by a strobe signal transition of the data line when the clock is high.8.2READThere is a normal and a fast-read cycle.In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indica-tor, then an 8-bit word is read out. The U4091BM-R drives the data line.The fast read cycle is indicated by a strobe signal. With the following two clocks the U4091BM-R reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is present (see Figure 10-1 on page 11, Figure 10-2 on page 11 and Figure 10-3 on page 11).Table 6-1.Threshold LevelRINGTH[0:3]V RING 07V 1522V Step1VTable 7-1.Clock OutputCLK[0:1]Divider Frequency 01 3.58 MHz 18447 kHz 216224 kHz 332112 kHz94872A–CORD–08/05U4091BM-R9.DTMF DialingThe DTMF generator sends a multi-frequency signal through the matrix to the line. The signal is the result of the sum of two frequencies and is internally filtered. The frequencies are chosen from a low and a high frequency group. The circuit conforms to the CEPT recommendation con-cerning DTMF option. Three different levels for the low level group and two different pre-emphasis (2.5 dB and 3.5 dB) can be chosen by means of the serial bus (rec. T/CF 46-03).Attention: In high gain mode, distortion can occur if AGATX is high and DC mask is low.10.Melody and Confidence Tone GenerationMelody and confidence tone frequencies are given in Table 10-1.The frequencies are provided at the DTMF input of the switch matrix. A sinusoidal wave, a square wave or a pulsed wave can be selected by the serial bus. A square signal means the out-put is high for half of the frequency cycle, and low for the other half. A pulsed signal means high impedance phases of 1/6 of the period occur between the high and low phases.Table 10-1.Status of Melody GeneratingDecimalDTMFM[0:2]Status0000DTMF generator OFF1001Confidence tone melody on (sine)2010Ringer melody (pulse)3011Ringer melody (square signal)4100DTMF (mid level)5101DTMF (low level)6110DTMF (high level)7111–Table 10-2.DTMF FrequenciesDecimalDTMFF[0:1]in DTMF ModeFrequencyError (%)000697–0.007101770–0.1562108520.0323119410.316Table 10-3.DTMF FrequenciesDecimalDTMFF[2:3]in DTMF ModeFrequency Error (%)0001209–0.11010113360.1232101477–0.0203111633–0.182104872A–CORD–08/05U4091BM-RTable 10-4.DTMFF4 in DTMF ModePre-emphasis SelectionLevel 0 2.5 dB 13.5 dBTable 10-5.DTMF and Melody FrequenciesDecimalDTMFF [0:4]f (Hz)Tone/Name Error (%)DTMF Freq.DTMP Freq.Key 000000440.0A 4–0.00869712091100001466.2A#4–0.01677012094200010493.9B 4–0.00385212097300011523.2C 40.0149411209*400100554.4C#40.01869713362500101587.3D 4–0.02377013365600110622.3D#4–0.12985213368700111659.3E 40.10694113360801000698.5F 4–0.21669714773901001740.0F#4–0.222770147761001010784.0G 40.126852147791101011830.0G#4–0.1699411477#1201100880.0A 50.2886971633A 1301101932.3A#5–0.0147701633B 1401110987.8B 5–0.0048521633C 150********.5C 5–0.3359411633D 16100001108.7C#5–0.3556971209117100011174.7D 5–0.0237701209418100101244.5D#5–0.1298521209719100111318.5E 50.1069411209*20101001396.9F 5–0.2146971336221101011480.0F#5–0.2227701336522101101568.0G 50.1268521336823101111661.2G#5–0.2419411336024110001760.0A 6–0.3026971477325110011864.6A#6–0.0147701477626110101975.5B 60.6658521477927110112093.0C 60.3679411477#28111002217.5C#60.3876971633A 29111012349.3D 60.7717701633B 30111102663.3---8521633C 31111112983.0---9411633D114872A–CORD–08/05U4091BM-RFigure 10-1.Write CycleFigure 10-2.Normal Read CycleFigure 10-3.Fast Read Cycle124872A–CORD–08/05U4091BM-RTable 10-6.Names and Functions of the Serial RegistersRegisterGroup Description StatusR0EnablesR0B0ENRING Enable ringer 1R0B1ERX Enable receive part 0R0B2ETX Enable transmit part 0R0B3ENVM Enable VM generator 1R0B4ENMIC Enable microphone 0R0B5ENSTBAL Enable sidetone0R0B6MUTE Muting earpiece amplifier 0R0B7ENRLT Enable POR low threshold1R1EnablesR1B0ENSACL Enable anti-clipping for speaker amplifier 0R1B1ENSA Enable speaker amplifier and AFS 0R1B2ENSAO Enable output stage speaker amplifier 0R1B3ENAM Enable answering machine connections 0R1B4ENAGC Enable AGC for answering machine 0R1B5Reserved -0R1B6Reserved -0R1B7FOFFC Speed up offset canceller 0R2MatrixR2B0I1O1Switch on MIC/LTX 0R2B1I1O2Switch on MIC/SA 0R2B2I1O3Switch on MIC/EPO 0R2B3I1O4Switch on MIC/AMREC 0R2B4I1O5Switch on MIC/AGCI 0R2B5I2O1Switch on DTMF/LTX 0R2B6I2O2Switch on DTMF/SA 0R2B7I2O3Switch on DTMF/EPO 0R3MatrixR3B0I2O4Switch on DTMF/AMREC 0R3B1I2O5Switch on DTMF/AGCI 0R3B2I3O1Switch on LRX/LTX 0R3B3I3O2Switch on LRX/SA 0R3B4I3O3Switch on LRX/EPO 0R3B5I3O4Switch on LRX/AMREC 0R3B6I3O5Switch on LRX/AGCI 0R3B7I4O1Switch on AMPB/LTX134872A–CORD–08/05U4091BM-RR4MatrixR4B0I4O2Switch on AMPB/SA 0R4B1I4O3Switch on AMPB/EPO 0R4B2I4O4Switch on AMPB/AMREC 0R5AGA TX MICLIMR4B3I4O5Switch on AMPB/AGCI 0R4B4I5O1Switch on AGCO/LTX 0R4B5I5O2Switch on AGCO/SA 0R4B6I5O3Switch on AGCO/EPO 0R4B7I5O4Switch on AGCO/AMREC 0R5B0EAFS Enable AFS block 0R5B1AGA TX0Gain transmit AGA LSB 0R5B2AGA TX1Gain transmit AGA 0R5B3AGA TX2Gain transmit AGA MSB 0R5B4MICHF Select RF-microphone input0R5B5DBM5Maximum transmit level for anti-clipping 0R5B6MIC0Gain microphone amplifier LSB 0R5B7MIC1Gain microphone amplifier MSB 0R6Shut down SidetoneR6B0SD Shut down 0R6B1Reserved -0R6B2SL0Slope adjustment for sidetone LSB 0R6B3SL1Slope adjustment for sidetone MSB 0R6B4LF0Low frequency adjustment for sidetone LSB 0R6B5LF1Low frequency adjustment for sidetone 0R6B6LF2Low frequency adjustment for sidetone 0R6B7LF3Low frequency adjustment for sidetone MSB 0R7Sidetone AGARXR7B0P0Pole adjustment for sidetone LSB 0R7B1P1Pole adjustment for sidetone 0R7B2P2Pole adjustment for sidetone 0R7B3P3Pole adjustment for sidetone 0R7B4P4Pole adjustment for sidetone MSB 0R7B5AGARX0Gain receive AGC LSB 0R7B6AGARX1Gain receive AGC 0R7B7AGARX2Gain receive AGC MSB 0R8EARA LineimpedanceR8B0EA0Gain earpiece amplifier LSB 0R8B1EA1Gain earpiece amplifier 0R8B2EA2Gain earpiece amplifier 0R8B3EA3Gain earpiece amplifier 0R8B4EA4Gain earpiece amplifier MSB 0R8B5IMPH Line impedance selection (1 = 1 k Ω)0R8B6LOMAKE Short circuit during pulse dialing0R8B7AIMPSwitch for additional external line impedanceTable 10-6.Names and Functions of the Serial Registers (Continued)Register Group Description Status144872A–CORD–08/05U4091BM-RR9AFSR9B0AFS0AFS gain adjustment LSB 0R9B1AFS1AFS gain adjustment 0R9B2AFS2AFS gain adjustment 0R9B3AFS3AFS gain adjustment 0R9B4AFS4AFS gain adjustment 0R9B5AFS5AFS gain adjustment MSB 0R9B6AFS4PS Enable 4-point sensing 0R9B7Reserved -0R10SAR10B0SA0Gain speaker amplifier LSB 0R10B1SA1Gain speaker amplifier 0R10B2SA2Gain speaker amplifier 0R10B3SA3Gain speaker amplifier 0R10B4SA4Gain speaker amplifier MSB0R10B5SE Speaker amplifier single-ended mode0R10B6LSCUR0Speaker amplifier charge-current adjustment LSB 0R10B7LSCUR1Speaker amplifier charge-current adjustment MSB 0R11ADCR11B0ADC0Input selection ADC 0R11B1ADC1Input selection ADC 0R11B2ADC2Input selection ADC 0R11B3ADC3Input selection ADC 0R11B4NWT Network tuning0R11B5SOC Start of ADC conversion 0R11B6ADCR Selection of ADC range 0R11B7MSKIT Mask for interrupt bits 0R12DTMFR12B0DTMFF0DTMF frequency selection 0R12B1DTMFF1DTMF frequency selection 0R12B2DTMFF2DTMF frequency selection 0R12B3DTMFF3DTMF frequency selection 0R12B4DTMFF4DTMF frequency selection 0R12B5DTMFM0Generator mode selection 0R12B6DTMFM1Generator mode selection 0R12B7DTMFM2Generator mode selection0R13CLK RTH TMR13B0CLK0Selection clock frequency for microcontroller 0R13B1CLK1Selection clock frequency for microcontroller 0R13B2RTH0Ringer threshold adjustment LSB 0R13B3RTH1Ringer threshold adjustment 0R13B4RTH2Ringer threshold adjustment 0R13B5RTH3Ringer threshold adjustment MSB 0R13B6TME0Test mode enable (low active)0R13B7TME1Test mode enable (high active)Table 10-6.Names and Functions of the Serial Registers (Continued)RegisterGroup DescriptionStatus154872A–CORD–08/05U4091BM-R10.1Power-on ResetTo avoid undefined states of the system when it is powered on, an internal reset clears the inter-nal registers.The system (U4091BM-R + microcontroller) is woken up by any of the following conditions:•VMP > 2.75V and VB > 2.95V •and line voltage (VL)•or ringer (VRING)•or external supply (ES)The power-down of the circuit is caused by a shut-down sent by the serial bus (SD = 1), low-volt-age reset, or by the watchdog function (see Figure 12-2 on page 17, Figure 12-3 on page 17 and Figure 12-4 on page 17).11.Watchdog FunctionTo avoid the system operating the microcontroller in a fault state, the circuit provides a watchdog function. The watchdog has to be retriggered every second by triggering the serial bus (sending information to the IC or other remote components at the serial bus). If there has been no bus transmission for more than one second, the watchdog initiates a reset.The watchdog provides a reset for the external microcontroller, but does not change the U4091BM-R’s registers.R14TM CLORR14B0TME2Test mode enable (high active)0R14B1TME3Test mode enable (low active)0R14B2Reserved -0R14B3CLOR0Adjustment for calculated receive log amp LSB 0R14B4CLOR1Adjustment for calculated receive log amp 0R14B5CLOR2Adjustment for calculated receive log amp 0R14B6CLOR3Adjustment for calculated receive log amp 0R14B7CLOR4Adjustment for calculated receive log amp MSB 0R15CLOTR15B0Reserved -0R15B1Reserved -0R15B2Reserved -0R15B3CLOT0Adjustment for calculated transmit log amp LSB 0R15B4CLOT1Adjustment for calculated transmit log amp 0R15B5CLOT2Adjustment for calculated transmit log amp 0R15B6CLOT3Adjustment for calculated transmit log amp 0R15B7CLOT4Adjustment for calculated transmit log amp MSBTable 10-6.Names and Functions of the Serial Registers (Continued)RegisterGroup DescriptionStatus164872A–CORD–08/05U4091BM-R12.Acoustic Feedback SuppressionAcoustical feedback from the loudspeaker to the hands-free microphone may cause instability of the system. The U4091BM-R has a very efficient feedback-suppression circuit which offers a 4-point or (alternatively) a 2-point signal-sensing topology (see Figure 12-1).Two attenuators (TXA and SAI) reduce the critical loop gain via the serial bus either in the trans-mit or in the receive path. The overall loop gain remains constant under all operating conditions.The LOGs produce a logarithmically-compressed signal of the TX- and RX-envelope curve. The AFSCON block determines whether the TX or the RX signal has to be attenuated.The voice-switch topology can be selected by the serial bus. In 2-point-sensing mode, AFSCON is controlled directly by the LOG outputs.Figure 12-1.Basic System Configurations174872A–CORD–08/05U4091BM-RFigure 12-2.Power-on Reset (Line)Figure 12-3.Power-on Reset (Ringing)Figure 12-4.Power-on Reset (Low Voltage Reset)Line LID VMPLVI Reset OSCOUTLVI LVR184872A–CORD–08/05U4091BM-R12.1Dial-tone DetectorThe dial-tone detector is a comparator with one side connected to the speaker amplifier input and the other to VM with a 35-mV offset (see Figure 12-5 on page 21). If the circuit is in idle mode, and the incoming signal is greater than 35 mV (25 mV rms ), the comparator's output will change thus disabling the receive idle mode. This circuit prevents the dial tone (which would be considered as continuous noise) from fading away as the circuit would have the tendency to switch to idle mode. By disabling the receive idle mode, the dial tone remains at the normally expected full level.12.2Background Noise MonitorsThis circuit distinguishes speech (which consists of bursts) from background noise (a relatively constant signal level). There are two background-noise monitors, one for the receive path and the other for the transmit path. The receive background-noise monitor is operated on by the receive level detector, while the transmit background noise monitor is operated on by the trans-mit level detector (see Figure 12-6 on page 21). They monitor the background noise by storing a DC voltage representative of the respective noise levels in capacitors at CBNMR and CBNMT. The voltages at these pins have slow rise times (determined by the internal current source and an external capacitor), but fast decay times. If the signal at TLDR (or TLDT) changes slowly, the voltage at BNMR (or BNMT) will remain more positive than the voltage at the non-inverting input of the monitor's output comparator. When speech is present, the voltage at the non-inverting input of the comparator will rise more quickly than the voltage at the inverting input (due to the burst characteristic of speech), causing its output to change. This output is sensed by the mode-control block.12.34-point SensingIn 4-point-sensing mode, the receive- and the transmit-sensing paths include additional CLOGs (calculated logarithmic amplifiers). The block MODECON compares the detector output signals and decides whether receive, transmit or idle mode has to be activated. Depending on the mode decision, MODECON generates a differential voltage to control AFSCON.The MODECON block has seven inputs:•The output of the transmit log (LOGT) – the comparison of LOGT, CLOGR •The output of the receive clog (CLOGR) – designated I1•The output of the transmit clog (CLOGT) – the comparison of CLOGT , LOGR •The output of the receive log (LOGR) – designated I2•The output of the transmit background-noise monitor (BNMT) – designated I3•The output of the receive background-noise monitor (BNMR) – designated I4•The output of the dial-tone detectorThe differential output (AFST, AFSR) of the block MODECON controls AFSCON. The effect of I1-I4 in Table 12-1 on page 19.194872A–CORD–08/05U4091BM-RNote:X = don’t care; Y = I3 and I4 are not both noise.12.4Term Definitions1.Transmit means the transmit attenuator is fully on, and the receive attenuator is at max-imum attenuation.2.Receive means the receive attenuator is fully on, and the transmit attenuator is at max-imum attenuation.3.In idle mode, the transmit and receive attenuator are at half of their maximumattenuation.–Change mode means both the transmit and receive speech are present inapproximately equal levels. The attenuators are quickly switched (30 ms) to the opposite mode until one speech level dominates the other.–Idle means speech has ceased in both transmit and receive paths. The attenuators are then slowly switched (1.5s) to idle mode.4.Switching to full transmit or receive modes from the idle mode is done at a fast rate(30 ms).Table 12-1.Mode Decision for Signal SensingInputOutputI1I2I3I4 Mode T T S X T ransmit T R Y Y Change mode R T Y Y Change mode R R X S Receive T T N X Idle T R N N Idle R T N N Idle RRXNIdleLOGT > CLOGR I1 = T LOGT < CLOGR I1 = R LOGR < CLOGT I2 = T LOGR > CLOGTI2 = R BNMT detects speech I3 = S BNMT detects noise I3 = N BNMR detects speech I4 = S BNMR detects noise I4 = N204872A–CORD–08/05U4091BM-R12.5Summary of Truth Table1.The circuit will switch to transmit mode if–Both transmit level detectors sense higher signal levels than the respective receive level detectors, and–The transmit background-noise monitor indicates the presence of speech 2.The circuit will switch to receive mode if–Both receive level detectors sense higher signal levels than the respective transmit level detectors, and–The receive background-noise monitor indicates the presence of speech 3.The circuit will switch to the reverse mode if–The level detectors disagree on the relative strengths of the signal levels, and –At least one of the background-noise monitors indicates speech 4.The circuit will switch to idle mode when–Both speakers are quiet (no speech present), or–When one speaker speech level is continuously overridden by noise at the other speaker’s locationThe time required to switch the circuit between transmit, receive and idle is determined by inter-nal current sources and the capacitor at pin CT. A diagram of the CT circuitry is shown in Figure 12-7 on page 21. It operates as follows:•CCT is typically 4.7 µF .•To switch to transmit mode, ITX is turned on (IRX is off), charging the external capacitor to –240 mV below VM. (An internal clamp prevents further charging of the capacitor.)•To switch to receive mode, IRX is turned on (ITX is off), increasing the voltage on the capacitor to +240 mV with respect to VM.•To switch to reverse mode, the current sources ITX, IRX are turned off, and the current source IFI is switched on, discharging the capacitor to VM.•To switch to idle mode, the current sources ITX, IRX, IFI are turned off, and the current source ISI charges the capacitor to VM.214872A–CORD–08/05U4091BM-RFigure 12-5.Dial Tone DetectorFigure 12-6.Background Noise MonitorFigure 12-7.Generation of Control Voltage (CT) for Mode Switching224872A–CORD–08/05U4091BM-RFigure 12-8.Block Diagram Hands-free Mode U4091BM-R 2-point Signal SensingFigure 12-9.Block Diagram Hands-free Mode U4091BM-R 4-point Signal Sensing234872A–CORD–08/05U4091BM-R13.Analog-to-Digital Converter (ADC)This circuit is a 7-bit successive-approximation analog-to-digital converter in switched capacitor technique. An internal band gap circuit generates a 1.25-V reference voltage which is the equiv-alent of 1 MSB (1 LSB = 19.5 mV). The possible input voltage at ADIN is 0V to 2.48V.The ADC needs an SOC (Start Of Conversion) signal. In the High phase of the SOC signal, the ADC is reset. Then, 50 µs after the beginning of the Low phase of the SOC signal, the ADC gen-erates an EOC (End Of Conversion) signal which indicates that the conversion is finished. The rising edge of EOC generates an interrupt at the INT output. The result can be read out by the serial bus.Voltages higher than 2.45V have to be divided. The signal connected to the ADC is determined by 4 bits: ADC0, ADC1, ADC2 and ADC3. TLDR/TLDT measuring is possible relative to a pre-ceding reference measurement. The current range of IL can be doubled by ADCR. If ADCR is High, S has the value 0.5, otherwise S = 1.The source impedance at ADIN must be lower than 250 k Ω.Accuracy: 1 LSB + 3%Figure 13-1.Timing of ADCFigure 13-2.ADC Input SelectionADIN 0.4 x VB 0.4 x VMPS 0.4 x SAO10.4 x VMP8 x (TLDR - REF)8 x (TLDT - REF)0.4 x OFF10.4 x OFF20.4 x OFF3IL x 20 mV/(1 mA x S)ADCMSB BIT5BIT4BIT3BIT2BIT1LSBSOCEOC。

华宝空调红外遥控编码资料

华宝空调红外遥控编码资料简介华宝空调是一款广泛使用的家用空调品牌，它提供了方便的红外遥控功能，使得用户可以轻松控制空调的各种设置。

本文将介绍华宝空调红外遥控编码资料，包括红外遥控编码的原理、常用编码格式、编码数据的解析和使用方法等。

红外遥控编码原理红外遥控编码是通过发送特定的红外脉冲信号来实现对设备的控制。

华宝空调红外遥控编码原理基于脉冲宽度调制（PWM）技术，即通过调整脉冲信号的宽度来表示不同的控制指令。

常用编码格式华宝空调红外遥控编码使用了一种常见的编码格式，即NEC编码格式。

NEC编码格式是一种广泛应用于红外遥控领域的标准编码格式，它使用了32位二进制数据表示一个完整的红外遥控指令。

NEC编码格式的具体结构如下： - Header：8位数据，用于表示一个遥控指令的开始。

- Address：8位数据，用于表示遥控器的地址。

- Command：8位数据，用于表示具体的遥控指令。

- Inverted Command：8位数据，用于表示Command的反码。

编码数据的解析要解析华宝空调红外遥控编码数据，可以按照以下步骤进行： 1. 接收红外遥控编码数据。

2. 解析Header，判断是否为一个完整的红外遥控指令。

3. 解析Address，获取遥控器的地址。

4. 解析Command，获取具体的遥控指令。

5. 对Command进行处理，执行相应的操作。

使用方法要使用华宝空调红外遥控编码，可以按照以下步骤进行： 1. 获取红外遥控编码数据。

2. 解析编码数据，获取遥控指令。

3. 根据遥控指令，执行相应的操作，如调整温度、风速、模式等。

下面是一个示例代码，演示如何使用华宝空调红外遥控编码进行温度调节：# 导入红外遥控库import infrared_remote_control as irc# 获取红外遥控编码数据data = irc.get_infrared_data()# 解析编码数据header = irc.parse_header(data)address = irc.parse_address(data)command = irc.parse_command(data)# 判断遥控指令类型if command == "temperature_up":# 温度增加temperature = irc.get_current_temperature()irc.set_temperature(temperature + 1)elif command == "temperature_down":# 温度减少temperature = irc.get_current_temperature()irc.set_temperature(temperature - 1)else:# 其他指令pass总结华宝空调红外遥控编码资料介绍了红外遥控编码的原理、常用编码格式、编码数据的解析和使用方法。

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s16MHz TOGGLE RATE(Typ.)atV DD-V SS=10Vs GATED INPUTSs QUIESCENT CURRENT SPECIFIED UP TO 20Vs5V,10V AND15V PARAMETRIC RATINGSs INPUT LEAKAGE CURRENTI I=100nA(MAX)AT V DD=18V T A=25°Cs100%TESTED FOR QUIESCENT CURRENT s MEETS ALL REQUIREMENTS OF JEDEC JESD13B”STANDARD SPECIFICATIONSFOR DESCRIPTION OF B SERIES CMOSDEVICES”DESCRIPTIONHCF4095B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4095B is J-K Master-Slave Flip-Flops featuring separate AND gating of multiple J and K inputs.The gated J-K input control transfers information into the master section during clocked rmation on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse.SET and RESET inputs (active high)are provided for asynchronous operation.HCF4095BGATED J-K MASTER SLAVE FLIP-FLOPPIN CONNECTION ORDER CODESPACKAGE TUBE T&R DIP HCF4095BEYSOP HCF4095BM1HCF4095M013TRDIP SOP1/11September2002HCF4095BINPUT EQUIVALENT CIRCUIT PIN DESCRIPTIONPIN No SYMBOL NAME AND FUNCTION3,4,5J1to J3J Inputs11,10,9K1to K3K Inputs8Q Q Output6Q Q Output13SET(S)Set Inputs(Active High)2RESET(R)Reset Inputs(Active High)12CLOCK Clock Inputs1NC Not Connected7V SS Negative Supply Voltage14V DD Positive Supply Voltage TRUTH TABLE:SYNCHRONOUS OPERATION(S=0R=0)INPUTS BEFORE POSITIVE CLOCK TRANSITION OUTPUTS AFTER POSITIVE CLOCK TRANSITION J*K*Q QL L NO CHANGEL H L HH L H LH H TOGGLES(*):J=J1•J2•J3,K=K1•K2•K3TRUTH TABLE:ASYNCHRONOUS OPERATION(J and K DON’T CARE)INPUTS BEFORE POSITIVE CLOCK TRANSITION OUTPUTS AFTER POSITIVE CLOCK TRANSITION S R Q QL L NO CHANGEL H L HH L H LH H L L(*):L=Vss,H=Vdd2/11HCF4095B FUNCTIONAL DIAGRAMLOGIC DIAGRAM3/11HCF4095B4/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur.Functional operation under these conditions is not implied.All voltage values are referred to V SS pin voltage.RECOMMENDED OPERATING CONDITIONSDC SPECIFICATIONSSymbol ParameterValue Unit V DD Supply Voltage -0.5to +22V V I DC Input Voltage -0.5to V DD +0.5V I I DC Input Current±10mA P D Power Dissipation per Package200mW Power Dissipation per Output Transistor 100mW T op Operating Temperature -55to +125°C T stgStorage Temperature-65to +150°CSymbol ParameterValue Unit V DD Supply Voltage 3to 20V V I Input Voltage0to V DD V T opOperating Temperature-55to 125°CSymbolParameterTest ConditionValue UnitV I (V)V O (V)|I O |(µA)V DD (V)T A =25°C -40to 85°C -55to 125°C Min.Typ.Max.Min.Max.Min.Max.I LQuiescent Current0/550.0213030µA0/10100.02260600/15150.024*******/20200.0420600600V OHHigh Level Output Voltage0/5<15 4.95 4.95 4.95V0/10<1109.959.959.950/15<11514.9514.9514.95V OLLow Level Output Voltage 5/0<150.050.050.05V10/0<1100.050.050.0515/0<1150.050.050.05V IHHigh Level Input Voltage 0.5/4.5<15 3.5 3.5 3.5V1/9<1107771.5/13.5<115111111V ILLow Level Input Voltage 4.5/0.5<15 1.5 1.5 1.5V9/1<11033313.5/1.5<115444I OHOutput Drive Current0/5 2.5<15-1.36-3.2-1.15-1.1mA0/5 4.6<15-0.44-1-0.36-0.360/109.5<110-1.1-2.6-0.9-0.90/1513.5<115-3.0-6.8-2.4-2.4I OLOutput Sink Current0/50.4<150.4410.360.36mA0/100.5<110 1.1 2.60.90.90/151.5<1153.06.82.4 2.4HCF4095B5/11The Noise Margin for both ”1”and ”0”level is:1V min.with V DD =5V,2V min.with V DD =10V,2.5V min.with V DD =15VDYNAMIC ELECTRICAL CHARACTERISTICS (T amb =25°C,C L =50pF,R L =200K Ω,t r =t f =20ns)(*)Typical temperature coefficient for all V DD value is 0.3%/°C.I I Input Leakage Current0/18Any Input 18±10-5±0.1±1±1µA C IInput CapacitanceAny Input57.5pF SymbolParameterTest ConditionValue (*)UnitV DD (V)Min.Typ.Max.t PLH t PHL Propagation Delay Time5250500ns 101002001575150t PLH t PHL Propagation Delay Time(Set or Reset)5150300ns10751501550100t TLH t THL Transition Time5100200ns1050100154080f CLMaximum Clock Input Frequency 5 3.57MHz10816151224t WClock Pulse Width514070ns106030154020t r,t fClock input Rise or Fall Time515µs105155t WSet or Reset Pulse Width5200100ns1010050155025t setupData Setup Time5400200ns10160801510050SymbolParameterTest ConditionValue UnitV I (V)V O (V)|I O |(µA)V DD (V)T A =25°C -40to 85°C -55to 125°C Min.Typ.Max.Min.Max.Min.Max.HCF4095B6/11TEST CIRCUITC L =50pF or equivalent (includes jig and probe capacitance)R L =200K ΩR T =Z OUT of pulse generator (typically 50Ω)WAVEFORM :PROPAGATION DELAY,TRANSITION AND SETUP TIMEHCF4095B WAVEFORM:CLOCK PULSE,RISE AND FALL TIMETYPICAL APPLICATION:T-TYPE FLIP-FLOP7/11HCF4095BTYPICAL APPLICATION:SYNCHRONOUS BINARY DIVIDE BY TEN COUNTERTRUTH TABLESTATE QA QB QC QD 0L L L L1H L L L2L H L L3H H L L4L L H L5H L H L6L H H L7H H H L8L L L H9H L L H NOTE:In all units the Set and Reset are Connected to V SS.8/11HCF4095B Plastic DIP-14MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.a10.510.020B 1.39 1.650.0550.065b0.50.020b10.250.010D200.787E8.50.335e 2.540.100e315.240.600F7.10.280I 5.10.201L 3.30.130Z 1.27 2.540.0500.100P001A9/11HCF4095B10/11DIM.mm.inchMIN.TYP MAX.MIN.TYP.MAX.A 1.750.068 a10.10.20.0030.007 a2 1.650.064 b0.350.460.0130.018 b10.190.250.0070.010 C0.50.019c145°(typ.)D8.558.750.3360.344 E 5.8 6.20.2280.244 e 1.270.050e37.620.300F 3.8 4.00.1490.157G 4.6 5.30.1810.208 L0.5 1.270.0190.050 M0.680.026 S°(max.)SO-14MECHANICAL DATAPO13G8元器件交易网HCF4095B Information furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specificationsmentioned in this publication are subject to change without notice.This publication supersedes and replaces all informationpreviously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2002STMicroelectronics-Printed in Italy-All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia-Brazil-Canada-China-Finland-France-Germany-Hong Kong-India-Israel-Italy-Japan-Malaysia-Malta-MoroccoSingapore-Spain-Sweden-Switzerland-United Kingdom-United States.© 11/11。