MAX6363LUT26+T中文资料
MA26V16资料

Variable Capacitance Diodes
MA26V16
Silicon epitaxial planar type
Unit: mm
For VCO ■ Features
3
0.65±0.01
2 0.05±0.03
Junction temperature Storage temperature
125
■ Electrical Characteristics Ta = 25°C ± 3°C
Parameter Symbol IR Reverse current
tf o ht llow tp in :// g pa U na RL so a ni bo c. u ne t l t/s ate c/ st en in f
10
1 −25
−5
15
35
55
75
Ambient temperature Ta (°C)
2
Pl
ea s
e
vi
si
tf o ht llow tp in :// g pa U na RL so a ni bo c. u ne t l t/s ate c/ st en in f
SKD00084CED
102
Forward current IF (mA)
CD (Ta) CD (Ta = 25°C)
80
Ta = 85°C
−25°C
VR = 1 V 1.015 1.005 0.995 0.985 0.975 0.965 3V
60
MAX322CPA+中文资料

_______________General DescriptionThe MAX320/MAX321/MAX322 are precision, dual,SPST analog switches designed to operate from ±3V to ±8V dual supplies. The MAX320 has two normally open (NO) switches and the MAX321 has two normally closed (NC) switches. The MAX322 has one NO and one NC switch. Low power consumption (1.25mW)makes these parts ideal for battery-powered equip-ment. They offer low leakage currents (100pA max) and fast switching speeds (t ON = 150ns max, t OFF = 100ns max).The MAX320 series, powered from ±5V supplies, offers 35Ωmax on-resistance (R ON ), 2Ωmax matching between channels, and 4Ωmax R ON flatness.These switches also offer 5pC max charge injection and a minimum of 2000V ESD protection per Method 3015.7.For equivalent devices specified for single-supply oper-ation, see the MAX323/MAX324/MAX325 data sheet.For quad versions of these switches, see the MAX391/MAX392/MAX393 data sheet.________________________ApplicationsBattery-Operated Systems Sample-and-Hold Circuits Heads-Up Displays Guidance and Control Systems Audio and Video Switching Military RadiosTest Equipment Communications Systems ±5V DACs and ADCsPBX, PABX____________________________Featureso Low On-Resistance, 35Ωmax (16Ωtypical)o R ON Matching Between Channels <2Ωo R ON Flatness <4Ωo Guaranteed Charge Injection <5pC o Bipolar Supply Operation (±3V to ±8V)o Low Power Consumption, <1.25mW o Low Leakage Current Over Temperature, <2.5nA at +85°C o Fast Switching, t ON <150ns, t OFF <100ns o Guaranteed Break-Before-Make (MAX322 only)______________Ordering InformationMAX320/MAX321/MAX322Precision, Dual-Supply, SPSTAnalog Switches________________________________________________________________Maxim Integrated Products 1_____________________Pin Configurations/Functional Diagrams/Truth TablesCall toll free 1-800-998-8800 for free samples or literature.19-0350; Rev 0; 12/94* Contact factory for dice specifications.** Contact factory for availability.Voltage Referenced to V-V+................................................................(V- - 0.3V) to +17V IN_, COM_, NC_, NO_ (Note 1).........(V- - 0.3V) to (V+ + 0.3V)Continuous Current (any terminal)......................................30mA Peak Current, COM_, NO_, NC_(pulsed at 1ms, 10% duty cycle max)..............................100mA ESD per Method 3015.7..................................................>2000V Continuous Power DissipationPlastic DIP (derate 9.09mW/°C above +70°C).............727mW Narrow SO (derate 5.88mW/°C above +70°C).............471mWµMAX (derate 4.10mW/°C above +70°C).....................330mW CERDIP (derate 8.00mW/°C above +70°C)..................640mW Operating Temperature RangesMAX32_C_ _........................................................0°C to +70°C MAX32_E_ _......................................................-40°C to +85°C MAX32_MJA...................................................-55°C to +125°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10sec).............................+300°CM A X 320/M A X 321/M A X 322Precision, Dual-Supply, SPST Analog Switches 2_______________________________________________________________________________________Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ABSOLUTE MAXIMUM RATINGSNote 1:Signals on NC_, NO_, COM_, or IN_ exceeding V+ or V- are clamped by internal diodes. Limit forward diode current tomaximum current rating.ELECTRICAL CHARACTERISTICS(V+ = +5V ±10%, V- = -5V ±10%, V INH = 3.5V, V INL = 2.5V, T A = T MIN to T MAX , unless otherwise noted.)MAX320/MAX321/MAX322Precision, Dual-Supply, SPSTAnalog Switches_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS(V+ = +5V ±10%, V- = -5V ±10%, V INH = 3.5V, V INL = 2.5V, T A = T MIN to T MAX , unless otherwise noted.)Note 2:The algebraic convention where the most negative value is a minimum and the most positive value a maximum is used in this data sheet.Note 3:Guaranteed by design.Note 4:∆R ON = ∆R ON max - ∆R ON min.Note 5:Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range.Note 6:Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at +25°C.Note 7:Off Isolation = 20 log 10[ V COM ⁄ (V NC or V NO )], V COM = output, V NC or V NO = input to off switch.Note 8:Between any two switches.M A X 320/M A X 321/M A X 322Precision, Dual-Supply, SPST Analog Switches 4_________________________________________________________________________________________________________________________________Typical Operating Characteristics(V+ = +5V, V- = -5V, T A = +25°C, unless otherwise noted.)0.0001-556585OFF LEAKAGE CURRENT vs. TEMPERATURE10TEMPERATURE (°C)O F F L E A K A G E C U R R E N T (n A )-1552545-351051250.10.00110.011000-8-602ON-RESISTANCE vs. VOLTAGE AT COM PIN30V COM (V)R O N (Ω)-4-24682052510150-5-3-4-234ON-RESISTANCE vs. VOLTAGE AT COM PIN(OVER TEMPERATURE)30V COM (V)R O N (Ω)-11252052515100-5-1ON-RESISTANCE MATCH vs. VOLTAGE AT COM PIN (OVER TEMPERATURE)V COM (V)∆R O N (Ω)130.300.350.100.050.400.450.200.250.150.505-30.0001-556585ON LEAKAGE CURRENT vs. TEMPERATURE10TEMPERATURE (°C)O N L E A K A G E C U R R E N T (n A )-1552545-351051250.10.00110.011000-556585SUPPLY CURRENT vs. TEMPERATURE100120M A X 320-07TEMPERATURE (°C)I S U P P L Y (µA )2545-35-15510512580204060140-20-5CHARGE INJECTION vs. VOLTAGE AT COM PIN15M A X 320-06V COM (V)Q (p C )-1050-15105-10-520-4-3-21234MAX320/MAX321/MAX322Precision, Dual-Supply, SPSTAnalog Switches_______________________________________________________________________________________5__________Applications InformationLogic LevelsCalculate the logic thresholds typically as follows: V IH =(V+ - 1.5V) and V IL = (V+ - 2.5V).Power-supply consumption is minimized when IN1 and IN2 are driven with logic-high levels equal to V+ and logic-low levels well below the calculated V IL of (V+ - 2.5V). IN1and IN2 can be driven to V- without damage.Analog Signal LevelsAnalog signals that range over the entire supply voltage (V- to V+) can be switched, with very little change in on-resistance over the entire voltage range (see Typical Operating Characteristics ). All switches are bidirec-tional, so NO_, NC_, and COM_ pins can be used as either inputs or outputs.Power-Supply Sequencing and Overvoltage ProtectionDo not exceed the absolute maximum ratings, because stresses beyond the listed ratings may cause perma-nent damage to the devices.Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+, followed by V-,before applying analog signals or logic inputs, especial-ly if the analog or logic signals are not current-limited. Ifthis sequencing is not possible, and if the analog or logic inputs are not current-limited to <30mA, add two small signal diodes (D1, D2) as shown in Figure 1.Adding protection diodes reduces the analog signal range to a diode drop (about 0.7V) below V+ for D1,and a diode drop above V- for D2. Leakage is not affected by adding the diodes. On-resistance increas-es by a small amount at low supply voltages. Maximum supply voltage (V- to V+) must not exceed 17V.Adding protection diode D1 causes the logic thresh-olds to be shifted relative to the positive power-supply rail. This can be significant when low positive supply voltages (+5V or less) are used. Driving IN1 and IN2 all the way to the supply rails (i.e., to a diode drop higher than the V+ pin or a diode drop lower than the V- pin) is always acceptable.The protection diodes D1 and D2 also protect against some overvoltage situations. With the circuit of Figure 1,if the supply voltage is below the absolute maximum rating and if a fault voltage up to the absolute maximum rating is applied to an analog signal pin, no damage will result. For example, with ±5V supplies, analog sig-nals up to ±8.5V will not damage the circuit of Figure 1.If only a single fault signal is present, the fault voltage can rise to +12V or to -12V without damage._____________________Pin DescriptionFigure 1. Overvoltage Protection Using Two External Blocking DiodesM A X 320/M A X 321/M A X 322Precision, Dual-Supply, SPST Analog Switches 6_______________________________________________________________________________________Figure 4. Charge InjectionFigure 2. Switching TimeFigure 3. Break-Before-Make Interval (MAX322 only)______________________________________________Test Circuits/Timing DiagramsMAX320/MAX321/MAX322Precision, Dual-Supply, SPSTAnalog Switches_______________________________________________________________________________________7Figure 6. Crosstalk_________________________________Test Circuits/Timing Diagrams (continued)Figure 8. Channel-On CapacitanceFigure 7. Channel-Off Capacitance__Ordering Information (continued)___________________Chip Topography0.075" (1.90mm)0.055" (1.40mm)V+ IN2V-IN1COM2NO2 (MAX320) NC2 (MAX321/2)COM1NO1 (MAX320/2) NC1 (MAX321)* Contact factory for dice specifications.** Contact factory for availability.TRANSISTOR COUNT: 91SUBSTRATE CONNECTED TO V+M A X 320/M A X 321/M A X 322Precision, Dual-Supply, SPST Analog Switches________________________________________________________Package Informationimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.8___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600©1994 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.。
MAX9236EUM中文资料

General DescriptionThe MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply,allowing 1.8V to 5V output logic levels. All these devices are hot-swappable and allow “on-the-fly” frequency programming.The MAX9234/MAX9236/MAX9238 feature DC balance,which allows isolation between a serializer and deseri-alizer using AC-coupling. Each deserializer decodes data transmitted by one of the MAX9209/MAX9211/MAX9213/MAX9215 serializers.The MAX9234 has a rising-edge output strobe. The MAX9236/MAX9238 have a falling-edge output strobe.The MAX9234/MAX9236/MAX9238 operate in DC-balanced mode only.The MAX9234/MAX9236 operate with a parallel input clock of 8MHz to 34MHz, while the MAX9238 operates from 16MHz to 66MHz. The transition time of the single-ended outputs is increased on the low-frequency version parts (MAX9234/MAX9236) for reduced EMI. The LVDS inputs meet ISO 10605 ESD specification, ±25kV for Air-Gap Discharge and ±8kV Contact Discharge.The MAX9234/MAX9236/MAX9238 are available in 48-pin TSSOP packages and operate over the -40°C to +85°C temperature range.ApplicationsAutomotive Navigation Systems Automotive DVD Entertainment Systems Digital Copiers Laser PrintersFeatures♦DC Balance Allows AC-Coupling for Wider Input Common-Mode Voltage Range ♦On-the-Fly Frequency Programming ♦Operating Frequency Range8MHz to 34MHz (MAX9234/MAX9236)16MHz to 66MHz (MAX9238)♦Falling-Edge Output Strobe (MAX9236/MAX9238)♦Slower Output Transitions for Reduced EMI (MAX9234/MAX9236)♦High-Impedance Outputs when PWRDWN Is Low Allow Output Busing ♦5V-Tolerant PWRDWN Input♦PLL Requires No External Components ♦Up to 1.386Gbps Throughput♦Separate Output Supply Pins Allow Interface to 1.8V, 2.5V, 3.3V, and 5V Logic ♦LVDS Inputs Meet ISO 10605 ESD Requirements ♦LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS Standard ♦Low-Profile, 48-Lead TSSOP Package ♦+3.3V Main Power Supply♦-40°C to +85°C Operating Temperature RangeMAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers________________________________________________________________Maxim Integrated Products 1Ordering Information19-3641; Rev 1; 10/07For pricing, delivery, and ordering information,please contact Maxim Direct at 1-888-629-4642,or visit Maxim’s website at .Functional Diagram and Pin Configuration appear at end of data sheet.M A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS(V CC = +3.0V to +3.6V, V CCO = +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐V ID ⏐= 0.05V to 1.2V, input common-mode voltage V CM = ⏐V ID /2⏐to 2.4V - ⏐V ID /2⏐, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = V CCO =+3.3V, ⏐V ID ⏐= 0.2V, V CM = 1.25V, T A = +25°C.) (Notes 1, 2)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V CC to GND...........................................................-0.5V to +4.0V V CCO to GND.........................................................-0.5V to +6.0V RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V PWRDWN to GND....................................................-0.5V to 6.0V RxOUT_, RxCLK OUT to GND................-0.5V to (V CCO + 0.5V)Continuous Power Dissipation (T A = +70°C)48-Pin TSSOP (derate 16mW/°C above +70°C).......1282mW Storage Temperature Range.............................-65°C to +150°C Junction Temperature......................................................+150°CESD ProtectionHuman Body Model (R D = 1.5k Ω, C S = 100pF)All Pins to GND..................................………………….±5kV IEC 61000-4-2 (R D = 330Ω, CS = 150pF)Contact Discharge (RxIN_, RxCLK IN_) to GND .........±8kV Air-Gap Discharge (RxIN_, RxCLK IN_) to GND .......±15kV ISO 10605 (R D = 2k Ω, C S = 330pF)Contact Discharge (RxIN_, RxCLK IN_) to GND ........±8kV Air Discharge (RxIN_, RxCLK IN_) to GND ...............±25kV Lead Temperature (soldering, 10s).................................+300°CMAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS (continued)(V CC = +3.0V to +3.6V, V CCO = +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐V ID ⏐= 0.05V to 1.2V, input common-mode voltage V CM = ⏐V ID /2⏐to 2.4V - ⏐V ID /2⏐, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = V CCO =+3.3V, ⏐V ID ⏐= 0.2V, V CM = 1.25V, T A = +25°C.) (Notes 1, 2)M A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 4_______________________________________________________________________________________TH TL Note 2:Maximum and minimum limits overtemperature are guaranteed by design and characterization. Devices are productiontested at T A = +25°C.Note 3:AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.Note 4:C L includes probe and test jig capacitance.Note 5:RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.Note 6:RSKM measured with ≤150ps cycle-to-cycle jitter on RxCLK IN.AC ELECTRICAL CHARACTERISTICS(V CC = V CCO = +3.0V to +3.6V, 100mV P-P at 200kHz supply noise, C L = 8pF, PWRDWN = high, differential input voltage ⏐V ID ⏐=0.1V to 1.2V, input common mode voltage V CM = ⏐V ID /2⏐to 2.4V - ⏐V ID /2⏐, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = V CCO = +3.3V, ⏐V ID ⏐= 0.2V, V CM = 1.25V, T A = +25°C.) (Notes 3, 4, 5)MAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers_______________________________________________________________________________________5MAX9234/MAX9236WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCYFREQUENCY (MHz)S U P P L Y C U R R E N T (m A )30252015104030506070809010054035MAX9238WORST-CASE PATTERN AND PRBS SUPPLY CURRENT vs. FREQUENCYFREQUENCY (MHz)S U P P L Y C U R R E N T (m A )60504030206040801001201401601801070MAX9234/MAX9236RxOUT TRANSITION TIMEvs. OUTPUT SUPPLY VOLTAGE (V CCO )OUTPUT SUPPLY VOLTAGE (V)O U T P U T T R A N S I T I O N T I M E (n s )4.54.03.53.012345672.55.0MAX9238RxOUT TRANSITION TIMEvs. OUTPUT SUPPLY VOLTAGE (V CCO )OUTPUT SUPPLY VOLTAGE (V)O U T P U T T R A N S I T I O N T I M E (n s )4.54.03.53.0123452.55.0Typical Operating Characteristics(V CC = V CCO = +3.3V, C L = 8pF, PWRDWN = high, differential input voltage ⏐V ID ⏐= 0.2V, input common-mode voltage V CM = 1.2V,T A = +25°C, unless otherwise noted.)M A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 6_______________________________________________________________________________________Pin DescriptionMAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers_______________________________________________________________________________________7Detailed DescriptionThe MAX9234/MAX9236 operate at a parallel clock fre-quency of 8MHz to 34MHz. The MAX9238 operates at a parallel clock frequency of 16MHz to 66MHz. The tran-sition times of the single-ended outputs are increased on the MAX9234/MAX9236 for reduced EMI.DC BalanceData coding by the MAX9209/MAX9211/MAX9213/MAX9215 serializers (which are companion devices to the MAX9234/MAX9236/MAX9238 deserializers) limits the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the varia-tion in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the data channels is 10. At most, 10 more zeros than ones,or 10 more ones than zeros, are transmitted. The maxi-mum DSV for the clock channel is five. Limiting the DSV and choosing the correct coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on AC-coupled links.To obtain DC balance on the data channels, the serial-izer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary.Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9234/MAX9236/MAX9238 deserializers whether the data bits are inverted (see Figure 9). The deserializer restores the original state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintain DC balance.AC-Coupling BenefitsBit errors experienced with DC-coupling can be elimi-nated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the com-mon-mode voltage range of an LVDS receiver to nearly the voltage rating of the capacitor. The typical LVDS dri-ver output is 350mV centered on an offset voltage of 1.25V, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0 to 2.4V, allowing approximately ±1V common-mode differ-ence between the driver and receiver on a DC-coupledCommon-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than ±1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage differ-ence up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-bal-anced coding of the data is required to maintain the dif-ferential signal amplitude and limit jitter on an AC-coupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling.However, two capacitors—one at the serializer output and one at the deserializer input—provide protection in case either end of the cable is shorted to a high voltage.Figure 1. LVDS Input CircuitM A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 8_______________________________________________________________________________________Figure 4. LVDS Receiver Input Skew MarginFigure 5a. MAX9234 Output Setup/Hold and High/Low TimesFigure 5b. MAX9236/MAX9238 Output Setup/Hold and High/Low TimesFigure 6a. MAX9234 Clock-IN to Clock-OUT DelayFigure 6b. MAX9236/MAX9238 Clock-IN to Clock-OUT DelayFigure 7. Phase-Locked Loop Set TimeMAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers_______________________________________________________________________________________9MAX9234/MAX9236/MAX9238 vs.MAX9210/MAX9220/MAX9222The MAX9234/MAX9236/MAX9238 operate in DC-bal-ance mode only. Pinouts are the same as the MAX9210/MAX9220/MAX9222 except that pin 6 on the MAX9234/MAX9236/MAX9238 is no connect (N.C.). DC balance allows AC-coupling with series capacitors. The MAX9234/MAX9236/MAX9238 are hot-swappable and the input frequency can be changed on the fly, but oth-erwise the specifications and functionality are the same as the MAX9210/MAX9220/MAX9222 operating in DC-balance mode. See Table 1.Applications InformationSelection of AC-Coupling CapacitorsVoltage droop and the DSV of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level.The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (R T ), the LVDS driver output resistor (R O ), and the series AC-coupling capac-itors (C). The RC time constant for two equal-value series capacitors is (C x (R T + R O )) / 2 (Figure 10). The RC time constant for four equal-value series capacitors is (C x (R T + R O )) / 4 (Figure 11).R T is required to match the transmission line imped-ance (usually 100Ω) and R O is determined by the LVDS driver design (the minimum differential output resis-tance of 78Ωfor the MAX9209/MAX9211/MAX9213/MAX9215 serializers is used in the following example).This leaves the capacitor selection to change the sys-tem time constant.Figure 9. Deserializer Serial InputFigure 8. Power-Down DelayM A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS DeserializersFigure 10. Two Capacitors per Link, AC-CoupledMAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers______________________________________________________________________________________11In the following example, the capacitor value for a droop of 2% is calculated. J itter due to this droop is then calculated assuming a 1ns transition time:C = - (2 x t B x DSV) / (ln (1 - D) x (R T + R O )) (Eq 1)where:C = AC-coupling capacitor (F).t B = bit time (s).DSV = digital sum variation (integer).ln = natural log.D = droop (% of signal amplitude).R T = termination resistor (Ω).R O = output resistance (Ω).Equation 1 is for two series capacitors (Figure 10). The bit time (t B ) is the period of the parallel clock divided by 9. The DSV is 10. See equation 3 for four series capaci-tors (Figure 11).The capacitor for 2% maximum droop at 8MHz parallel rate clock is:C = - (2 x t B x DSV) / (ln (1 - D) x (R T + R O ))C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω+ 78Ω))C = 0.0773µFJ itter due to droop is proportional to the droop and transition time:t J = t T x D (Eq 2)where:t J = jitter (s).t T = transition time (s) (0 to 100%).D = droop (% of signal amplitude).Jitter due to 2% droop and assumed 1ns transition time is:t J = 1ns x 0.02t J = 20psThe transition time in a real system depends on the fre-quency response of the cable driven by the serializer.The capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and e high-frequency, surface-mount ceramic capacitors.Equation 1 altered for four series capacitors (Figure 11) is:C = - (4 x t B x DSV) / (ln (1 - D) x (R T + R O )) (Eq 3)Input Bias and Frequency DetectionThe inverting and noninverting LVDS inputs are internally connected to +1.2V through 42k Ω(min) to provide bias-ing for AC-coupling (Figure 1).A frequency-detection circuit on the clock input detects when the input is not switching, or is switching at low frequency. In this case,all outputs are driven low. To prevent switching due to noise when the clock input is not driven, bias the clock input to differential +15mV by connecting a 10k Ω±1%pullup resistor between the noninverting input and V CC ,and a 10k Ω±1% pulldown resistor between the invert-ing input and ground. These bias resistors, along with the 100Ω±1% tolerance termination resistor, provide +15mV of differential input.Unused LVDS Data InputsAt each unused LVDS data input, pull the inverting input up to V CC using a 10k Ωresistor, and pull the noninverting input down to ground using a 10k Ωresistor. Do not con-nect a termination resistor. The pullup and pulldown resis-tors drive the corresponding outputs low and prevent switching due to noise.PWRDWNDriving PWRDWN low puts the outputs in high imped-ance, stops the PLL, and reduces supply current to 50µA or less. Driving PWRDWN high drives the outputs low until the PLL locks. The outputs of two deserializers can be bused to form a 2:1 mux with the outputs con-trolled by PWRDWN . Wait 100ns between disabling one deserializer (driving PWRDWN low) and enabling the second one (driving PWRDWN high) to avoid con-tention of the bused outputs.Input Clock and PLL Lock TimeThere is no required timing sequence for the applica-tion or reapplication of the parallel rate clock (RxCLK IN) relative to PWRDWN , or to a power-supply ramp for proper PLL lock. The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and clock should be stable to meet the lock-time specification. When the PLL is locking, the outputs are low.Power-Supply BypassingThere are separate on-chip power domains for digital circuits, outputs, PLL, and LVDS inputs.Bypass each V CC , V CCO , PLL V CC , and LVDS V CC pin with high-fre-quency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possi-ble, with the smallest value capacitor closest to the supply pin.Cables and ConnectorsInterconnect for LVDS typically has a differential imped-ance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field cancel-ing effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.M A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 12______________________________________________________________________________________Board LayoutKeep the LVTTL/LVCMOS outputs and LVDS input sig-nals separated to prevent crosstalk. A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended.ESD ProtectionThe MAX9234/MAX9236/MAX9238 ESD tolerance is rated for IEC 61000-4-2 Human Body Model and ISO 10605 standards. IEC 61000-4-2 and ISO 10605 specifiy ESD tolerance for electronic systems. The Human Body Model discharge components are C S = 100pF and R D =1.5k Ω(Figure 12). For the Human Body Model, all pins are rated for ±5kV contact discharge. The ISO 10605 dis-charge components are C S = 330pF and R D = 2k Ω(Figure 13). For ISO 10605, the LVDS outputs are rated for ±8kV contact and ±25kV air discharge. The IEC 61000-4-2 discharge components are C S = 150pF and R D = 330Ω(Figure 14). For IEC 61000-4-2, the LVDS inputs are rated for ±8kV Contact Discharge and ±15kV Air-Gap Discharge.5V Tolerant InputPWRDWN is 5V tolerant and is internally pulled down to GND.Skew Margin (RSKM)Skew margin (RSKM) is the time allowed for degrada-tion of the serial data sampling setup and hold times by sources other than the deserializer. The deserializer sampling uncertainty is accounted for and does not need to be subtracted from RSKM. The main outside contributors of jitter and skew that subtract from RSKM are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew.V CCO Output Supply and Power DissipationThe outputs have a separate supply (V CCO ) for interfacing to systems with 1.8V to 5V nominal input-logic levels. The DC Electrical Characteristics table gives the maximum supply current for V CCO = 3.6V with 8pF load at several switching frequencies with all outputs switching in the worst-case switching pattern. The approximate incremen-tal supply current for V CCO other than 3.6V with the same 8pF load and worst-case pattern can be calculated using:I I = C T V I 0.5f C x 21 (data outputs)+ C T V I f C x 1 (clock output)where:I I = incremental supply current.C T = total internal (C INT ) and external (C L ) load capaci-tance.V I = incremental supply voltage.f C = output clock-switching frequency.The incremental current is added to (for V CCO >3.6V)or subtracted from (for V CCO <3.6V) the DC Electrical Characteristics table maximum supply current. The internal output buffer capacitance is C INT = 6pF. The worst-case pattern-switching frequency of the data out-puts is half the switching frequency of the output clock.In the following example, the incremental supply current is calculated for V CCO = 5.5V, f C = 34MHz, and C L = 8pF:V I = 5.5V - 3.6V = 1.9VC T = C INT + C L = 6pF + 8pF = 14pFFigure 13. ISO 10605 Contact Discharge ESD Test CircuitFigure 12. Human Body ESD Test CircuitFigure 14. IEC 61000-4-2 Contact Discharge ESD Test CircuitMAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializers______________________________________________________________________________________13where:I I = C T V I 0.5F C x 21 (data outputs) + C T V I f C x 1 (clock output).I I = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x 34MHz).I I = 9.5mA + 0.9mA = 10.4mA.The maximum supply current in DC-balanced mode for V CC = V CCO = 3.6V at f C = 34MHz is 106mA (from the DC Electrical Characteristics table). Add 10.4mA to get the total approximate maximum supply current at V CCO = 5.5V and V CC = 3.6V.If the output supply voltage is less than V CCO = 3.6V,the reduced supply current can be calculated using the same formula and method.At high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power-dissipation rating. Do not exceed the maximum package power-dissipation rating. See the Absolute Maximum Ratings for maximum package power-dissipation capacity and temperature derating.Rising- or Falling-Edge Output StrobeThe MAX9234 has a rising-edge output strobe, which latches the parallel output data into the next chip on the rising edge of RxCLK OUT. The MAX9236/MAX9238have a falling-edge output strobe, which latches the parallel output data into the next chip on the falling edge of RxCLK OUT. The deserializer output strobe polarity does not need to match the serializer input strobe polarity. A deserializer with rising- or falling-edge output strobe can be driven by a serializer with a rising-edge input strobe.Pin ConfigurationChip InformationMAX9234 TRANSISTOR COUNT: 14,104MAX9236 TRANSISTOR COUNT: 14,104MAX9238 TRANSISTOR COUNT: 14,104PROCESS: CMOSM A X 9234/M A X 9236/M A X 9238Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers 14______________________________________________________________________________________Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)MAX9234/MAX9236/MAX9238Hot-Swappable, 21-Bit, DC-Balanced LVDSDeserializersMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________15©2007 Maxim Integrated Productsis a registered trademark of Maxim Integrated Products, Inc.Revision History。
MAX3232EEAE+T中文资料

Battery-Powered Equipment Cell Phones Cell-Phone Data Cables Notebook, Subnotebook, and Palmtop Computers
Applications
Printers Smart Phones xDSL Modems
MAX3222EEPN -40°C to +85°C 18 Plastic DIP —
MAX3232ECAE 0°C to +70°C 16 SSOP
—
MAX262中文资料

M A X262中文资料(总5页) -CAL-FENGHAI.-(YICAI)-Company One1-CAL-本页仅作为文档封面,使用请直接删除在电子电路中,滤波器是不可或缺的部分,其中有源滤波器更为常用。
一般有源滤波器由运算放大器和RC元件组成,对元器件的参数精度要求比较高,设计和调试也比较麻烦。
美国Maxim公司生产的可编程滤波器芯片MAX262可以通过编程对各种低频信号实现低通、高通、带通、带阻以及全通滤波处理,且滤波的特性参数如中心频率、品质因数等,可通过编程进行设置,电路的外围器件也少。
本文介绍MAX262的情况以及由它构成的程控滤波器电路。
1 MAX262芯片介绍MAX262芯片是Maxim公司推出的双二阶通用开关电容有源滤波器,可通过微处理器精确控制滤波器的传递函数(包括设置中心频率、品质因数和工作方式)。
它采用CMOS工艺制造,在不需外部元件的情况下就可以构成各种带通、低通、高通、陷波和全通滤波器。
图1是它的引脚排列情况。
图1 MAX262引脚V+ ——正电源输入端。
V- ——负电源输入端。
GND ——模拟地。
CLKA ——外接晶体振荡器和滤波器A 部分的时钟输入端,在滤波器内部,时钟频率被2分频。
CLKB ——滤波器B 部分的时钟输入端,同样在滤波器内部,时钟频率被2分频。
CLKOUT ——晶体振荡器和R-C振荡的时钟输出端。
OSCOUT ——与晶体振荡器或R-C振荡器相连,用于自同步。
INA、INB ——滤波器的信号输入端。
BPA、BPB——带通滤波器输出端。
LPA、LPB——低通滤波器输出端。
HPA、HPB——高通、带阻、全通滤波器输出端。
WR ——写入有效输入端。
接V+时,输人数据不起作用;接V-时,数据可通过逻辑接口进入一个可编程的内存之中,以完成滤波器的工作模式、f0及Q的设置。
此外,还可以接收TTL电平信号,并上升沿锁存输人数据。
A0、A1、A2、A3 ——地址输人端,可用来完成对滤波器工作模式、f0和Q的相应设置。
MAX706中文资料_数据手册_参数

UNREGULATED DC
MAX667 +5V DC LINEAR
REGULATOR
PUSHBUTTON SWITCH
VCC
RESMR
MAX706 MAX813L
PFO
µP
VCC RESET I/O LINE NMI INTERRUPT
___________________________Features
o Available in Tiny µMAX Package
o Guaranteed RESET Valid at VCC = 1V o Precision Supply-Voltage Monitor
4.65V in MAX705/MAX707/MAX813L 4.40V in MAX706/MAX708
Output Current (all outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C) . . . . . . . 727mW SO (derate 5.88mW/°C above +70°C) . . . . . . . . . . . . . . . 471mW µMAX (derate 4.10mW/°C above +70°C) . . . . . . . . . . . . 330mW
3) A 1.25V threshold detector for power-fail warning, low-battery detection, or for monitoring a power supply other than +5V.
MAX1682-MAX1683中文资料

ELECTRICAL CHARACTERISTICS
(VIN = +5.0V, capacitor values from Table 2, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER No-Load Supply Current Supply Voltage Range Minimum Operating Voltage Oscillator Frequency Output Resistance Voltage Conversion Efficiency TA = +25°C RLOAD = 10kΩ (Note 2) TA = +25°C IOUT = 5mA IOUT = 0mA, TA = +25°C MAX1682 MAX1683 TA = +25°C TA = 0°C to +85°C 98 99.9 8.4 24.5 CONDITIONS MAX1682 MAX1683 TA = +25°C TA = 0°C to +85°C 2.0 2.1 MIN TYP 110 230 1.7 1.8 1 12 35 20 15.6 45.5 50 65 MAX 145 310 5.5 5.5 UNITS µA V V kHz Ω %
OUTPUT RESISTANCE vs. SUPPLY VOLTAGE
80 OUTPUT RESISTANCE (Ω) 70 60 50 40 30 20 10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) MAX1683, C1 = C2 = 10µF MAX1682, C1 = C2 = 10µF MAX1683, C1 = C2 = 3.3µF
max263翻译

Max263(264)是开关电容有源滤波器设计用于精密滤波应用。
中心频率,Q,工作模式都可以通过输入引脚选择。
Max263不需要用外部元件去实现带通,低通,高通,全通滤波。
max263是专门带通应用程序和包含一个通用运算放大器。
两个第二阶滤波器部分都包含在这两个设备。
通过fclk/f0Max263和267的中心频率可以到达57KHZ,而max264和268可以到达140KHZ。
Max263(264)有28个引脚,max267(268)有24个引脚。
1、滤波器设计软件化2、中心频率32阶可控3、Q值128阶可控4、Q值与f0独立可编程5、f0可达140KHz6、支持+5V和士5V两种供电方式芯片诸引脚功能如下(括号内数字为引脚号):V+(10):供电正极, 并接旁路电容尽量靠近该脚V-(18):供电负极, 并接旁路电容尽量靠近该脚GND(19):模拟地CLKA(13):A单元元时钟输人, 该时钟在芯片内部被二分频CLKB(14):B单元时钟输人, 该时钟在芯片内部被二分频OSC OUT(20):连至晶体, 组成晶振电路(若接时钟信号时, 该脚不连)INA,INB(5,1):滤波器输人BPA,BPB(3,27): 带通输出LPA,LPB(2,28):低通输出HPA,HPB(4,26):高通、带陷、全通输出M0,M1(8,7):模式选择,+5V高,-5V低F0-F4(24,17,23,12,11):时钟与中心频率比值(FCLK/f0)编程端Q0-Q6(15,16,21,22,25,6,9):Q编程端。
1、供给电压士15V2、输入电压士0.3V3、输入电流士50Ma对M0、M1两个管脚编程可使芯片工作于模式1、2、3、4几种方式,对应的功能如表1所示。
时钟与中心频率比值与编码对应如表2所示。
模式1:当我们要实现全极点低通或带通滤波器如切比雪夫、巴特沃斯滤波器时这种模式是很有用的, 有时该模式也用来实现带陷滤波器, 但由于相关零极点位置固定, 使得用作带陷时受到限制。
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For free samples and the latest literature, visit or phone 1-800-998-8800.For small orders, phone 1-800-835-8769.General DescriptionThe MAX6361–MAX6364 supervisory circuits reduce the complexity and number of components required for power-supply monitoring and battery control functions in microprocessor (µP) systems. The circuits significantly improve system reliability and accuracy compared to that obtainable with separate ICs or discrete components.Their functions include µP reset, backup battery switchover, and power failure warning.The MAX6361–MAX6364 operate from supply voltages as low as +1.2V. The factory-preset reset threshold voltage ranges from 2.32V to 4.63V (see Ordering Information ).These devices provide a manual reset input (MAX6361),watchdog timer input (MAX6362), battery-on output (MAX6363), and an auxiliary adjustable reset input (MAX6364). In addition, each part type is offered in three reset output versions: an active-low open-drain reset, an active-low open-drain reset, and an active-high open-drain reset (see Selector Guide at end of data sheet).ApplicationsFeatures♦Low +1.2V Operating Supply Voltage (V CC or V BATT )♦Precision Monitoring of +5.0V, +3.3V, +3.0V, and +2.5V Power-Supply Voltages♦Debounced Manual Reset Input (MAX6361)♦Watchdog Timer with 1.6s Timeout Period (MAX6362)♦Battery-On Output Indicator (MAX6363)♦Auxiliary User-Adjustable RESET IN (MAX6364)♦Three Available Output StructuresPush-Pull RESET , Open-Drain RESET , Open-Drain RESET♦RESET/RESET Valid Down to 1.2V Guaranteed (V CC or V BATT )♦Power-Supply Transient Immunity ♦150ms (min) Reset Timeout Period ♦Small 6-Pin SOT23 PackageMAX6361–MAX6364SOT23, Low-Power µP Supervisory Circuitswith Battery Backup________________________________________________________________Maxim Integrated Products119-1615; Rev 3; 11/05Ordering InformationPin ConfigurationsFrom the table below, select the suffix corresponding to the desired threshold voltage and insert it into the part number to complete it. When ordering from the factory, there is a 2500-piece minimum on the SOT package (tape-and-reel only).Devices are available in both leaded and lead-free packaging.Specify lead-free by replacing "-T" with "+T" when ordering.Computers ControllersIntelligent Instruments Critical µP/µC Power MonitoringFax Machines Industrial Control POS EquipmentPortable/Battery-Powered EquipmentSelector Guide appears at end of data sheet.Typical Operating Circuit appears at end of data sheet.M A X 6361–M A X 6364SOT23, Low-Power µP Supervisory Circuits with Battery BackupABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V CC = +2.4V to +5.5V, V BATT = 3V, T A = -40°C to +85°C, reset not asserted. Typical values are at T A = +25°C, unless otherwise noted.) (Note 1)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Terminal Voltages (with respect to GND)V CC , BATT, OUT.......................................................-0.3V to +6V RESET (open drain), RESET (open drain)................-0.3V to +6V BATT ON, RESET (push-pull), RESET IN,WDI.......................................................-0.3V to (V OUT + 0.3V)MR .............................................................-0.3V to (V CC + 0.3V)Input CurrentV CC Peak ............................................................................1A V CC Continuous............................................................250mA BATT Peak....................................................................250mA BATT Continuous............................................................40mAGND................................................................................75mA Output CurrentOUT................................Short-Circuit Protection for up to 10s RESET, RESET , BATT ON ..............................................20mA Continuous Power Dissipation (T A = +70°C)6-Pin SOT23 (derate 8.70mW/°C above +70°C) .........696mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX6361–MAX6364SOT23, Low-Power µP Supervisory Circuitswith Battery Backup_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)(V CC = +2.4V to +5.5V, V BATT = 3V, T A = -40°C to +85°C, reset not asserted. Typical values are at T A = +25°C, unless otherwise noted.) (Note 1)Note 1:All devices are 100% production tested at T A = +25°C. Limits over temperature are guaranteed by design.Note 2:V BATT can be 0 anytime or V CC can go down to 0 if V BATT is active (except at startup).M A X 6361–M A X 6364SOT23, Low-Power µP Supervisory Circuits with Battery Backup 4_______________________________________________________________________________________Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)1214161820SUPPLY CURRENT vs. TEMPERATURE(NO LOAD)TEMPERATURE (°C)S U P P L Y C U R R E N T (µA )-402040-2060800.20.60.40.81.01.2BATTERY SUPPLY CURRENT (BACKUP MODE) vs. TEMPERATURETEMPERATURE (°C)B A T T E R Y S U P P L Y C U R R E N T (µA )-402040-20060801432567BATTERY TO OUT ON-RESISTANCEvs. TEMPERATURETEMPERATURE (°C)B A T T T O O U T O N -R E S I S T A NC E (Ω)-402040-20608000.30.90.61.2V CC TO OUT ON-RESISTANCEvs. TEMPERATURETEMPERATURE (°C)V O U T T O O U T O N -R E S I S T A N C E (Ω)-402040-206080190195205200210RESET TIMEOUT PERIOD vs. TEMPERATUREM A X 6361 t o c 05TEMPERATURE (°C)R E S E T T I M E O U T P E R I O D (m s )-402040-206080301575604513512010590V CC TO RESET PROPAGATION DELAYvs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E LA Y (µs )-402040-2060802.03.02.55.04.54.03.5RESET THRESHOLD vs. TEMPERATURETEMPERATURE (°C)T H R E S H O L D (V )-402040-2060801.21.41.31.61.51.91.81.72.0-40-2020406080MAX6362WATCHDOG TIMEOUT PERIODvs. TEMPERATUREM A X 6361t o c 06aTEMPERATURE (°C)W A T C H D O G T I M E O U T P E R I O D (s )1100101k10kMAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVERESET THRESHOLD OVERDRIVE V TH - V CC (mV)M A X I M U M T R A N S I E N T D U R A T I O N (µs )400300350250200050150100MAX6361–MAX6364SOT23, Low-Power µP Supervisory Circuitswith Battery Backup1.2341.2351.236MAX6364RESET IN THRESHOLD vs. TEMPERATUREM A X 6361 t o c 10TEMPERATURE (°C)T H R E S H O L D (V )-402040-206080Typical Operating Characteristics (continued)(T A = +25°C, unless otherwise noted.)1.01.91.61.32.82.52.2MAX6364RESET IN TO RESET PROPAGATION DELAYvs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E L A Y (µs )-402040-206080Pin Description0321456789101234BATTERY SUPPLY CURRENT vs. SUPPLY VOLTAGEV CC (V)B A T T E R Y S U P P L YC U R R E N T (µA )M A X 6361–M A X 6364Detailed DescriptionThe Typical Operating Circuit shows a typical connection for the MAX6361–MAX6364 family. OUT powers the stat-ic random-access memory (SRAM). OUT is internally connected to V CC if V CC is greater than the reset thresh-old, or to the greater of V CC or V BATT when V CC is less than the reset threshold. OUT can supply up to 150mA from V CC . When V CC is higher than V BATT , the BATT ON (MAX6363) output is low. When V CC is lower than V BATT ,an internal MOSF ET connects the backup battery to OUT. The on-resistance of the MOSFET is a function of backup-battery voltage and is shown in the Battery to Out On-Resistance vs. Temperature graph in the Typical Operating Characteristics section.Backup-Battery SwitchoverIn a brownout or power failure, it may be necessary to preserve the contents of the RAM. With a backup bat-tery installed at BATT, the MAX6361–MAX6364 auto-matically switch the RAM to backup power when V CC falls. The MAX6363 has a BATT ON output that goes high when in battery-backup mode. These devices require two conditions before switching to battery-backup mode:1)V CC must be below the reset threshold.2)V CC must be below V BATT .Table 1 lists the status of the inputs and outputs in bat-tery-backup mode. The device will not power up if the only voltage source is on BATT. OUT will only power up from V CC at startup.Manual Reset Input (MAX6361 Only)Many µP-based products require manual reset capabili-ty, allowing the operator, a test technician, or external logic circuitry to initiate a reset. For the MAX6361, a logic low on MR asserts reset. Reset remains asserted while MR is low, and for a minimum of 150ms (t RP ) after it returns high. MR has an internal 20k Ωpull-up resistor to V CC . This input can be driven with TTL/CMOS logic lev-els or with open-drain/collector outputs. Connect a nor-mally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity.Watchdog Input (MAX6362 Only)The watchdog monitors µP activity through the input WDI. If the µP becomes inactive, the reset output is asserted in pulses. To use the watchdog function, con-nect WDI to a bus line or µP I/O line. A change of state(high to low or low to high) within the watchdog timeout period (t WD ) with a 100ns minimum pulse width clears the watchdog timer. If WDI remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and a reset pulse is triggered for the reset timeout period (t RP ). The internal watchdog timer clears whenever reset asserts or the WDI sees a rising or falling edge within the watchdog timeout period. If WDI remains in a high or low state for an extended period of time, a reset pulse asserts after every watchdog timeout period (t WD ) (Figure 1).Reset In (MAX6364 Only)RESET IN is compared to an internal 1.235V reference.If the voltage at RESET IN is less than 1.235V, reset is asserted. The RESET IN comparator may be used as an undervoltage detector to signal a failing power sup-ply. It can also be used as a secondary power-supply reset monitor.To program the reset threshold (V RTH ) of the secondary power supply, use the following equation (see Typical Operating Circuit ):where V REF = 1.235V. To simplify the resistor selection,choose a value for R2 and calculate R1:Since the input current at RESET IN is 25nA (max), large values (up to 1M Ω) can be used for R2 with no signifi-cant loss in accuracy. F or example, in the TypicalSOT23, Low-Power µP Supervisory Circuits with Battery Backup 6_______________________________________________________________________________________R R V V RTH REF 121 /=()−[]MAX6361–MAX6364SOT23, Low-Power µP Supervisory Circuitswith Battery Backup_______________________________________________________________________________________7Operating Circuit,the MAX6362 monitors two supply voltages. To monitor the secondary 5V logic or analog supply with a 4.60V nominal programmed reset thresh-old, choose R2 = 100k Ω, and calculate R1 = 273k Ω.Reset OutputA µP’s reset input starts the µP in a known state. The MAX6361–MAX6364 µP supervisory circuits assert a reset to prevent code-execution errors during power-up, power-down, and brownout conditions. RESET is guaranteed to be a logic low or high depending on the device chosen (see Ordering Information ). RESET or RESET asserts when V CC is below the reset threshold and for at least 150ms (t RP ) after V CC rises above the reset threshold. RESET or RESET also asserts when MR is low (MAX6361) and when RESET IN is less than 1.235V (MAX6364). The MAX6362 watchdog function will cause RESET (or RESET ) to assert in pulses follow-ing a watchdog timeout (Figure 1).Applications InformationOperation Without a BackupPower SourceThe MAX6361–MAX6364 were designed for battery-backed applications. If a backup battery is not used,connect V CC to OUT and connect BATT to GND.Replacing the Backup BatteryIf BATT is decoupled with a 0.1µF capacitor to ground,the backup power source can be removed while V CC remains valid without danger of triggering a reset pulse.The device does not enter battery-backup mode when V CC stays above the reset threshold voltage.Negative-Going V CC TransientsThese supervisors are relatively immune to short-dura-tion, negative-going V CC transients. Resetting the µPwhen V CC experiences only small glitches is usually not desirable.The Typical Operating Characteristics section shows a graph of Maximum Transient Duration vs. Reset Threshold Overdrive for which reset is not asserted.The graph was produced using negative-going V CC pulses, starting at V CC and ending below the reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a negative-going V CC transient can typically have without triggering a reset pulse. As the amplitude of the transient increases (i.e., goes further below the reset threshold), the maximum allowable pulse width decreases. Typically, a V CC transient that goes 100mV below the reset threshold and lasts for 30µs will not trigger a reset pulse.A 0.1µF bypass capacitor mounted close to the V CC pin provides additional transient immunity.Figure 1. MAX6362 Watchdog Timeout Period and Reset Active TimeM A X 6361–M A X 6364Watchdog Software Considerations(MAX6362 Only)To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at dif-ferent points in the program, rather than “pulsing” the watchdog input low-high-low. This technique avoids a “stuck” loop, in which the watchdog timer would contin-ue to be reset within the loop, keeping the watchdog from timing out. F igure 2 shows an example of a flow diagram where the I/O driving the WDI is set low at the beginning of the program, set high at the beginning of every subroutine or loop, then set low again when the program returns to the beginning. If the program should “hang” in any subroutine, the problem would quickly be corrected, since the I/O is continually set low and the watchdog timer is allowed to time out, trigger-ing a reset.SOT23, Low-Power µP Supervisory Circuits with Battery Backup 8_______________________________________________________________________________________Figure 2. Watchdog Flow DiagramMAX6361–MAX6364SOT23, Low-Power µP Supervisory Circuitswith Battery Backup_______________________________________________________________________________________9*Sample stock generally held on standard versions only. Contact factory for availability of nonstandard versions.Device Marking CodesSelector GuideM A X 6361–M A X 6364SOT23, Low-Power µP Supervisory Circuits with Battery Backup 10______________________________________________________________________________________Pin Configurations (continued)Typical Operating CircuitChip InformationTRANSISTOR COUNT: 720MAX6361–MAX6364SOT23, Low-Power µP Supervisory Circuits with Battery Backup______________________________________________________________________________________11Package InformationM A X 6361–M A X 6364SOT23, Low-Power µP Supervisory Circuits with Battery BackupMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.12____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.NOTES。