ADL5382ACPZ-WP中文资料

700 MHz to 2.7 GHzQuadrature DemodulatorADL5382 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURESOperating RF and LO frequency: 700 MHz to 2.7 GHz Input IP333.5 dBm @ 900 MHz30.5 dBm @1900 MHzInput IP2: >70 dBm @ 900 MHzInput P1dB: 14.7 dBm @ 900 MHzNoise figure (NF)14.0 dB @ 900 MHz15.6 dB @ 1900 MHzVoltage conversion gain: ~4 dBQuadrature demodulation accuracyPhase accuracy: ~0.2°Amplitude balance: ~0.05 dBDemodulation bandwidth: ~370 MHzBaseband I/Q drive: 2 V p-p into 200 ΩSingle 5 V supplyAPPLICATIONSCellular W-CDMA/CDMA/CDMA2000/GSM Microwave point-to-(multi)point radios Broadband wireless and WiMAXFUNCTIONAL BLOCK DIAGRAMVPACOMBIASVPLVPLVPLVPBVPBQHIQLOIHIILO728-1Figure 1.GENERAL DESCRIPTIONThe ADL5382 is a broadband quadrature I-Q demodulator that covers an RF input frequency range from 700 MHz to 2.7 GHz. With a NF = 14 dB, IP1dB = 14.7 dBm, and IIP3 = 33.5 dBm at 900 MHz, the ADL5382 demodulator offers outstanding dynamic range suitable for the demanding infrastructure direct-conversion requirements. The differential RF inputs provide a well-behaved broadband input impedance of 50 Ω and are best driven from a 1:1 balun for optimum performance.Excellent demodulation accuracy is achieved with amplitude and phase balances ~0.05 dB and ~0.2°, respectively. The demodulated in-phase (I) and quadrature (Q) differential outputs are fully buffered and provide a voltage conversion gain of ~4 dB. The buffered baseband outputs are capable of driving a 2 V p-p differential signal into 200 Ω. The fully balanced design minimizes effects from second-order distortion. The leakage from the LO port to the RF port is<−65 dBc. Differential dc offsets at the I and Q outputs are typically <10 mV. Both of these factors contribute to the excellent IIP2 specifications which is >60 dBm.The ADL5382 operates off a single 4.75 V to 5.25 V supply. The supply current is adjustable with an external resistor from the BIAS pin to ground.The ADL5382 is fabricated using the Analog Devices, Inc., advanced Silicon-Germanium bipolar process and is available in a 24-lead exposed paddle LFCSP.ADL5382Rev. 0 | Page 2 of 28TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................5 ESD Caution..................................................................................5 Pin Configuration and Function Descriptions.............................6 Typical Performance Characteristics.............................................7 Distributions for f RF = 900 MHz...............................................10 Distributions for f RF = 1900 MHz.............................................11 Distributions for f RF = 2700 MHz.............................................12 Circuit Description.........................................................................13 LO Interface.................................................................................13 V-to-I Converter.........................................................................13 Mixers..........................................................................................13 Emitter Follower Buffers...........................................................13 Bias Circuit..................................................................................13 Applications Information..............................................................14 Basic Connections......................................................................14 Power Supply...............................................................................14 Local Oscillator (LO) Input......................................................14 RF Input.......................................................................................15 Baseband Outputs......................................................................15 Error V ector Magnitude (EVM) Performance...........................16 Low IF Image Rejection.............................................................17 Example Baseband Interface.....................................................17 Characterization Setups.................................................................21 Evaluation Board............................................................................23 Outline Dimensions.......................................................................27 Ordering Guide.. (27)REVISION HISTORY3/08—Revision 0: Initial VersionADL5382Rev. 0 | Page 3 of 28SPECIFICATIONSV S = 5 V , T A = 25°C, f LO = 900 MHz, f IF = 4.5 MHz, P LO = 0 dBm, BIAS pin open, Z O = 50 Ω, unless otherwise noted. Baseband outputs differentially loaded with 450 Ω. Loss of the balun used to drive the RF port was de-embedded from these measurements. Table 1.Parameter Condition Min Typ Max UnitOPERATING CONDITIONS LO and RF Frequency Range 0.7 2.7 GHz LO INPUT LOIP , LOIN Input Return Loss LO driven differentially through a balun at 900 MHz −11 dB LO Input Level −6 0 +6 dBm I/Q BASEBAND OUTPUTS QHI, QLO, IHI, ILO Voltage Conversion Gain 450 Ω differential load on I and Q outputs at 900 MHz 3.9 dB 200 Ω differential load on I and Q outputs at 900 MHz 3.0 dB Demodulation Bandwidth 1 V p-p signal, 3 dB bandwidth 370 MHz Quadrature Phase Error At 900 MHz 0.2 Degrees I/Q Amplitude Imbalance 0.05 dB Output DC Offset (Differential) 0 dBm LO input at 900 MHz ±5 mV Output Common Mode VPOS − 2.8 V 0.1 dB Gain Flatness 50 MHz Output Swing Differential 200 Ω load 2 V p-p Peak Output Current Each pin 12 mA POWER SUPPLIES VPA, VPL, VPB, VPXVoltage 4.75 5.25 V Current BIAS pin open 220 mA R BIAS = 4 kΩ 196 mA DYNAMIC PERFORMANCE at RF = 900 MHz Conversion Gain 3.9 dB Input P1dB 14.7 dBm Second-Order Input Intercept (IIP2) −5 dBm each input tone 73 dBm Third-Order Input Intercept (IIP3) −5 dBm each input tone 33.5 dBm LO to RF RFIN, RFIP terminated in 50 Ω −92 dBm RF to LO LOIN, LOIP terminated in 50 Ω −89 dBc IQ Magnitude Imbalance 0.05 dB IQ Phase Imbalance 0.2 Degrees LO to IQ RFIN, RFIP terminated in 50 Ω −43 dBm Noise Figure 14.0 dB Noise Figure under Blocking Conditions With a −5 dBm interferer 5 MHz away 19.9 dB DYNAMIC PERFORMANCE at RF = 1900 MHz Conversion Gain 3.9 dB Input P1dB 14.4 dBm Second-Order Input Intercept (IIP2) −5 dBm each input tone 65 dBm Third-Order Input Intercept (IIP3) −5 dBm each input tone 30.5 dBm LO to RF RFIN, RFIP terminated in 50 Ω −71 dBm RF to LO LOIN, LOIP terminated in 50 Ω −78 dBc IQ Magnitude Imbalance 0.05 dB IQ Phase Imbalance 0.2 Degrees LO to IQ RFIN, RFIP terminated in 50 Ω −41 dBm Noise Figure 15.6 dB Noise Figure under Blocking Conditions With a −5 dBm interferer 5 MHz away20.5 dBADL5382Rev. 0 | Page 4 of 28Parameter Condition Min Typ Max UnitDYNAMIC PERFORMANCE at RF = 2700 MHz RFIP , RFIN Conversion Gain 3.3 dB Input P1dB 14.5 dBm Second-Order Input Intercept (IIP2) −5 dBm each input tone 52 dBm Third-Order Input Intercept (IIP3) −5 dBm each input tone 28.3 dBm LO to RF RFIN, RFIP terminated in 50 Ω, 1xLO appearing at RF port −70 dBm RF to LO LOIN, LOIP terminated in 50 Ω −55 dBc IQ Magnitude Imbalance 0.16 dB IQ Phase Imbalance 0.1 Degrees LO to IQ RFIN, RFIP terminated in 50 Ω, 1xLO appearing at BB port −42 dBm Noise Figure 17.6 dBADL5382Rev. 0 | Page 5 of 28ABSOLUTE MAXIMUM RATINGSTable 2.Parameter RatingSupply Voltage (VPA, VPL, VPB, VPX) 5.5 VLO Input Power 13 dBm (re: 50 Ω)RF Input Power 15 dBm (re: 50 Ω)Internal Maximum Power Dissipation 1230 mWθJA54°C/W Maximum Junction Temperature150°COperating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONADL5382Rev. 0 | Page 6 of 28PIN CONFIGURATION AND FUNCTION DESCRIPTIONS124CMRF CMRF RFIP ADL5382TOP VIEW(Not to Scale)RFIN CMRF VPX CML VPA COM BIASVPL VPL VPL VPB VPB QHI QLO IHI ILO LOIP LOIN CML CML COM232221201978910111223456181716151********-002Figure 2. Pin ConfigurationTable 3. Pin Function DescriptionsPin No. MnemonicDescription1, 4 to 6,17 to 19VPA, VPL, VPB, VPX Supply. Positive supply for LO, IF, biasing, and baseband sections. These pins should be decoupled to the board ground using appropriate-sized capacitors. 2, 7, 10 to 12, 20, 23, 24COM, CML, CMRF Ground. Connect to a low impedance ground plane.3 BIAS Bias Control. A resistor (R BIAS ) can be connected between BIAS and COM to reduce the mixer core current. The default setting for this pin is open.8, 9 LOIP , LOIN Local Oscillator Input. Pins must be ac-coupled. A differential drive through a balun (recommended balun is the M/A-COM ETC1-1-13) is necessary to achieve optimal performance.13 to 16ILO, IHI, QLO, QHII Channel and Q Channel Mixer Baseband Outputs. These outputs have a 50 Ω differential output impedance (25 Ω per pin). The bias level on these pins is equal to VPOS − 2.8 V. Each output pair can swing 2 V p-p (differential) into a load of 200 Ω. Output 3 dB bandwidth is 370 MHz.21, 22 RFIN, RFIPRF Input. A single-ended 50 Ω signal can be applied to the RF inputs through a 1:1 balun (recommended balun is the M/A-COM ETC1-1-13). Ground-referenced inductors must also be connected to RFIP and RFIN (recommended values = 33 nH).EPExposed Paddle. Connect to a low impedance thermal and electrical ground plane.ADL5382Rev. 0 | Page 7 of 28TYPICAL PERFORMANCE CHARACTERISTICSV S = 5 V , T A = 25°C, LO drive level = 0 dBm, R BIAS = open, RF input balun loss is de-embedded, unless otherwise noted.07208-003RF FREQUENCY (MHz)G A I N (d B ), I P 1d B (d B m )Figure 3. Conversion Gain and Input IP1 dB Compression Point (IP1dB) vs.RF Frequency102030405060708070090011001300150017001900210023002500270007208-004RF FREQUENCY (MHz)I I P 3, I I P 2 (d B m )Figure 4. Input Third-Order Intercept (IIP3) andInput Second-Order Intercept Point (IIP2) vs. RF Frequency–2.0–1.5–1.00–0.50.51.01.52.070090011001300150017001900210023002500270007208-005RF FREQUENCY (MHz)G A I N M I S M A T C H (d B )Figure 5. IQ Gain Mismatch vs. RF Frequency–8–7–6–5–4–3–2–101210100100007208-006BASEBAND FREQUENCY (MHz)B A S E B A N D R E S P O N S E (d B)Figure 6. Normalized IQ Baseband Frequency Response121314151617181970090011001300150017001900210023002500270007208-007RF FREQUENCY (MHz)N O I S E F I G U R E (d B )Figure 7. Noise Figure vs. RF Frequency–4–3–2–107208-008RF FREQUENCY (MHz)Q U A D R A T U R E P H A S E E R R O R (D e g r e e s )Figure 8. IQ Quadrature Phase Error vs. RF FrequencyADL5382Rev. 0 | Page 8 of 28101520–6–5–4–3–2–101234562035506580I I P 3, I I P 2 (d B m )07208-009LO LEVEL (dBm)G A I N (d B ), I P 1d B (d B m ), N O I S E F I G U R E (d B )Figure 9. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.LO Level, f RF = 900 MHz10141822263034110100S U P P L Y C U R R E N T (m A )07208-010R BIAS (k Ω)I I P 3 (d B m ) A N D N O I S E F I G U R E (d B )Figure 10. IIP3, Noise Figure, and Supply Current vs. R BIAS , f RF = 900 MHz131517192123252729–30–25–20–15–10–50507208-011RF BLOCKER INPUT POWER (dBm)N O I S E F I G U R E (d B )Figure 11. Noise Figure vs. Input Blocker Level, f RF = 900 MHz, 1900 MHz(RF Blocker 5 MHz Offset) 24681012141618020–6–5–4–3–2–10123456I I P 3, I I P 2 (d B m )07208-012LO LEVEL (dBm)G A I N (d B ), I P 1d B (d B m ), N O I S E F I G U R E (d B )Figure 12. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.LO Level, f RF = 1900 MHz812162024283207208-013R BIAS (k Ω)I I P 3 (d B m ) A N D N O I S E F I G U R E (d B)Figure 13. IIP3 and Noise Figure vs. R BIAS , f RF = 1900 MHz11007208-014R BIAS (k Ω)G A I N (d B ), I P 1d B (d B m ),I I P 2 I A N D Q C H A N N E L (d B m )1001020304050607080Figure 14. Conversion Gain, IP1dB, IIP2_I, and IIP2_Q vs.R BIAS , f RF = 900 MHz, 1900MHzADL5382Rev. 0 | Page 9 of 28I I P 2, I A N D Q C H A N N E L S (d B m )07208-015BASEBAND FREQUENCY (MHz)I P 1d B , I I P 3 (d B m )5101520253035401020304050Figure 15. IP1dB, IIP3, and IIP2 vs. Baseband Frequency–80–70–60–50–40–30–20–10070090011001300150017001900210023002500270007208-016LO FREQUENCY (MHz)L E A K A G E (d B m )Figure 16. LO-to-BB Leakage vs. LO Frequency–50–45–40–35–30–25–20–15–10–5070090011001300150017001900210023002500270007208-017RF FREQUENCY (MHz)R E T U R N L O S S (d B )Figure 17. RF Port Return Loss vs. RF Frequency Measured on a CharacterizationBoard through an ETC1-1-13 Balun with 33 nH Bias Inductors –100–90–80–70–60–50–40–30–2070090011001300150017001900210023002500270007208-018LO FREQUENCY (MHz)L E A K A G E (d B m )Figure 18. LO-to-RF Leakage vs. LO Frequency–100–90–80–70–60–50–40–30–2070090011001300150017001900210023002500270007208-019RF FREQUENCY (MHz)L E A K A G E (d B c )Figure 19. RF-to-LO Leakage vs. RF Frequency–30–25–20–15–10–570090011001300150017001900210023002500270007208-020LO FREQUENCY (MHz)R E T U R N L O S S (d B )Figure 20. LO Port Return Loss vs. LO Frequency Measured onCharacterization Board through an ETC1-1-13 BalunADL5382Rev. 0 | Page 10 of 28DISTRIBUTIONS FOR f RF = 900 MHz2040608010007208-021INPUT IP3 (dBm)P E R C E N T A G E (%)Figure 21. IIP3 Distributions, f RF = 900 MHz2040608010007208-022INPUT P1dB (dBm)P E R C E N T A G E (%)Figure 22. IP1dB Distributions, f RF = 900 MHz02040608010007208-023GAIN MISMATCH (dB)P E R C E N T A G E (%)Figure 23. IQ Gain Mismatch Distributions, f RF = 900 MHz02040608010007208-024INPUT IP2 (dBm)P E R C E N T A G E (%)Figure 24. IIP2 Distributions for I Channel and Q Channel, f RF = 900 MHz12.513.013.514.014.515.015.502040608010007208-025NOISE FIGURE (dB)P E R C E N T A G E (%)Figure 25. Noise Figure Distributions, f RF = 900 MHz–1.00–0.75–0.50–0.2500.250.500.75 1.0002040608010007208-026QUADRATURE PHASE ERROR (Degrees)P E R C E N T A G E (%)Figure 26. IQ Quadrature Phase Error Distributions, f RF = 900 MHzDISTRIBUTIONS FOR f RF = 1900 MHz02040608010007208-027INPUT IP3 (dBm)P E R C E N T A G E (%)Figure 27. IIP3 Distributions, f RF = 1900 MHz12131415161702040608010007208-028INPUT P1dB (dBm)P E R C E N T A G E (%)Figure 28. IP1dB Distributions, f RF = 1900 MHz–0.2–0.100.10.202040608010007208-029GAIN MISMATCH (dB)P E R C E N T A G E (%)Figure 29. IQ Gain Mismatch Distributions, f RF = 1900 MHz02040608010007208-030INPUT IP2 (dBm)P E R C E N T A G E (%)Figure 30. IIP2 Distributions for I Channel and Q Channel, f RF = 1900 MHz02040608010007208-031NOISE FIGURE (dB)P E R C E N T A G E (%)Figure 31. Noise Figure Distributions, f RF = 1900 MHz02040608010007208-032QUADRATURE PHASE ERROR (Degrees)P E R C E N T A G E (%)Figure 32. IQ Quadrature Phase Error Distributions, f RF = 1900 MHzDISTRIBUTIONS FOR f RF = 2700 MHz02040608010007208-033INPUT IP3 (dBm)P E R C E N T A G E (%)Figure 33. IIP3 Distributions, f RF = 2700 MHz02040608010007208-034INPUT P1dB (dBm)P E R C E N T A G E (%)Figure 34. IP1dB Distributions, f RF = 2700 MHz02040608010007208-035GAIN MISMATCH (dB)P E R C E N T A G E (%)Figure 35. IQ Gain Mismatch Distributions, f RF = 2700 MHz02040608010007208-036INPUT IP2 (dBm)P E R C E N TA G E (%)Figure 36. IIP2 Distributions for I Channel and Q Channel, f RF = 2700 MHz02040608010007208-037NOISE FIGURE (dB)P E R C E N T A G E (%)Figure 37. Noise Figure Distributions, f RF = 2700 MHz02040608010007208-038QUADRATURE PHASE ERROR (Degrees)P E R C E N T A G E (%)Figure 38. IQ Quadrature Phase Error Distributions, f RF = 2700 MHzCIRCUIT DESCRIPTIONThe ADL5382 can be divided into five sections: the local oscillator (LO) interface, the RF voltage-to-current (V-to-I) converter, the mixers, the differential emitter follower outputs, and the bias circuit. A detailed block diagram of the device is shown in Figure 39.RFIP RFIN07208-039Figure 39. Block DiagramThe LO interface generates two LO signals at 90° of phase difference to drive two mixers in quadrature. RF signals are converted into currents by the V-to-I converters that feed into the two mixers. The differential I and Q outputs of the mixers are buffered via emitter followers. Reference currents to each section are generated by the bias circuit. A detailed description of each section follows.LO INTERFACEThe LO interface consists of a polyphase quadrature splitter followed by a limiting amplifier. The LO input impedance is set by the polyphase, which splits the LO signal into two differential signals in quadrature. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal. For optimal performance, the LO inputs must be driven differentially. V-TO-I CONVERTERThe differential RF input signal is applied to a resistively degenerated common base stage, which converts the differential input voltage to output currents. The output currents thenmodulate the two half frequency LO carriers in the mixer stage.MIXERSThe ADL5382 has two double-balanced mixers: one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). These mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers.EMITTER FOLLOWER BUFFERSThe output emitter followers drive the differential I and Q signals off-chip. The output impedance is set by on-chip 25 Ω series resistors that yield a 50 Ω differential output impedance for each baseband port. The fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. For example, a 500 Ω differential load has 1 dB lower effective gain than a high (10 kΩ) differential load impedance.BIAS CIRCUITA band gap reference circuit generates the proportional-to-absolute temperature (PTAT) as well as temperature-independent reference currents used by different sections. The mixer current can be reduced via an external resistor between the BIAS pin and ground. When the BIAS pin is open, the mixer runs at maximum current and therefore the greatest dynamic range. The mixer current can be reduced by placing a resistance to ground; therefore, reducing overall power consumption, noise figure, and IIP3. The effect on each of these parameters is shown in Figure 10, Figure 13, and Figure 14.APPLICATIONS INFORMATIONBASIC CONNECTIONSFigure 41 shows the basic connections schematic for the ADL5382.POWER SUPPLYThe nominal voltage supply for the ADL5382 is 5 V and is applied to the VPA, VPB, VPL, and VPX pins. Ground should be connected to the COM, CML, and CMRF pins. The exposed paddle on the underside of the package should also be soldered to a low thermal and electrical impedance ground plane. If the ground plane spans multiple layers on the circuit board, these layers should be stitched together with nine vias under the exposed paddle. The Application Note AN-772 discusses the thermal and electrical grounding of the LFCSP in detail. Each of the supply pins should be decoupled using two capacitors; recommended capacitor values are 100 pF and 0.1 μF .LOCAL OSCILLATOR (LO) INPUTFor optimum performance, the LO port should be driven differentially through a balun. The recommended balun isthe M/A-COM ETC1-1-13. The LO inputs to the device should be ac-coupled with 1000 pF capacitors. The LO port is designed for a broadband 50 Ω match from 700 MHz to 2.7 GHz. The LO return loss can be seen in Figure 20. Figure 40 shows the LO input configuration.07208-040Figure 40. Differential LO DriveThe recommended LO drive level is between −6 dBm and +6 dBm. The applied LO frequency range is between 700 MHz and 2.7 GHz.0.1µFV POSV POS07208-041Figure 41. Basic Connections SchematicRF INPUTThe RF inputs have a differential input impedance ofapproximately 50 Ω. For optimum performance, the RF port should be driven differentially through a balun. The recommended balun is the M/A-COM ETC1-1-13. The RF inputs to the device should be ac-coupled with 1000 pF capacitors. Ground-referenced choke inductors must also be connected to RFIP and RFIN (the recommended value is 33 nH, Coilcraft 0603CS-33NX) for appropriate biasing. Several important aspects must be taken into account when selecting an appropriate choke inductor for this application. First, the inductor must be able to handle the approximately 40 mA of standing dc current being delivered from each of the RF input pins (RFIP , RFIN). The suggested 0603 inductor has a 600 mA current rating. The purpose of the choke inductors is to provide a very low resistance dc path to ground and high ac impedance at the RF frequency so as not to affect the RF input impedance. A choke inductor that has a self-resonant frequency greater than the RF input frequency ensures that the choke is still looking inductive and therefore has a more predictable ac impedance (jωL) at the RF frequency. Figure 42 shows the RF input configuration.07208-042Figure 42. RF InputThe differential RF port return loss is characterized as shown in Figure 43.–10–12–14–16–18–20–22–240.70.9 1.1 1.5 1.71.3 1.9 2.1 2.3 2.5 2.7 2.9S 11 (d B )FREQUENCY (GHz)07208-043Figure 43. Differential RF Port Return LossBASEBAND OUTPUTSThe baseband outputs QHI, QLO, IHI, and ILO are fixed impedance ports. Each baseband pair has a 50 Ω differential output impedance. The outputs can be presented with differential loads as low as 200 Ω (with some degradation in gain) or high impedance differential loads (500 Ω or greater impedance yields the same excellent linearity) that is typical of an ADC. The TCM9-1 9:1 balun converts the differential IF output to single-ended. When loaded with 50 Ω, this balun presents a 450 Ω load to the device. The typical maximum linear voltage swing for these outputs is 2 V p-p differential. The bias level on these pins is equal to VPOS − 2.8 V . The output 3 dB bandwidth is 370 MHz. Figure 44 shows the baseband output configuration.QHIQLOIHIILOQHI QLO IHI ILO 07208-044Figure 44. Baseband Output ConfigurationERROR VECTOR MAGNITUDE (EVM) PERFORMANCEEVM is a measure used to quantify the performance of a digital radio transmitter or receiver. A signal received by a receiver would have all constellation points at the ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from the ideal locations. The ADL5382 shows excellent EVM performance for various modulation schemes. Figure 45 shows the EVM performance of the ADL5382 with a 16 QAM, 200 kHz low IF.–50–45–40–35–30–25–20–15–10–50–65–85–75–55–45–35–25–15–507208-045RF INPUT POWER (dBm)E V M (d B )Figure 45. EVM, RF = 900 MHz, IF = 200 kHz vs. RF Input Power for a 16 QAM 160 ksym/s SignalFigure 46 shows the zero-IF EVM performance of a 10 MHz IEEE 802.16e WiMAX signal through the ADL5382. Thedifferential dc offsets on the ADL5382 are in the order of a few millivolts. However, ac coupling the baseband outputs with 10 μF capacitors eliminates dc offsets and enhances EVM performance. With a 10 MHz BW signal, 10 μF ac coupling capacitors with the 500 Ω differential load results in a high-pass corner frequency of ~64 Hz, which absorbs an insignificant amount of modulated signal energy from the baseband signal. By using ac-coupling capacitors at the baseband outputs, the dc offset effects, which can limit dynamic range at low input power levels, can be eliminated. –50–45–40–35–30–25–20–15–10–50–65–60–55–50–45–40–35–30–25–20–15–10–551007208-046RF INPUT POWER (dBm)E V M (d B )Figure 46. EVM, RF = 2.6 GHz, IF = 0 Hz vs. RF Input Power for a 16 QAM 10 MHz Bandwidth Mobile WiMAX Signal (AC-Coupled Baseband Outputs)Figure 47 exhibits multiple W-CDMA low-IF EVMperformance curves over a wide RF input power range into the ADL5382. In the case of zero-IF, the noise contribution by the vector signal analyzer becomes predominant at lower power levels, making it difficult to measure SNR accurately.–50–45–40–35–30–25–20–15–10–50–75–70–65–60–55–50–45–40–35–30–25–20–15–10–507208-047RF INPUT POWER (dBm)E V M (d B )Figure 47. EVM, RF = 1900 MHz, IF = 0 Hz, 2.5 MHz, 5 MHz, and 7.5 MHz vs. RFInput Power for a W-CDMA Signal (AC-Coupled Baseband Outputs)LO IFIF07208-048Figure 48. Illustration of the Image ProblemLOW IF IMAGE REJECTIONThe image rejection ratio is the ratio of the intermediate frequency (IF) signal level produced by the desired input frequency to that produced by the image frequency. The image rejection ratio is expressed in decibels. Appropriate image rejection is critical because the image power can be much higher than that of the desired signal, thereby plaguing the down conversion process. Figure 48 illustrates the image problem. If the upper sideband (lower sideband) is the desired band, a 90° shift to the Q channel (I channel) cancels the image at the lower sideband (upper sideband). Phase and gain balance between I and Q channels are critical for high levels of image rejection.Figure 49 shows the excellent image rejection capabilities of the ADL5382 for low IF applications, such as W-CDMA. The ADL5382 exhibits image rejection greater than 45 dB over abroad frequency range.70090011001300150017001900210023002500270001020304050607007208-049RF FREQUENCY (MHz)I M A G E R E J E C T I O N (d B )Figure 49. Image Rejection vs. RF Frequency for a W-CDMA Signal,IF = 2.5 MHz, 5 MHz, and 7.5 MHzEXAMPLE BASEBAND INTERFACEIn most direct conversion receiver designs, it is desirable to select a wanted carrier within a specified band. The desired channel can be demodulated by tuning the LO to the appropriate carrier frequency. If the desired RF band contains multiple carriers of interest, the adjacent carriers would also be down converted to a lower IF frequency. These adjacent carriers can be problematic if they are large relative to the wanted carrier as they can overdrive the baseband signal detection circuitry. As a result, it is often necessary to insert a filter to provide sufficient rejection of the adjacent carriers.It is necessary to consider the overall source and load impedance presented by the ADL5382 and ADC input to design the filter network. The differential baseband output impedance of the ADL5382 is 50 Ω. The ADL5382 is designed to drive a high impedance ADC input. It may be desirable to terminate the ADC input down to lower impedance by using a terminating resistor, such as 500 Ω. The terminating resistor helps to better define the input impedance at the ADC input at the cost of a slightly reduced gain (see the Circuit Description section for details on the emitter-follower output loading effects). The order and type of filter network depends on the desired high frequency rejection required, pass-band ripple, and group delay. Filter design tables provide outlines for various filter types and orders, illustrating the normalized inductor and capacitor values for a 1 Hz cutoff frequency and 1 Ω load. After scaling the normalized prototype element values by the actual desired cut-off frequency and load impedance, the series reactance elements are halved to realize the final balanced filter network component values.。