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AT89S52单片机应用中英文翻译

本科毕业设计（论文）AT89S52单片机应用中英文翻译专业名称：电气工程及其自动化年级班级：学生姓名：指导老师：二O一二年六月九日AT89S52 MCU ApplicationsFunction Characteristic DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin DescriptionVCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that areexternally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during eachaccess to exter-nal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data. Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #data. Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information o n the timers’ operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDFTimer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be heldactive long enough to allow the oscillator to restart and stabilize.Idle ModIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.AT89S52单片机应用功能特征描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

毕设外文翻译--单片机基础

毕设外文翻译--单片机基础毕业设计(论文)外文资料翻译系别: 电气系专业: 电气工程及其自动化班级:姓名:学号:外文出处: Atomation Professional English Course(用外文写) Pressed By Machinery Industry Press附件:1、外文原文;2、外文资料翻译译文。

指导教师评语:签字:年月日注:请将该封面与附件装订成册。

1、外文原文(复印件)A: Fundamentals of Single-chip MicrocomputerThe single-chip microcomputer is the culmination of both the development of the digital computer and the integrated circuit arguably the tow most significant inventions of the 20th century [1].These tow types of architecture are found in single-chip microcomputer. Some employ the split program/data memory of the Harvard architecture, shown in Fig.3-5A-1, others follow the philosophy, widely adapted for general-purpose computers and microprocessors, of making nological distinction between program and data memory as in the Princeton architecture, shown in Fig.3-5A-2.In general terms a single-chip microcomputer is characterized by the incorporation of all the units of a computer into a single device, as shown in Fig3-5A-3.ProgramInput& memoryOutputCPU unitDatamemoryFig.3-5A-1 A Harvard typeInput&Output CPU memoryunitFig.3-5A-2. A conventional Princeton computerExternal Timer/ System Timing Counter clock componentsSerial I/OReset ROMPrarallelI/OInterrupts RAMCPUPowerFig3-5A-3. Principal features of a microcomputerRead only memory (ROM).ROM is usually for the permanent,non-volatile storage of an applications program .Many microcomputers and microcontrollers are intended for high-volume applications and hence the economical manufacture of the devices requires that the contents of the program memory be committed permanently during the manufacture of chips . Clearly, this implies a rigorous approach to ROM code development since changes cannot be made after manufacture .This development process may involve emulation using a sophisticated development system with a hardware emulation capability as well as the use of powerful software tools.Some manufacturers provide additional ROM options by including in their range devices with (or intended for use with) user programmable memory. The simplest of these is usually device which can operate in a microprocessor mode by using some of the input/output lines as an address and data bus for accessing external memory. This type of device can behave functionally as the single chip microcomputer from which itis derived albeit with restricted I/O and a modified external circuit. The use of these ROMless devices is common even in production circuits where the volume doesnot justify the development costs of custom on-chip ROM[2];there can still be a significant saving in I/O and other chips compared to a conventional microprocessor based circuit. More exact replacement for ROM devices can be obtained in the form of variants with 'piggy-back'EPROM(Erasable programmable ROM )sockets or devices with EPROM insteadof ROM 。

单片机毕业设计--英文翻译

附录一：中文翻译单片机的组成单片机要自动完成计算，它应该具有哪些最重要的部分呢？我们以打算盘为例计算一道算术题。

例：36＋163×156－166÷34。

现在要进行运算，首先需要一把算盘，其次是纸和笔。

我们把要计算的问题记录下来，然后第一步先算163×156，把它与36相加的结果记在纸上，然后计算166÷34，再把它从上一次结果中减去，就得到最后的结果。

现在，我们用单片机来完成上述过程，显然，它首先要有代替算盘进行运算的部件，这就是“运算器”；其次，要有能起到纸和笔作用的器件，即能记忆原始题目、原始数据和中间结果，还要记住使单片机能自动进行运算而编制的各种命令。

这类器件就称为“存贮器”。

此外，还需要有能代替人作用的控制器，它能根据事先给定的命令发出各种控制信号，使整个计算过程能一步步地进行。

但是光有这三部分还不够，原始的数据与命令要输入，计算的结果要输出，都需要按先后顺序进行，有时还需等待。

如上例中，当在计算163×156时，数字36就不能同时进入运算器。

因此就需要在单片机上设置按控制器的命令进行动作的“门”，当运算器需要时，就让新数据进入。

或者，当运算器得到最后结果时，再将此结果输出，而中间结果不能随便“溜出”单片机。

这种对输入、输出数据进行一定管理的“门”电路在单片机中称为“口”（Port）。

在单片机中，基本上有三类信息在流动，一类是数据，即各种原始数据（如上例中的36、163等）、中间结果（如166÷34所得的商4、余数30等）、程序（命令的集合）等。

这样要由外部设备通过“口”进入单片机，再存放在存贮器中，在运算处理过程中，数据从存贮器读入运算器进行运算，运算的中间结果要存入存贮器中，或最后由运算器经“出入口”输出。

用户要单片机执行的各种命令（程序）也以数据的形式由存贮器送入控制器，由控制器解读（译码）后变为各种控制信号，以便执行如加、减、乘、除等功能的各种命令。

plc单片机毕业论文文献翻译中英文对照

外文翻译：The monolithic In order to prevent without authorization the visit or the copy monolithic integrated circuit machine in the procedure, the majority of monolithic integrated circuits all has the encryption to lock the localization or the encryption byte, by protects the internal procedure. If in programming time encrypts locks the localization to enable (locking), is unable with the ordinary programming directly reading in the monolithic integrated circuit the procedure, this is the so-called copy protection or says the fixed function. In fact, such protective measures are very frail, is very easily explained. The monolithic integrated circuit aggressor with the aid of the special purpose equipment or the self-made equipment, using the monolithic integrated circuit chip design in loophole or the software flaw, through the many kinds of technical method, may withdraw the essential information from the chip, gains in the monolithic integrated circuit the procedure. Therefore, has the newest technology extremely as electronic products project engineer which the essential understanding current monolithic integrated circuit attacks, achieves knows oneself and the other side, knows fairly well, can effectively prevent oneself spends the product which the massive moneys and the time laboriously designs the matter occurrence which is counterfeited by a others night between.monolithic integrated circuits attacks technology：At present, attacks the monolithic integrated circuit mainly to have four kind of technologies, respectively is:This technical usual use processor correspondence connection and in the use agreement, the encryption algorithm or these algorithm security loophole carries on the attack. The software attack obtains the success a case in point is to early A T M E L A the T 89 C series monolithic integrated circuit attack. The aggressor has used in this series monolithic integrated circuit cleaning operation succession design loophole, uses from arranges the procedure to lock the localization after the cleaning encryption, stops the next step of cleaning internal program memory data the operation, thus makes to add the dense monolithic integrated circuit not to turn the encryption monolithic integrated circuit, then use programming read-out internal procedure.This technology usually monitors the processor by the high time resolution when the normal operation all power sources and the connection connection simulation characteristic, and through monitors its electromagnetic radiation characteristic to implement the attack. Because the monolithic integrated circuit is an active electronic device, when it carries out the different instruction, the corresponding mains input consumption also correspondingly changes. Like this analyzes and examines these changes through the use special electronic surveying instrument and mathematics statistical method, then gains in the monolithic integrated circuit the specific essential information.the mistake has the technology This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may usefor to forbid the protection circuit work or to fortected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the ece the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is proxecution.This technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kind of attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may use for to forbid the protection circuit work or to force the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is protected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the execution.(4) probe technologyThis technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kindof attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.3 invasions attacks general process：The invasion attack first step uncovers the chip seal. Some two methods may achieve this goal: The first kind is dissolves the chip seal completely, the exposed metal segment. The second kind is only moves above the silicon nucleus plastic seal. The first method needs the chip to tests on the jig, with the aid of Taiwan to operate. The second method except needs to have the aggressor certain knowledge and Wants outside skill, but also needs individual wisdom and the patience, but operates relatively quite is convenient.Above the chip plastic may use the knife to open, around the chip epoxy resin may use the aqua fortis perish. The hot aqua fortis can dissolve the chip seal but not to be able to affect the chip and the segment. This process carries on generally under the extremely dry condition, because the water existence possibly can corrode already the aluminum wire connection which exposes.Then first uses the acetone in the supersonic pond to clean this chip by except the remaining nitric acid, then cleans with the clear water by and is dry except the salinity. Not the supersonic pond, jumps over generally this step. In this kind of situation, the chip surface can a little dirty, but not too affects the ultraviolet ray to the chip operation effect.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.If does not have the microscope, then uses the chip different partially exposes to the ultraviolet ray under and the observed result way carries on the simple search. When operation applies not the opaque slip of paper cover chipby to protect the program memory not by the ultraviolet ray cleaning. Will protect the melt silk to expose in the ultraviolet ray next 5 ~ 10 minutes can broken the protection position protective function, afterwards, will use the simple programming to be possible the direct readout program memory content.Regarding used the protective layer to protect E E P R O the M unit the monolithic integrated circuit to say that, the use ultraviolet ray repositioned the protection circuit is not feasible. Regarding this kind of type monolithic integrated circuit, uses the micro probe technology reading the memory content generally. Opens after the chip seal, puts in the chip under the microscope to be able very easy finding中文翻译单片机为了防止未经授权访问或拷贝单片机的机内程序，大部分单片机都带有加密锁定位或者加密字节，以保护片内程序。

毕业设计(论文)外文原文及译文

毕业设计（论文）外文原文及译文一、外文原文MCUA microcontroller (or MCU) is a computer-on-a-chip. It is a type of microcontroller emphasizing self-sufficiency and cost-effectiveness, in contrast to a general-purpose microprocessor (the kind used in a PC).With the development of technology and control systems in a wide range of applications, as well as equipment to small and intelligent development, as one of the single-chip high-tech for its small size, powerful, low cost, and other advantages of the use of flexible, show a strong vitality. It is generally better compared to the integrated circuit of anti-interference ability, the environmental temperature and humidity have better adaptability, can be stable under the conditions in the industrial. And single-chip widely used in a variety of instruments and meters, so that intelligent instrumentation and improves their measurement speed and measurement accuracy, to strengthen control functions. In short，with the advent of the information age, traditional single- chip inherent structural weaknesses, so that it show a lot of drawbacks. The speed, scale, performance indicators, such as users increasingly difficult to meet the needs of the development of single-chip chipset, upgrades are faced with new challenges.The Description of AT89S52The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes ofFlash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Features• Compatible with MCS-51® Products• 8K Bytes of In-System Programmable (ISP) Flash Memory– Endurance: 1000 Write/Erase Cycles• 4.0V to 5.5V Operating Range• Fully Static Operation: 0 Hz to 33 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Eight Interrupt Sources• Full Duplex UART Serial Channel• Low-power Idle and Power-down Modes• Interrupt Recovery from Power-down Mode• Watchdog Timer• Dual Data Pointer• Power-off FlagPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSENis activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersNote that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers:Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers areprovided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag:The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10.Each of these interrupt sources can be individually enabled or disabledby setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.二、译文单片机单片机即微型计算机，是把中央处理器、存储器、定时/计数器、输入输出接口都集成在一块集成电路芯片上的微型计算机。

STC89C52处理芯片——单片机类毕业设计外文翻译、中英文翻译

STC89C52处理芯片——单片机类毕业设计外文翻译、中英文翻译外文资料翻译STC89C52 processing chip Prime features: With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number pointer, power identifier. Efficacy: characteristics STC89C52 is one kind of low power consumption, high CMOS8 bit micro-controller, 8K in system programmable Flash memory. Use high-density nonvolatile storage technology, and industrial 80C51 product instruction and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and online system programmable Flash, increase STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/counters, serial, continuous to work. Protection asana pattern, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices. Mouth: P0 P0 mouth is a two-way open drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impedance input. When access to external programs and numerical memory, also known as low P0 mouth eight address/numerical reuse. In this mode, with the internal P0 resistor. In the flash when programming, also used for P0 mouth; absorb instruction bytes In the process, the output command byte calibration. When the program requires external, calibration on pull-up resistors. Mouth: P1 mouth P1 is an internal resistance of the eight two-way I/O buffers can drive, P1 output four TTL logic level. To write "1" P1 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). In addition, P1.0 and P1.2 respectively timer/counter 2 external counting input (P1.0 / T2) and when the trigger editor/counter P1.1 input (2), specific T2EX/are shown below. In programming and calibration, flash P1mouth absorb eight address low byte. Efficacy: the foot. P1.0 T2 (timer/counter T2 external counting input), clock output P1.1 T2EX (timer/counter T2 capture/overloaded triggered signals and direction control), P1.5 MOSI (with) online system programming, P1.6 MISO (with) online system programming, P1.7 SCK (with) online system programming, Mouth: P2 P2 mouth is an internal resistance of the eight two-way I/O buffers and P2 output can drive four TTL logic level. To write "1" P2 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). In the external program memory access or use 16bit external numerical memory address read (for example MOVX execution DPTR @), P2 mouth send out high 8 address. In this application, P2 mouth on the internal use strong pull send 1. In using 8-bit address (such as MOVX @ RI) access to external numerical memory, P2 mouth output P2 latches content. In programming and calibration, flash P2 mouth also absorb high eight address byte and some control signal. P3: a P3 mouth on the inside of the eight two-way pull-up resistors I/O buffers can drive, p2 output four TTL logic level. For P3 port to write "1", the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). P3 mouth AT89S52 special functions (also as the second efficacy), are shown below. In programming and calibration, flash also absorb some P3 mouth controlsignals. Port pin second efficacy: P3.0 RXD (serial input) P3.1 TXD (serial export), P3.2 INTO the discontinuous (0) P3.3 INT1 (1) the discontinuous P3.4 (time/counter TO 0) P3.5 T1 (1) time/counter, P3.6 WR (external numerical memory write for) P3.7 RD (external numerical memory read for) In addition, also absorb some used in mp3 mouth FLASH memory programming and calibration of program control signals. RST, reset input: when the vibrator, RST pin appeared two machine cycle above high level will be reset the chip. ALE/PROG - when access to external program memory or numerical memory, ALE (address latch allow) output pulses are used to latch address of low eight bytes. Normally, ALE with clock frequencies are 1/6 output pulse si。

单片机书英译汉

本科生毕业设计（翻译）Chapter2 Overview About MicrocontrollersA microcontroller is a single-chip device that contains memory for program information and data. It can perform the operation logic of programming a control process, reading inputs, manipulating and sending output; namely, it has build-in interfaces for input/output (I/O) as well as a central processing unit (CPU). Thus the microcontroller id often know as microcontroller unit (MCU) and the built-in interface capability is designed for connection with sensors, actuators and communications with other devices, and so on. In practice, a microcontroller chip has other chips in addition to itself. They are called support chips will be embedded into the microcontroller chip in the future, namely, become part of the microcontroller chip.Microcontrollers are one kind of microprocessors involved in the special direction-they are highly integrated and they remit the increased computing power. They are developed CPU chips with built-in memory and interface circuits. This results in the situation that more microcontrollers are sold than powerful microcomputers, because they are used in many machines, instruments, and consumer products.In this chapter an overview of microcontroller from many viewpoints, including internal organization, normal types, basic design structure, material-structure styles, operation process, working cycles, working conditions, memory types and software, is shortly described. Finally, as an example, a typical microcontroller single-chip of type 80C51 is sketched.2.1 Normal Configurations Of MicrocontrollersA single chip of microcontroller basically consists of the following internal function blocks.1. CPU playing a role as a brain and heart, under the control of whichsome necessary blocks are working.2. Energy management system receiving the externally provided energy from power supply and allocating them to the internal function blocks for their usages.3. Clock and timing system providing a clock signal with constant frequency, under the help of external oscillation system, for the operation process to hold the entire process in a synchronous state.4. Reset control system leading the operation logic back to the initial state or holding the operation logic at the initial state.5. Control logic memory storing the internal data programs or instructions which indicate the CPU how to guide the operation process.6. Variable area storing the internal data produced during the operation process.The most basic principle of internal configurations and connections are shown as Figure 2.1.The group of microcontrollers, normally called “single chips”,has various kinds. They have differences in volumes, forms, leg numbers, functions, characteristics, etc., and can be principally divided into three large classes called “embedded microcontrollers”, having their common essentiality, as well as their own special points in characters, structures, functions and application ranges. Some of them can replace each other by only adding a little development, but some of them have their own special advantages and disadvantages which can’t be found in othersEach class of microcontrollers mentioned above will be described shortly later.2.1.1 Embedded MicrocontrollerEmbedded microcontrollers cover a very wide range. Their common character is that a single chip contains almost all necessary functions such asdata storage, input and output interfaces designed for its independent work, thus, to drive an embedded microcontroller to start to work, a user only needs to supply an electrical power and a clock system to it.An embedded microcontroller can be a single chip based on a microprocessor criterion already set up, also can be a system set up by using a microcontroller criterion. So it can implement a lot of functions, for example, a single task in a single chip.An elementary role played by the embedded microcontrollers is supplying inexpensive programmable logical controllers and interfaces. Thus, they needn’t to have high degree completed functio ns, but they can implement very complex control combinations according to different requests.Generally the embedded microcontrollers have the following common characteristics:1. Holding a CPU (as mentioned above).2. Possess the reset (as mentioned above) capability.3. Possess the ability of internal clock timing (timing the operation logic by using internal clock).4. Having control memories and program input terminals.5. Having variable areas.6. Having I/O (input/output) pins.7. Having instruction cycle timer.The expended set based on the primary chip mentioned above can satisfy the basic requirements of a computer system, and all added functions listed below are realized through their I/O pins:Internally installed monitor/debug programs.1. The ability to program the internal control memories-this is implemented by using a directing control of a mainframe.2. The abilities of interrupt stimulated by different interrupt sources.3. I/O interface for analog and digital signals.4. Serial I/O (synchronous and asynchronous) interfaces.5. Parallel I/O interfaces.6. Interfaces for external memories.The characteristics listed above make the microcontrollers more flexible, easier to be used and able to realize many developing tasks which seems unable to realize.2.1.2 External Storage MicrocontrollerThe basic structure of external storage microcontrollers can be shown as Figure 2.2.A typical application of external storage microcontrollers is being used as a service device to fetch and temporarily store the data for the main memory. They rationally distribute and temporarily store a lot of data, and can work at a quite high speed than the embedded microcontrollers.Most external storage microcontrollers possess 16-bit or 32-bit channels. They have external memories for storing the operation programs. Their operations fully depend upon their external memories which include control memories and all variable memories required for the microcontrollers.The typical type of external storage microcontrollers is type 80188, made by Intel. The basic body of type 80188 is the type 8088 used in IBM PC and their compatible types. Based on 8088, some circuits are added to the chip to supply some typical functions implemented in application of microcontrollers.The purpose of developing the 80188 is to provide a set of integrated soft-shells for the users. The 80188 includes all required circuit functions provided for application technology development engineer.2.1.3 Digital Signal Processor (DSP)This is a kind of relatively new processors playing a role in sampling data from analog signals, and calculating out the corresponding values.DSP S and their arithmetic and logic units (ALU) operate at very high speed, so that real-time control can be realized, and they involve a variety of mathematic algorithm systems so that they are very welcome in high-level science and technology fields.DSP S are often used to eliminate noises for the equipments, such as the microphone in airplanes, or the signal processors in TV Centers, owing to their high speed and mathematic functions.The DSP algorithm development is a special science field, especially is an important branch of control theory requiring quite high-level mathematics, for example, the Fuzzy Logics, a non-classical mathematics, supporting computer system control.DSP S include multiplex kinds. All of them have the common features which can be found in embedded microcontrollers and external storage microcontrollers. DSP S share typically not used alone, but combined in a system organized by a center control devices such as microcontroller, or with the help of a interface connection element.DSP S are generally used to control the external digital hardware, or process input signal and structure output signal in the description form which consist of equations.2.2 Basic Design Structures Of MicrocontrollersThe microcontrollers belong to the large family of single chip digital processors, so the hardware and software structure class of the former equivalent to the later. Their software structures include RISC structure and CISC structure, and hardware structures include Princeton structure andHarvard structure.2.2.1 Basic Instruction Structures Of CISC And RISCCISC structure refers to a kind of structure of Complex Instruction Set Computer. RISC structure refers to a kind of Reduced Instruction Set Computer. The main difference between them consists in the instruction structures. In the following differentiations and comparisons between them are discussed.1. Operation speedUsually, the operation speed of RISC is higher than CISC, though some processors of CISC type are regarded as one of RISC-like type. Many processors of CISC type implement the operation code with higher speed than the processors of RISC type, or implement some higher level technologies, which the RISC type can not realize.2. Instruction storage and implementationIn CISC, usually a lot of instructions are stored in the processors, and implement different steps of a single operation, such as direct data fetching out or filling in, and symbol register test. Each operation to be implemented requires an instruction-combination arranged by the designer.In RISC, usually each instruction stored in the processor exists as a least unit basing on which the user himself designs the required operations; this isn’t done by the designer.For example ,a STACK process includes two operation sets, PUSH and POP. The PUSH operation set is implemented at the start of a interrupt process and consists of putting all related data, addresses and state symbols, orderly, to the stack registers where they will stay, POP operation is implemented after the interrupt process and consists of putting all related data, addresses and state symbols, in opposite order, from the stack register, where they stays. Implementing all operations in RISC processors mentioned aboverequire only two instructions: “take out data from register” and “put data into register”, but a lot of programming tasks done by the user, meanwhile, in CISC processors, two instructions are required for implementing all the same operation, POP and PUSH, which are designed and programmed by the designer and then supplied to the users as a product.Basic Hardware Structures: Harvard Structure and Princeton StructureThe Harvard and Princeton structure are two computer hardware structures established by the expert of Harvard University and Princeton University in 1970 to satisfy the public requirement, in order to suit the high operation speed and variations of environment conditions.The principle of Princeton structure is shown as in Figure2.3. In this structure a common memory is arrayed, in order to store the control program and the data structure, such as variables and stack. In this structure a memory interface is used to construct an arbitrary channel, directing to the memory space, for supporting the data transmission between the processor and the internal registers.The problem of Princeton structure is “bottle neck” effect which appears when data of many channels are taken out or put in within a short time, so that the data flow is resisted.In the Harvard structure, shown in Figure 2.4, there are flexible connections and interfaces among the processor, control memory, register space and stack, as a result, the “bottle neck” effect and the data resistance can be avoided, the advantage of Princeton structure often can be shown when a set of complex operation system is to be implement.2.3 Chip Technology Of PMOS、NMOS、BMOS And CMOSAlong with the development of manufacture, like all other electronic products, the microcomputers have been growing smaller and smaller, running faster an faster, consuming less and less power, and becomingcheaper and cheaper, primarily due to improvements in the manufacturing processes and technologies, especially in the material processing technologies. The “CMOS” logic technology, a currently widely used material processing technique for microcontrollers, has made a large contribution to provide the computer functions and electrical interfaces. This is primarily a “push-pull”technology combining a “PMOS” and“NMOS” transistor together shown in Figure 2.5. It consists in a CMOS inverter working as a “NOT” gate, where the PMOS transistor is conducted(or“on”) and the NMOS transistor is blocked(or “off”), when the input signal is a low voltage level. Namely, the transistor, playing the role as a “switch” at V CC will be “on”, supplying V CC to the signal output responding to an input signal held on low voltage level. Contrarily, when receiving a signa l “high”, the NMOS transistor will be turn on, pulling the output line to GROUND (marked as GND) to provide an output signal “low”. The full names of the three terms mentioned are given below.1. PMOS or NMOS-P- channel Metal Oxide Semiconductor. This material technology was earlier used in the microprocessor manufacture history for microcomputers of types PMOS and NMOS.2. BMOS-Bipolar Metal Oxide Semiconductor. This technology includes BINMOS (Bipolar NMOS) and BIPMOS.3. CMOS-Complementary Metal Oxide Semiconductor. In this logic technique advantages of two silicon crystal structure types are optimally developed in combination, as shown in Figure 2.5, so the microcomputers have the advantages such as low power consumption, micro value, high operation speed and large capacity.Getting into the chip technologies deeper and deeper, some important terms and problems, mentioned below, can be explained more and more clearly.1. Power consumption and working frequencyDuring a state transition mentioned above, the amount of current flowing through the transistor is very small. As the working frequency increase, the current flows more often in a given time period, so that the average current, namely power consumption of device, must go up.2. Sleep modeIn this working mode no input signal is received, or no operation reacts to any input signal, namely no gates are switching so that no current flows through the device, thus the power consumption falls nearly to zero.3. Signal switching pointBefore using any devices, it is important to check if the input signal switching point matches the input threshold level of the device. For CMOS devices this is, typically, 1.4 V to one-half of V CC, but it can be different from types.4. High-and low-voltage levelCMOS can interface directly with most positive logic technologies, where logic value“1”is represented by high-voltage level, and logic value“0”-by low. Thus, it is important to make sure that a high-voltage level can be differentiated from a low in all circumstances, i. e., a “high” input is always above the voltage-switching threshold level,2.4 Basic Operation Process Of MicrocontrollersThe most basic operation process of a microcontroller consists of the following steps shown as in Figure 2.6.1. Instruction fetching-The CPU takes out an instruction from one of the rooms of internal or external control memory, ROM, according to the address calculated in the last step and recognizes the contents of the instruction.2. Instruction number calculating-The instruction number calculator of the CPU calculates the instruction number, namely, adds 1 to the number calculated in the last step.3. Instruction implementing-The operation system controlled by CPU implements the operation under the guiding of the content of the instruction.4. Address calculating-The address calculator calculates the next address, namely, plus an address increment to the last calculated address.5. Repeating-Going back to step 1 and starting the next cycle.All steps of a process are controlled by the operating logical control system and synchronized by the timing system with the help of an internally or externally supported clock system.2.5 Cycles Running In MicrocontrollersUsually there are 5 concepts of cycles defined for describing the implementation process of a microcontroller: clock cycle, machine cycle, instruction cycle, taps cycle (P cycle) and state cycle (S cycle). A short description will be given for each one as fellows.Clock cycle is the least basic cycle, called cycle of clock pulse as well. This cycle is produced internally or externally by an oscillation circuit such as crystal oscillator system, driven by an internal electronic energy source circuit, and equals to a natural cycle of the oscillation element.Machine cycle means a time interval for implementing a basic operation step.Instruction cycle refers to needed time interval for implementing an instruction.Tap cycle, marked as “P”, refers to a time interval, which equals to N *(clock cycle), where N is an integer.State Cycle, marked as “S”, is defined as 1 clock cycle and equals to 2 Ps.C51. If a crystal element of working frequency, 1 MHz, is selected to be used in the clock system, then 1 clock cycle equals to 1 us, 1 machine cycle is defined as 12 clock cycles and equals to 12 us; 1 instruction cycle Equals to 1 or 2 machine cycle(s) depending on the instruction lengthand mode, and equals to 12 or 24 clock cycles, i.e. 12 or 24 us.2.6 Basic Working Conditions And Center Function BlocksThe basic hardware-conditions for normally running an essential microcontroller system, or called least microcontroller system, configured according the basic conditions, are shown in Figure 2.7 based on an example of 80C51 microcontroller chip. In the essential system each peripheral element and related circuit plays a role in insuring and protesting normal operation of the microcontroller.2.6.1 PowerVirtually all microcontrollers today are built by using CMOS technology. They require significantly less power than the older, but usually use batteries and relies on “super-capacitors” for safe operation during power outages, thus minimizing power consumption becomes important. There are three conditions to be considered.1. Intrinsic power-the power required only for running the microcontroller.2. I/O Drive Power-the power taken into account for the power consumption when the microcontroller is sinking the current from or raising the current to external I/O devices.3. Sleep/Standby power-the power used when the microcontroller stays in “sleep”/“standby” state and is waiting for a specific external event.Many chips have robust power handling circuitries to fit the wide variety of different applications and power sources, ranging from 1 V to 6V.Different terms can be used to describe powers of different devices (Figure 2.7 shown above), such as V CC or V DD:high level, usually ranging from +2 V TO +5 V, V SS or GND (Ground).When applying a microcontroller, an important problem to consider isprotesting the power supply input from the complex power environment disturbance. A practical and reliable resolution is to use a tantalum capacitor of about 0.1 uF installed between the V CC (V DD) and GND (like C2 and C3) to filter the high frequency part of the input voltage, so that the device can handle great I/O current transients without causing inadvertent resets or data corruption. C3is designed for avoiding inductance effect which often happens because of the disturbance of high frequency radio wave.2.6.2 ResetIn order to ensure a microcontroller to run at a valid power conditions, a reset system such as the one consists of C1,R1, and S1 shown in Figure 2.7, are usually set up at the chip connected with its RESET-leg. This enables the chip to have two functions: restart function and power on stay function, detailed as fellows.1. Restart functionThis function performs the following process:If the switch, S1, is turned on when the chip is running, the connection between V CC and RESET pin leads the current flowing from V CC to the pin, so that the pin holds on a higher level and the operation logic of the chip turns back to initial state, or say, the address pointer of operation logic turns to initial address. Through the manual turning on of S1, the operation logic can get out from the tangle, such as unlimited cycle caused by external disturbance.2. Power on delay functionThis function performs the following process:At the moment when the power supply is turned on, the charging of C1 through R1leads a current flowing from RESET leg to V CC, and set the RESET pin on the high level, so that a RESET process like the one mentioned above happens, and the initial state is held until the charging isfinished and the current disappears. This process can hold the operation logic delaying at initial state, until the power condition get into stable state.2.6.3 System Clock/OscillatorsWhen running, each operation step of a microcontroller must follow an accurate time order system based on an externally or internally provided stable pulse series with constant frequency like a clock. The system, providing such pulse series, called clock signal system, or simply-“clock”, consists in an oscillator circuit driven (shown in Figure 2.7, where C L is a crystal oscillator, C4 and C5 are load for holding the oscillator system stable) by an energy source which vibrates sympathetically with the circuit and provides energy for it.Most microcontrollers are designed to be able to run within wide frequency band: from 0 to 100 GHz, the practical value of which is determined by the selected frequency value of the crystal oscillator.Another methods used for providing clocks are “RC oscillator” and an arbitrary external circuit or element, which provides a stable clock signal series. The first one uses the characteristic rise/fall time of a RC network, thus, it is the cheapest one, but not accurate enough.Some microcontrollers have internal RC or “ring”oscillators without any external parts, usually enabled by a configuration register programmed with the control store.2.6.4 Level-And-Phase Converting ElementIn order to connect the microcontrollers(using CMOS communication protocol with the logical“0”:low level normally) with personal computer or other equipment(using RS-232 communication protocol with the logical“1”：-8~ -12 V，a nd logical“0”:+8~ +12V, normally), a potential-and-phase converting element is used to convert the serial signals of CMOS protocolsystem, coming from or going tip microcontrollers, into one of RS-232 protocol system, going to or coming from personal computer or other 232-type equipments(Figure 2.7,C V).2.6.5 Latch ElementWhen being used in parallel communication bus, the latch element (Figure 2.7, K C) functions as a relay station serving for address lines to hold the address data temporarily when the address lines work as data lines temporarily. This will be detailed in the following lessons.2.6.6 Timing Monitor Equipment (Watchdog)An external equipment or internal function block called Timing Monitor (Watchdog) is used for microcontroller. This element or function block can lead the operation process back to its initial state by implementing their counter and overflow signal if the operation system runs into unlimited repetition state or wrong path state accidentally, and disable this function by “clear up” signal sent by microcontroller, if it runs normally.The external and internal Watchdogs play the same role for causing a reset operation of the microcontroller. This is performed when the Watchdog is not updated within a predetermined time interval (usually from milliseconds to several seconds).Effective applications of a microcontroller are determined by its rational operation, and the later is based on the intelligent constitution of operations of all functional blocks built in the microcontroller. In the following the basic functional blocks of microcontrollers will be typically introduced.第二章微控制器的概述微控制器是一个用于存储程序信息和数据的单芯片器件。

单片机基础毕业设计外文翻译

本科生毕业设计（论文）外文翻译毕业设计题目：外文题目：Fundamentals of Single-chip Microcomputer 译文题目：单片机基础学院：信息科学与工程学院专业班级：电子信息工程0802班学生姓名：指导教师：外文原文Fundamentals of Single-chip MicrocomputerDr. Dobbs MacintoshJournalAbstractT h e s i n gl e-chi p m i c r o com pu t er i s t h e cul m i na t i on of bo t h t h e d e v el opm e nt o f t h e di gi t al c om p ut e r a nd t h e i nt e gra t e d c i r c ui t a rgu a b l y t h e t ow m o st s i gn i fi c ant i nv en t i on s of t h e 20t h ce n t u r y .T h es e t o w t yp e s o f a rc hi t e c t u r e a r e fo un d i n s i n gl e-c hi p m i c r o com pu t e r.S om e e m p l o y t h e s pl i t p ro gr a m/d at a m em o r y o f t h e H a r v a rd a r ch i t e ct u r e, s ho wn i n F i g.3-5A-1, ot h er s f o l l o w t he p hi l o so ph y,w i d e l y a d a p t ed f o r ge n e r al-pu rp os e com p ut e rs and m i c r op r oc e s s o rs,of m ak i n g n o l o gi c al di s t i nc t i on be t w ee n p ro gr a m a n d d at a m em o r y a s i n t h e P r i n c et on ar c hi t e ct u r e.In ge n e r a l t er m s a si n gl e-c hi p m i cro c om put e r i s c ha r ac t e ri z ed b y t h e i n co r po r at i o n o f al l t h e u ni t s o f a c om put e r i n t o a s i n gl e d e vi c e.Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory– Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 128 x 8-bit Internal RAM• 32 Programmable I/O Lines• Two 16-bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low-power Idle and Power-down ModesDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. Theon-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-orderaddress bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programmingand verification.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When theAT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes programexecution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsFigure 2. External Clock Drive ConfigurationPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erasedby using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.外文资料翻译译文单片机基础摘要：单片机是电脑和集成电路发展的巅峰，有据可查的是它们也是20世纪最意义的两大发明。

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附录一：中文翻译单片机的组成单片机要自动完成计算，它应该具有哪些最重要的部分呢？我们以打算盘为例计算一道算术题。

例：36＋163×156－166÷34。

现在要进行运算，首先需要一把算盘，其次是纸和笔。

这类器件就称为“存贮器”。

此外，还需要有能代替人作用的控制器，它能根据事先给定的命令发出各种控制信号，使整个计算过程能一步步地进行。

但是光有这三部分还不够，原始的数据与命令要输入，计算的结果要输出，都需要按先后顺序进行，有时还需等待。

如上例中，当在计算163×156时，数字36就不能同时进入运算器。

因此就需要在单片机上设置按控制器的命令进行动作的“门”，当运算器需要时，就让新数据进入。

或者，当运算器得到最后结果时，再将此结果输出，而中间结果不能随便“溜出”单片机。

这种对输入、输出数据进行一定管理的“门”电路在单片机中称为“口”（Port）。

所以，这一类信息就称为控制命令，即由控制器去控制运算器一步步地进行运算和处理，又控制存贮器的读（取出数据）和写（存入数据）等。

第三类信息是地址信息，其作用是告诉运算器和控制器在何处去取命令取数据，将结果存放到什么地方，通过哪个口输入和输出信息等。

存贮器又分为只读存贮器和读写存贮器两种，前者存放调试好的固定程序和常数，后者存放一些随时有可能变动的数据。

顾名思义，只读存贮器一旦将数据存入，就只能读出，不能更改（EPROM、E2PROM等类型的ROM可通过一定的方法来更改、写入数据——编者注）。

而读写存贮器可随时存入或读出数据。

实际上，人们往往把运算器和控制器合并称为中央处理单元——CPU。

单片机除了进行运算外，还要完成控制功能。

所以离不开计数和定时。

因此，在单片机中就设置有定时器兼计数器，其基本结构与本连载之（二）中的举例类似。

到这里为止，我们已经知道了单片机的基本组成，即单片机是由中央处理器（即CPU中的运算器和控制器）、只读存贮器（通常表示为ROM）、读写存贮器（又称随机存贮器通常表示为RAM）、输入/输出口（又分为并行口和串行口，表示为I/O口）等等组成。

实际上单片机里面还有一个时钟电路，使单片机在进行运算和控制时，都能有节奏地进行。

另外，还有所谓的“中断系统”，这个系统有“传达室”的作用，当单片机控制对象的参数到达某个需要加以干预的状态时，就可经此“传达室”通报给CPU，使CPU根据外部事态的轻重缓急来采取适当的应付措施。

现在，我们已经知道了单片机的组成，余下的问题是如何将它们的各部分连接成相互关联的整体呢？实际上，单片机内部有一条将它们连接起来的“纽带”，即所谓的“内部总线”。

此总线有如大城市的“干道”，而CPU、ROM、RAM、I/O 口、中断系统等就分布在此“总线”的两旁，并和它连通。

从而，一切指令、数据都可经内部总线传送，有如大城市内各种物品的传送都经过干道进行单片机指令系统与汇编语言程序前面已经讲述了单片机的几个主要组成部分，这些部分构成了单片机的硬件。

所谓硬件（Hardware），就是看得到，摸得到的实体。

但是，光有这样的硬件，还只是有了实现计算和控制功能的可能性。

单片机要真正地能进行计算和控制，还必须有软件（Software）的配合。

软件主要指的是各种程序。

只有将各种正确的程序“灌入”（存入）单片机，它才能有效地工作。

单片机所以能自动地进行运算和控制，正是由于人把实现计算和控制的步骤一步步地用命令的形式，即一条条指令（Instruction）预先存入到存贮器中，单片机在CPU的控制下，将指令一条条地取出来，并加以翻译和执行。

就以两个数相加这一简单的运算来说，当需要运算的数已存入存贮器后，还需要进行以下几步：第一步：把第一个数从它的存贮单元（Location）中取出来，送至运算器。

第二步：把第二个数从它所在的存贮单元中取出来，送至运算器；第三步：相加；第四步：把相加完的结果，送至存贮器中指定的单元。

所有这些取数、送数、相加、存数等等都是一种操作（Operation），我们把要求计算机执行的各种操作用命令的形式写下来，这就是指令。

但是怎样才能辨别和执行这些操作呢？这是在设计单片机时由设计人员赋予它的指令系统所决定的。

一条指令，对应着一种基本操作；单片机所能执行的全部指令，就是该单片机的指令系统（Iustruction Set），不同种类的单片机，其指令系统亦不同。

使用单片机时，事先应当把要解决的问题编成一系列指令。

这些指令必须是选定的单片机能识别和执行的指令。

单片机用户为解决自己的问题所编的指令程序，称为源程序（Source Program）。

指令通常分为操作码（Opcode）和操作数（Operand）两大部分。

操作码表示计算机执行什么操作，即指令的功能；操作数表示参加操作的数或操作数所在的地址（即操作数所存放的地方编号）。

因为单片机是一种可编程器件，只“认得”二进码（0、1）。

要单片机运作，单片机系统中的所有指令，都必须以二进制编码的形式来表示。

例如，在Intel公司的MCS－51系列单片机中，从存贮器中取出一数到CPU中的累加器（在运算器中，参与运算、存放运算结果的专用寄存器）的指令代码为74H，累加器内容加立即数的代码为24H，再加上立即数代码，累加器送数到内部RAM存贮器的代码为F6H～F7H等。

这些指令是用十六进制表示二进制的机器码。

MCS－51单片机的字长为8位，有时，要完成某些操作用一个字节尚不能充分表达。

所以，在指令系统中有单字节指令，也有多字节指令。

机器码是由一连串的0和1组成，没有明显的特征，不好记忆，不易理解，易出错。

所以，直接用它来编写程序十分困难。

因而，人们就用一些助记符（Mue monic）——通常是指令功能的英文缩写来代替操作码，如MCS－51中数的传送常用MOV （Move的缩写）、加法用Add(Addition的缩写）来作为助记符。

这样，每条指令有明显的动作特征，易于记忆和理解，也不容易出错。

用助记符来编写的程序称为汇编语言程序。

但是，助记符编写的程序便于人理解，可单片机却只认识二进制机器代码，因此，为了让单片机能“读懂”汇编语言程序必须再转换成由二进制机器码构成的程序，这种转换过程，就称为“汇编”。

汇编可借助于人工查表法来实现，也可借助PC机通过所谓“交叉汇编程序”来完成。

由机器码构成的用户程序一旦“进入”了单片机，再“启动”单片机，就可让它执行输入程序所规定的任务。

单片机8051的CPU由运算器和控制器组成。

一、运算器运算器以完成二进制的算术/逻辑运算部件ALU为核心，再加上暂存器TMP、累加器ACC、寄存器B、程序状态标志寄存器PSW及布尔处理器。

累加器ACC是一个八位寄存器，它是CPU中工作最频繁的寄存器。

在进行算术、逻辑运算时，累加器ACC往往在运算前暂存一个操作数（如被加数），而运算后又保存其结果（如代数和）。

寄存器B主要用于乘法和除法操作。

标志寄存器PSW也是一个八位寄存器，用来存放运算结果的一些特征，如有无进位、借位等。

其每位的具体含意如下所示。

PSW CY AC FO RS1 RS0 OV －P对用户来讲，最关心的是以下四位。

1 进位标志CY（PSW 7）。

它表示了运算是否有进位（或借位）。

如果操作结果在最高位有进位（加法）或者借位（减法），则该位为1，否则为0。

2 辅助进位标志AC。

又称半进位标志，它反映了两个八位数运算低四位是否有半进位，即低四位相加（或减）有否进位（或借位），如有则AC为1状态，否则为0。

3 溢出标志位OV。

MCS－51反映带符号数的运算结果是否有溢出，有溢出时，此位为1，否则为0。

4 奇偶标志P。

反映累加器ACC内容的奇偶性，如果ACC中的运算结果有偶数个1（如11001100B，其中有4个1），则P为0，否则，P=1。

PSW的其它位，将在以后再介绍。

由于PSW存放程序执行中的状态，故又叫程序状态字?运算器中还有一个按位（bit）进行逻辑运算的逻辑处理机（又称布尔处理机）。

其功能在介绍位指令时再说明。

二、控制器控制器是CPU的神经中枢，它包括定时控制逻辑电路、指令寄存器、译码器、地址指针DPTR及程序计数器PC、堆栈指针SP等。

这里程序计数器PC是由16位寄存器构成的计数器。

要单片机执行一个程序，就必须把该程序按顺序预先装入存储器ROM的某个区域。

单片机动作时应按顺序一条条取出指令来加以执行。

因此，必须有一个电路能找出指令所在的单元地址，该电路就是程序计数器PC。

当单片机开始执行程序时，给PC装入第一条指令所在地址，它每取出一条指令（如为多字节指令，则每取出一个指令字节），PC的内容就自动加1，以指向下一条指令的地址，使指令能顺序执行。

只有当程序遇到转移指令、子程序调用指令，或遇到中断时（后面将介绍），PC才转到所需要的地方去。

8051 CPU 碢C指定的地址，从ROM相应单元中取出指令字节放在指令寄存器中寄存，然后，指令寄存器中的指令代码被译码器译成各种形式的控制信号，这些信号与单片机时钟振荡器产生的时钟脉冲在定时与控制电路中相结合，形成按一定时间节拍变化的电平和时钟，即所谓控制信息，在CPU内部协调寄存器之间的数据传输、运算等操作。

三、存储器存储器是单片机的又一个重要组成部分，图6给出了一种存储容量为256个单元的存储器结构示意图。

其中每个存储单元对应一个地址，256个单元共有256个地址，用两位16进制数表示，即存储器的地址（00H～FFH）。

存储器中每个存储单元可存放一个八位二进制信息，通常用两位16进制数来表示，这就是存储器的内容。

存储器的存储单元地址和存储单元的内容是不同的两个概念，不能混淆。

一、程序存储器程序是控制计算机动作的一系列命令，单片机只认识由“0”和“1”代码构成的机器指令。