PICMG+2.16+Packet+Switch+Backplane
EVOC CPCI 详解
接入层
语音增值业务平台
北京市人民政府
CPCI产品客户关注参数
•了解客户的具体应用环境，为什么要用CPCI系统、用CPCI优势在哪里？ •根据客户的应用提供产品推荐，推荐时候尽量让客户选用我们标配产品； •产品主要关注点： •机箱尺寸、槽位数、板卡类型、插卡方式、背板总线要求、电源要求 •板卡类型、CPU参数、接口类型及其指标、是否需要载板硬盘 •整机环境要求：如温度、三防护要求、 •其它：由于我们提供的是平台，用户自己的板卡的一些特点也需要了解，涉及到兼容 性问题
传统PCI 64/66M位系统PCI总线 不可热插拔 金手指，两面接触连接器 直接插卡 系统管理不完善
CPCI PCI总线/H.110/千兆以太网 可热插拔，能冗余 针孔结构，插针全包围连接 前后插卡 通过IPMI完成对系统监控
CPCI规范简介：
标准名称（英文版） CompactPCI Specification CompactPCI Computer telephony Specification VME64x on CompactPCI PMC on CompactPCI Industry Pack on CompactPCI Keying of CompactPCI Boards and Backplanes CompactPCI Power Interface Specification CompactPCI System Management Specification CompactPCI Hot Swap Specification 6U Dual System Slot Specification PCI Telecom Mezzanine/Carrier Card Specification CompactPCI Packet Switching Backplane Specification CompactPCI MultiComputing Specification PICMG Specification Engineering Change Notice 2.0R3.0-002 EMBEDDED PCI-X SPECIFICATION (Epci-x) for System Host Boards and Backplanes Supporting Single or Dual PCI-X Busses PICMG Specification Engineering Change Notice ECN 2.9-1.0-001 Hot Swap Infrastructure Interface Specification StarFabric Specification Serial Mesh Backplane Specification Serial RapidIO Specification 2.12 R2.0 2.17 R1.0 2.20 R1.0 2.18 R1.0 2002.05.20 2002.05.20 2002.10.21 2004.06.18 1.2 R1.0 2002.01.14 版本号 2.0R3.0 2.5R1.0 2.2R1.0 2.3R1.0 2.4R1.0 2.10R1.0 2.11R1.0 2.9R1.0 2.1R2.0 2.7 R1.0 2.15 R1.0 2.16 R1.0 2.14 R1.0 1998.08.03 1999.10.01 1999.10.01 2000.02.02 2001.01.17 2001.03.23 2001.04.11 2001.09.05 2001.09.06 发布日期 1999.10.01 1998.04.03
PICMG ISA_PCI Passive Backplane Short Form
PICMG ISA / PCI Passive BackplaneThe PCI/ISA industrial PC standard allows integrators of passive-backplane systems based on PC architectures access to the performance of PCI-based peripheral co n-trollers, while maintaining compatibility between proce s-sor cards from multiple manufacturers and enabling co n-tinued use of existing ISA-based I/O. This is an overview of the standard and the thinking behind it.IntroductionThe development of PCs based on passive backplane technology has been driven by the needs of the industrial and Computer-Telephony Integration (CTI) markets.PC's designed for desktop use are based on motherboard architectures which fail to address a number of important requirements for industrial and CTI use.A motherboard structure is inflexible and may require the replacement of the entire motherboard in order to repair or to upgrade the system. This, in turn, results in long system downtime, which may be tolerable in a system used for office applications, but which is totally una c-ceptable in a system which controls the core processes on which a business depends.Many industrial and CTI applications require a large number of expansion slots for real-world I/O or speech cards. These are not available on motherboard-based PCs, while the overall construction of the motherboard and I/O expansion board system is not designed to cope with the environmental demands of many industrial a p-plications.A passive-backplane architecture solves these problems by completely dispensing with the motherboard. In a pa s-sive backplane PC, a system bus is used to interconnect a plug-in processor board and multiple plug-in add-on boards. This architecture makes rapid repair by board substitution possible and system upgrades and changes are greatly simplified, with minimum resulting system downtime. There is considerable scope for system expa n-sion, with up to 20 ISA slots available for I/O or speech cards. The rugged construction of a typical passive-backplane system provides reliable operation in an i n-dustrial environment.PCI - An opportunity and a problemWhile a passive backplane architecture solves the pro b-lems associated with the traditional motherboard arch i-tecture the rapidly increasing throughput of I/O systems presents new challenges. The data transfer requirements of fast disk sub-systems and high-speed networks are difficult to meet with an ISA or even a higher speed EISA I/O bus. At the same time, the Peripheral Comp o-nent Interconnect (PCI) has become a widely used el e-ment in high-volume personal computers and single-board computer designs. With a 32-bit data path and a bandwidth of up to 133 Mbytes/sec, PCI offers the throughput demanded by the latest I/O and storage devices.The PCI interface is processor independent, operating on its own clock rather than that of the processor devices. Computer boards based on X86, PowerPC and Alpha AXP processors use PCI as the local bus The Alpha AXP microprocessor and many peripheral I/O controllers are already available with integral PCI interface. The wid e-spread use of PCI brings economies of scale and resulting lower costs.The specification of a passive backplane PC architecture using PCI raises issues of vendor interoperability and standards. A passive-backplane system based solely on the ISA bus standard can simply adopt the ISA board format for the processor board, ensuring compatibility between plug-in SBCs and backplanes from multiple vendors. However, no suitable standard existed for an implementation which would support existing ISA I/O cards and allow the use of PCI for high-performance channels. Areas which required definition were:The mechanical form-factor of a plug-in single board computer. The mechanical form-factor of the passive backplane. The logical interface between the single board computer and the passive backplane. Backplane slot-specific si g nals and pin assignmentsIt was therefore necessary to generate a specification for the implementation of PCI on a passive backplane sy s-tem. In order to deliver the benefits of vendor interope r-ability and economies of scale, an open standard under the control of a independent specifying body was r e-quired. However, at the time no suitable group existed. The Solution - PICMG and the PCI/ISA Industrial StandardA group of industrial computer product vendors, with a long history of developing PC architecture products for industrial and embedded control, were aware of the n e-cessity for a configuration standard for PCI and joined forces. In May 1994 the PCI Industrial Computer Man u-facturers Group (PICMG) was established with the mi s-sion to define an industrial PCI/ISA passive backplane and CPU card interface specification . The PICMG tec h-nical committee generated a comprehensive specification for a passive backplane architecture to support both PCI and ISA I/O buses.The PCI/ISA industrial standard provides a broad-based open standard designed to maximize interoperability with other standards. Key objectives of the specification were:• To enable interoperability between plug-in single-board computers and passive backplanes from diffe r-ent manufacturers.• To ensure compatibility between passive backplanes built to the standard and off-the-shelf ISA and PCIadapters.• To allow older technology ISA based SBCs to work in the new PCI/ISA backplanes.• To allow an SBC with internal PCI bus to operate in an ISA-based system.• To cater for upgrade to 64-bit PCI.CPU/Backplane interfaceThe PCI/ISA industrial standard specifies the logical and mechanical interface between the CPU and the passive backplane. Instead of redesigning the entire edge co n-nector on the CPU card, the PICMG technical committee decided to use a physical board format and connector based on the ISA adapter specification and add a PCI connector below, and in line with, the ISA connector, allowing sufficient space for 32-bit or 64-bit PCI inte r-faces.The single-board computer can draw power from pins on the ISA connector and/or from pins on the PCI conne c-tor. This avoids the maximum power available to a CPU board being limited by the PCI local bus specification. The signals on the PCI interface have the same pin nu m-bers as a PCI expansion slot with the following additions: REQ# (3, 2, 1, 0)Request signals for each PCI slotGNT# (3, 2, 1, 0)Grant signals for each PCI slot CLKA Clock for slot 1 CLKB Clock for slot 2 CLKC Clock for slot 3 CLKD Clock for slot 4The adoption of a standard ISA adapter board and co n-nector format with additional PCI connector enables a two-stage approach to system upgrade. The first stage is to use a PCI-based single-board computer in an existing ISA passive-backplane system. This improves perfor m-ance thanks to the faster internal bus on the processor board. The second stage is to replace the backplane or system chassis with a PCI industrial standard passive backplane, when the additional performance will be e x-tended to the PCI expansion bus.PCI Expansion BusThe specification defines backplane signals for up to four PCI bus slots which can be implemented as masters or slaves. A master slot has the additional REQ and GNT signals which enable a card to acquire control of the bus for transmission of data without central CPU interve n-tion, making higher transfer speeds possible for SCSI controllers, fast Ethernet adapters and multi-media cards. Slave cards, such as modems, use the central CPU to move data. Some processor boards do not support masters in all four slots, since many PCI cards do not have a master capabi lity.Slot-specific signalsThe PCI specification includes slot-specific signals which allow a processor to select specific slots and read co n-figuration information during the boot process. This e n-ables the processor to determine the identity of the PCI board in each slot and to configure the system accor d-ingly, dispensing with the need for the system integrator to change jumpers or switches. The relationship between the select signals (IDSEL) and the allocation of the inte r-rupt signals on the backplane must be known to the CPU board BIOS. The PICMG specification requires a d-dress/data bit 31 (AD31) to be routed to IDSEL on slot 1 (the PCI slot next to the PCI/ISA processor slot) , AD30 to slot 2, AD29 to slot 3 and AD28 to slot 4. The pin assignment of REQ. GNT CLK and IDSEL signals for each PCI slot is shown in figure 3.Interrupt signal assignmentThe relationship between the IDSEL signals and inte r-rupt lines for each slot are defined as part of the PICMG specification. This enables the BIOS configuration pr o-gram to be standardized and takes full advantage of the four interrupt lines defined by the PCI specification. The layout used will facilitate the implementation of a PCI to PCI bridge on passive backplane systems. The interrupt signal assignment to each PCI slot is shown in figure 4. Implementation examplesPICMG members have designed families of dual arch i-tecture PCI/ISA systems which meet the PCI/ISA indu s-trial specification. These offer the system integrator the best of both worlds. The ISA bus offers full backwards compatibility with existing PC hardware and software while PCI provides the bandwidth necessary to take full advantage of the latest fast peripherals and high-speed networks. Backplanes with a dual-bus CPU connector, 1 to 4 PCI connectors and 6, to 15 ISA connectors are available.The dual-bus architecture has proved to be very popular for voice applications. The ISA bus provides full bac k-ward compatibility with existing ISA-based speech t e-lephony cards, while PCI provides access to the latest high-bandwidth disk I/O and networking sub-systems. Telephony systems based on traditional PC platforms often suffer from disk I/O bottlenecks, due to the limited capacity of the ISA bus with its 8 Mbytes/sec data rate and standard 10 Mbps Ethernet can reach saturation with just a few systems on the network. By elimination the bottlenecks inherent in traditional PC implementations of Voice systems, the new architecture can boost system throughput by an order of magnitude.。
IPS-1000系列VoIP综合接入系统用户手册V1.05
IPS-1000系列VoIP综合接入系统用户手册版本：V1.05目录1.前言 (1)2.概述 (2)3.系统指标 (3)3.1功能、性能 (3)3.2工作条件 (3)3.3配置 (4)4.结构 (5)4.1VIP板面板图 (5)4.2面板 (5)4.3出线 (6)4.4系列结构标准 (6)5.安装和操作 (7)5.1IPS设置简介 (7)5.2产品安装和呼叫 (7)5.3呼叫 (7)5.4IPS系列编程 (7)6.VIP设置命令（Telnet 远程配置） (8)6.1操作系统登录命令Telnet (8)6.2帮助命令Help (8)6.3显示配置命令Show (9)6.4设置配置命令Set (10)6.5存盘命令Save (10)6.6恢复前次配置命令Load (10)6.7恢复初始配置命令LoadDefault (10)6.8系统重起动命令Reboot (10)6.9退出命令配置Quit (11)7.配置数据 (12)7.1NetWork部分 (12)7.1.1广域网IP (12)7.1.2广域网IP子网掩码 (12)7.1.3广域网MAC值 (12)7.1.4广域网口DHCP模式 (12)7.1.5局域网IP (13)7.1.6局域网IP子网掩码 (13)7.1.7局域网MAC值 (13)7.1.8DNS状态 (13)7.1.9DNS IP (13)7.1.10默认网关IP (14)7.1.11NAT功能 (14)7.1.12NAT端口映射表 (14)7.1.13PPPoE (14)7.1.14PPPoE 用户名 ......................................... 147.1.15PPPoE 用户密码. (15)7.2GateWay部分 (15)7.2.1网关别名 (15)7.2.2网关IP (15)7.2.3网关区号 (15)7.2.4呼入前缀匹配值 (15)7.2.5呼入前缀删除状态 (16)7.2.6设备最大允许话音通道数 (16)7.2.7启用快速呼叫功能 (16)7.2.8Q.931协议端口值 (16)7.2.9RTP起始端口值 (16)7.2.10TCP起始端口值 (17)7.2.11MCC通信定时器 (17)7.2.12网守定时器 (17)7.2.13TCP定时器 (17)7.2.14ALERTING定时器 (17)7.2.15CONNECING定时器 (17)7.2.16RAS重发次数 (18)7.2.17网守状态 (18)7.2.18网守IP (18)7.2.19TUNNEL状态 (18)7.2.20网关路由表 (18)7.3CDR IP部分 (19)7.3.1中央维护台的IP (19)7.3.2普通维护台IP (19)7.3.3设置SNMP 管理站IP (19)7.4GateKeeper部分 (19)7.4.1网守最大支持呼叫数基本属性 (19)7.4.2内部网守状态 (20)7.4.3IRR消息频率 (20)7.4.4RRQ消息频率 (20)7.4.5RRQ消息超时次数 (20)7.4.6IRR消息超时次数 (20)7.4.7GKID (20)7.4.8网守信息表 (21)7.4.9DSP状态 (21)7.4.10语音编码类型 (21)7.4.11传真模式 (21)7.4.12语音包允许延迟时长 (22)7.4.13回声抵消状态 (22)7.4.14静音检测状态 (22)7.5SYSTEM部分 (22)7.5.1系统软件版本 (22)7.5.2T35国家码 (22)7.5.3T35扩展码 (22)7.5.4终端类别 (23)7.5.5产品ID号 (23)7.5.6设备厂家号 (23)7.5.7H.323协议栈版本 (23)7.5.8H.225协议栈版本 (23)7.5.9H.245协议栈版本 (23)7.6Dialedlen部分 (23)7.7IP ECHO部分 (24)7.7.1IPECHO客户端 (24)7.7.2客户机定时发送消息时间 (24)7.7.3服务器所在地址 (24)7.7.4服务器所在端口 (25)7.7.5是否作为服务器 (25)8.关于配置文件的存取 (26)8.1下载VIP配置文件至PC (26)8.2上传PC的配置文件至VIP中： (26)8.3用TFTP升级VIP系统软件 (26)9.维护注意事项 (27)9.1VIP板RUN灯长亮 (27)9.2IPS电话无法呼出 (27)图图5-1面板指示图 (5)表表5-1面板LED定义 (5)1.前言●本手册详细地介绍了IPS-1000系列V oIP综合接入系统（IPS-1016/1160/1240）的结构、工程安装说明、软件设置等，您也可以根据目录及页眉的标题进行选择性地阅读此手册。
ATCA基础知识
ATCA平台构成
ATCA平台构成 双星结构在ATCA机框内有两块交换单板，每 块交换单板与机框内其他的每一块单板都有 一条独立通道互连 双双星结构在机框内有四块交换单板，每块 交换单板与机框内其他的每一块单板都有一 条独立通道互连。
ATCA平台构成 全网状互连结构
机框内的每块单板与其他的每一块单板都有一条 独立的通道互连。 全网状互连结构不需要中心交换结构，每块单板 都可以做数据转发和数据处理。 全网状互连结构具有很大的灵活性，比较适合机 框槽位较少的系统。
ATCA与传统电信平台的比较 传统电信平台
建立在各家厂商封闭、专有的系统之上
软硬件模块互不兼容
ATCA与传统电信平台的比较
ATCA与传统电信平台的比较 ATCA架构 开放式、标准化、模块化的硬件平台架构 不同厂商的产品可以相互兼容
ATCA与传统电信平台的比较
ATCA与传统电信平台的比较
ATCA平台构成
ATCA平台构成 交换接口（Fabric Interface）
Fabric Interface是ATCA架构的业务平面的数据通道，为 ATCA单板提供高速数据传输 Fabric Interface提供以太网通道以供机框内单板互连 Fabric Interface的每个通道（Channel）由8对差分线（4对 接收、4对发送）构成，每两对差分线（1对接收，1对发 送）构成一个端口（Port） Fabric Interface支持ATCA架构的多种拓扑结构 Fabric Interface 支持多种传输协议（见ATCA辅助规范）
ATCA平台构成
IPMI：Intel、DELL、HP及NEC等公司共同提出的 开放标准的硬件管理接口规格，定义了嵌入式管理 子系统进行通信的特定标准
阿朗核心网设备-MPC CMS PSG
•Rouzic •) • OAM Server (
ALU 5400 ATCA
• MIF/Hub • MIF/Hub • MIF/Hub MIF/Hub MIF/Huard Computer (NBRZxx)
CPU
1 Dual-core Xeon @ 2.13GHz + E7520/ESB chipset, 32/64-bit, 4M L2 cache – 42 SpecInt Rate 2000 Up to 8GB memory (2x 4GB RDIMMs), 2 DIMMs sites, DDR2-400, ECC 2x GigE ports to host USB2.0 (bootable) RS-232 SAS HDD GigE connectivity to backplane Two different configurations Diskful Diskless
• • • •
ALU 5073 Signaling Gateway ALU 5073 Signaling Gateway
ATCA- V2 Chassis
2nd generation (“v2”) design 19” (482mm) wide, 14-slot Rack-mount, 11U Dedicated front slot for dual shelf manager Fully compliant with PICMG3.1 Dual Star Fabric backplane Update channels between even and old slots Front access fan trays and dust filters ETSI and NEBS level 3 certified
PICMG规范简介
李侃
2005年11月14日星期 一
1
内容大纲
PC总线的演进 PICMG 1.x PCI/ISA/PIC-X无源背板规范 PICMG 2.x CompactPCI规范 CompactPCI Express& PXI Express
2005年11月14日星期 一
2
工业计算机总线标准的发展趋势
VXI VME PXI 量测领域
CompactPCI ® ISA PICMG
现场应用 高可靠应用
2005年11月14日星期 一
3
工业计算机总线标准的发展趋势
PXI-Express
PCI-Express CompactPCI-Express
2005年11月14日星期 一
4
ISA Bus (Industrial Standard Architecture)
PCI-X Bus
2005年11月14日星期 一
PCI-X Bus
17
PICMG 1.2 规范比较
卡片尺寸 Size 340mm x 120mm = 61 in2 数据传输率 PCI-X = 64 bit x 133 MHz = 8 Gb/sec 卡片最大功率 50 Watts
PICMG 1.2 PICMG 1.0
5 排高密度针孔连接 + 2 排屏蔽
32-bit PCI 125 个信号
工业控制 军工领域 嵌入式控制
2005年11月14日星期 一
27
PICMG 2.0 规范比较
卡片尺寸 Size 6U x 180mm =57in2 数据传输率 64 bit x 133 MHz = 8Gb/sec 卡片最大功率消耗 50 Watts
CPCI测试规范10.8
研祥智能科技股份有限公司文件名称：CPCI测试规范编号：版本：页次：编写：审核：批准批准//日期：1.依据标准1.1.GB/T3047.2-1992高度进制为44.45mm（即1U）的面板、机架和机柜基本尺寸系列1.2.GB/T2822-1991标准尺寸1.3.CPCI相关规范PICMG 2.0R3.0:CompactPCI SpecificationPICMG 2.1R2.0:CompactPCI Hot Swap SpecificationPICMG 2.3R1.0:PMC on CompactPCIPICMG 2.5R1.0H.110:CompactPCI Computer telephony SpecificationPICMG 2.7R1.0:CompactPCI6U Dual System SlotPICMG 2.9R1.0:CompactPCI System Management SpecificationPICMG 2.10R1.0:Keying of CompactPCI Boards and BackplanesPICMG 2.11R1.0:CompactPCI Power Interface SpecificationPICMG 2.16R1.0:Packet Switching Backplane SpecificationIEEE1101.1标准的主板与主板间的位置关系2.CPCI主板测试：2.1.主板基本接口功能测试：具体参照具体接口对应的测试规范，如《USB接口测试规范》、《SATA接口测试规范》、《LAN接口测试规范》等。
2.2.CPCI基本规范测试：2.3.PICMG 2.1R2.0:CompactPCI Hot Swap Specification2.2.1.1热插拔操作步骤(主板烧录CPLD程式,运行主板热插拔软件)2.2.1.1.1CPCI卡热拔出时，先按下拉手条上的热插拔信号键后软件对话框提示有设备拔出，CPCI卡热插拔蓝色灯亮后,将CPCI卡拔出，要求系统正常运行且不能出现提示重启的对话框、或死机现象；在设备理器中CPCI卡的驱动可以卸载.2.2.1.1.2CPCI卡热插入过程时，热插拔蓝色灯亮后完全插入卡,软件对话框提示有设备插入，完全扣好接手条上的热插拔信号键,科技股份有限公司编号：版本：页次：要求系统正常运行且不能出现提示重启的对话框、或死机现象，驱动可以加载上,CPCI卡功能正常.2.2.1.2热插拔的技术要求2.2.1.2.1热替换：在X槽拔出CPCI卡，驱动自动卸载；在X槽插入CPCI卡,驱动自动加载.(没有热插拔软件时,需要在设备管理中”扫描检测硬件改动”),驱动加载后CPCI卡功能应正常。
ATCA - 新一代开放式架构通信平台
Alex Lee Director, Product Development CenterADLINK Technology Inc.alex.lee@•ATCA Applications•ADLINK ATCA Building Blocks2•ATCA Technology & Building Blocks•ATCA Applications•ADLINK ATCA Building Blocks3–Reduce time to market, time to revenue, time to volume, time to profit–Reduce development costs–Allow manufacturers of communications equipment to focus on their value add4them–Data transports required exceeded capability ofexisting architectures•Reduction in workforce in some parts of the world reduced the engineering pool available to solve the problem56CostFeaturesWhat to do?–Defines Chassis, Blade, Management•Service Availability Forum (SA Forum)–Application Interface and Hardware Platform interface specifications –Abstract the Application –Hardware layer•Open Source Development Lab (OSDL)–Carrier Grade LinuxTogether these standards offer the Building Blocksof next generation platforms78•ATCA Applications•ADLINK ATCA Building Blocks910l Data Transport Definition on Fabric ChannelPacket Routing Switch (PRS) for AdvancedTCA1112released January 2004–Adds shelf manager cross connects so that a single ShMC and Switch are not tied together•PICMG 3.0 Revision 2.0 released March 2005•PICMG 3.0 R2.0 ECN-002 released April 2006•Backplane capacity•Power distribution system•Hardware management13•Reliable, fully redundant support•Scalable and flexible•RASM features•Distributed 48V power system141516AdvancedTCA*171819•Manage power, cooling, hotswap and interconnect •IPMI–IPMI 1.5 + ATCA extensions•Electronic Keying (E-Keying)–Prevent damage to boards, mis-operation –Enables/disables backplane connections•“Shelf FRU Info ”describes the backplane links•“Board FRU Info ”describes the link types support for each port•Based on protocol compatibility of the end points of each backplane link •Future-proof for new fabric protocols•LIB for Application•SNMP•Command line interface (CLI)–via COM or Ethernet•Web based interface20•Not sufficient for some applications–On the horizon•10GbE–Too expensive today, but getting more cost effective •Advanced Switching (PICMG 3.4)–Need management software21–Allow users to mix and match functions based onthe application–Better utilization of ATCA board•Advanced Mezzanine Card can be used to add some I/O flexibility22system•Advanced Mezzanine Cards will be used inATCA and in backplane like systems to provideI/O modularity23•ATCA Applications•ADLINK ATCA Building Blocks242526Source: RHKRouter•ATCA Applications•ADLINK ATCA Building Blocks2829•E7520 Chipset–Dual Channel DDR2-400 PC3200 Registered/ECC DIMM –Maximum Capacity 16GB –Dual 64bit/66,133MHz PCI/PCI-X Capable PMC Sites, with One PIM Support –Built-in Two Staged Watchdog Timer –On-board Compact Flash, ATA-100 and SATA 2.5”HDD –Front Panel Access Dual 10/100/1000BASE-T Ports –Front Panel Access Serial Console•PICMG 3.1 Compliance–Two Base Interface 10/100/1000BASE-T Channels–Four Fabric Interface 1000BASE-BX Channels–PICMG 3.1 Option 1/2 Configurable30–Dual 2.5”SATA HDD Kits–PIM (VITA-36)–Legacy PS/2 Keyboard and Mouse, Serial COM, and USB Ports•Available Board Support Packages–MontaVista ®Carrier Grade Linux LSP–WindRiver ®VxWorksv5.5 BSP31•E7520 Chipset–Dual Channel DDR2-400 PC3200 Registered/ECC DIMM –Maximum Capacity 16GB –One PCI/PCI-X 32/64bit, 33/66/100/133MHz PMC Site –Built-in Two Staged Watchdog Timer –On-board Compact Flash –Optional On Board 2.5”UDMA HDD Shared Location with PMC –Optional Single Channel SATA Shared Location with PMC –Front Panel Access Serial Console –Front Panel Access Dual Fiber Channel Ports•PICMG 3.1 Compliance –Two Base Interface 10/100/1000BASE-T Channels–Two Fabric Interface 1000BASE-BX Channels–Two 4Gbps Fiber Channel Ports, Front Panel or Fabric Interface Channels –PICMG 3.1 Option 1/4/7 Configurable–Dual 2.5”SATA HDD Kits–Legacy PS/2 Keyboard and Mouse, Serial COM, and USB Ports•Available Board Support Packages–MontaVista®Carrier Grade Linux LSP–WindRiver®VxWorks v5.5 BSP32–Redundant Shelf Manager Ethernet and Switch-to-Switch Connections–One Additional Front Panel RJ-45 Access 1Gbps Port•Fabric Interface–Fourteen 1000BASE-BX Ports for 14 Slots Dual Star Fabric Interface Backplane–PICMG 3.1 Option 1 Compliant–Three Additional Front Panel RJ-45 Access 1Gbps Ports–Eight Additional Rear Transition Module Access 1Gbps Ports–Two Additional Front Panel Access 10Gbps Uplink Ports•Control Plane–Intel®80219 I/O Processor 600MHz, XScale®Core–DDR-200 System Memory up to 1GB–32MB Flash Storage–Front Panel RJ-11 Access Serial Configuration Port3334– 5 Rear Transition Module Slots–Two Shelf Manager Slots in 4U Width, 6HP Pitch Form Factor•Full Mesh Fabric Interface Backplane (aBP-5050)–Redundant IPMB Bus Topology •Push-Pull Dual Fan Trays –90 CFM Air Flow Per Slot (Simulation)–Hot Swappable Design •Redundant PEM w/ Circuit Breaker –Additional 1U AC110/220 to DC48V 1000W Power Bank*•Compatible Shelf Manager§ADLINK ®aCMM-2000§INTEL ®MPCMM0002* (Q4’06)•Redundant Shelf Manager Design•Front Panel Access–Dual 10/100BASE-T Ethernet to Fabric ShMC Ports–RJ-45 Serial Configuration Port–DB-15 Telco Alarm Connector–LED: Alarms (Minor, Major, Critical), Status (Active/Standby), User Defined 3x •Hardware Monitoring–PWM Fan Speed Control, Tachometer Reading–Remote/Local Temperature Sensor–Dumb PEM Monitor35Thank you.36。
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Copyright 2001, PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG specifications may require use of an invention covered by patent rights. PICMG shall not be responsible for identifying patents for which a license may be required by any PICMG specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of CompactPCI / Packet Switching Backplane equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG, CompactPCI, and the PICMG and CompactPCI logos are registered trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respectPCI Packet Switching Backplane
DO NOT SPECIFY OR CLAIM CONFORMANCE TO THIS DRAFT SPECIFICATION
PICMG 2.16 Draft 0.9.3
Contents
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 3 INTRODUCTION................................................................................................... 1 Objectives of the CompactPCI Packet Switching Backplane ......................... 1 Applicable Documents ...................................................................................... 3 Administration................................................................................................... 4 Special Word Usage .......................................................................................... 6 Name And Logo Usage ..................................................................................... 6 Signal Naming Conventions.............................................................................. 6 Intellectual Property .......................................................................................... 7 Acronyms .......................................................................................................... 7 Definitions......................................................................................................... 8 PACKET SWITCHING BACKPLANE OVERVIEW......................................... 11 Node Slot Overview ........................................................................................ 12 Fabric Slot Overview ...................................................................................... 12 Link Port Overview ......................................................................................... 13 Link Overview................................................................................................. 13 Hot Swap Interoperability ............................................................................... 14 COMPATIBILITY REQUIREMENTS ................................................................ 15 3.1 Keying Requirements ...................................................................................... 15 3.1.1 Node Board Keying Requirements................................................................ 15 3.1.1.1 Alternate Node Board Keying Compliance........................................... 15 3.1.2 Fabric Board Keying ..................................................................................... 16 3.1.2.1 Standard Fabric Board Keying .............................................................. 16 3.1.2.2 Extended Fabric Board Keying ............................................................. 16 3.1.3 Node Slot Keying Requirements ................................................................... 17 3.1.3.1 Alternate Node Slot Keying Compliance .............................................. 17 3.1.4 Standard Fabric Slot Keying ......................................................................... 17 3.1.5 Extended Fabric Slot Keying......................................................................... 18 3.2 3.2.1 3.2.2 3.2.3 3.2.4 Compatibility Glyph Requirements................................................................. 18 Backplane Glyph Requirements .................................................................... 19 Node Board Glyph Requirements ................................................................. 20 Fabric Board Glyph Requirements ................................................................ 21 Glyph Designation of Slot and Board Compatibility .................................... 21