NX8567SAM585-CC中文资料
BL8560-NCRC资料
Product Name
BL8560-APRC BL8560-BPRC BL8560-CPRC BL8560-DPRC BL8560-EPRC BL8560-FPRC BL8560-GPRC BL8560-HPRC BL8560-IPRC
Package Type
SOT-23-6D SOT-23-6D SOT-23-6D SOT-23-6D SOT-23-6D SOT-23-6D SOT-23-6D SOT-23-6D SOT-23-6D
Vin
Vout
7) Load transient response
-8Total 10 Pages
8/8/2006
元器件交易网
BL8560
Package Information:
-1Total 10 Pages
8/8/2006
元器件交易网
BL8560
Selection Guide BL8560 X X XX Pin Assignment
Pin Description
Pin Number
SOT-23-6C SOT-23-6D
-5Total 10 Pages
8/8/2006
元器件交易网
BL8560
Typical Application Circuit Application hints
Explanation
-6Total 10 Pages
8/8/2006
Vout Vin Vout Vout Iout
Vout T Vout
Electrical Characteristics by Output Voltage
Output Voltage Vout (V) Dropout Voltage, VDIF (V) Condition Typ. Max.
PCF8575中文资料
数据表PCF8575远程16位I 2 C总线I/O扩展器内容简介1．特征2．一般描述3．订货信息4．框图5．引脚6．I 2 C总线的特点6．1．位传输6．2．启停条件6．3．系统配置6．4．应答7．功能描述7．1．双向I/O7．2．寻址7．3．读取端口（输入模式）7．4．写入端口（输出模式）7．5．中断8．极限值9．处理10．特点11．I 2 C总线的时序特性12．设备的保护13．封装外形14．焊接14．1焊接表面贴装封装介绍14．2回流焊接14．3波动焊接14．4手工焊接14．5表面安装IC封装的波动和回流焊接方法的适用性15．定义16．支持应用程序17．购买飞利浦I 2 C组件1．特征工作电源电压2.5至5.5 V最大低待机电流消耗10µI 2 C总线并行端口扩展器快至400 kbits/s的I 2 C总线开漏中断输出16位远程I/O端口的I 2 C总线兼容大多数微控制器具有高电流锁存输出驱动能力可直接驱动LED地址由3个硬件地址引脚使用多达8个设备ssop24包装2．一般描述PCF8575是硅CMOS电路。
它提供了通用的远程I/O 扩展对于大多数的微控制器的家庭通过两线双向总线（I 2 C 总线）。
该设备有一个双向16位的接口和一个I 2 C总线接口。
PCF8575具有低电流消耗，包括锁存输出与LED直接驱动高电流驱动能力。
它还具有一个中断线（INT），它可以连接到中断逻辑的微控制器。
通过在这条线上发送中断信号，远程I / O可以通知单片机如果有接口输入的数据而不必通过I 2 C总线通信。
这意味着，PCF8575是I 2 C总线从发送器/接收器。
从PCF8575传输每一个数据必须由偶数个字节组成，第一个字节为P07至P00和第二个字节为P17至P10。
第三个为P07至P00等。
3．订货信息型号：PCF8575TS包装：“名称：SSOP24。
”“描述：塑料收缩小外形封装；24引线；机身宽度5.3毫米。
BZX85C7V5G中文资料
Nominal Zener Voltage (1)
VZ @ IZT (V) 2.7 3.0 3.3 3.6 3.9 4.3 4.7 5.1 5.6 6.2 6.8 7.5 8.2 9.1 10 11 12 13 15 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91 100 110 120 130 150 160 180 200 IZT (mA) 80 80 80 60 60 50 45 45 45 35 35 35 25 25 25 20 20 20 15 15 15 10 10 10 8.0 8.0 8.0 8.0 6.0 6.0 4.0 4.0 4.0 4.0 4.0 4.0 2.7 2.7 2.7 2.7 2.0 2.0 2.0 1.5 1.5 1.5
Maximum Reverse Maximum DC Leakage Current Zener Current
(µ A) 150 100 40 20 10 3.0 3.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 IR @ VR (V) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 2.0 3.0 4.0 4.5 6.2 6.8 7.5 8.2 9.1 10 11 12 13 15 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91 100 110 120 130 150 IZM (2) (mA) 370 340 320 290 280 250 215 200 190 170 155 140 130 120 105 97 88 79 71 66 62 56 52 47 41 36 33 30 28 26 23 21 19 16 15 14 12 10 9.4 8.6 7.8 7.0 6.4 5.8 5.2 4.7
NX1255GB中文资料
n Dimensions
mm
11.8±0.15 5.5 ±0.15
*1 Equivalent Series Resistance Frequency (MHz) (Range) 3.5 to 4 4 to 8 8 to 12 12 to 25
#1 #2
Equivalent Series Resistance max.[Ω] 200 180 1ications are standard for this NDK product. Custom-made specifications such as load capacitance and temperature characteristics are also available. Please contact NDK sales with your enquiries.
Internal connections(TOP VIEW)
#4 #3
2.5±0.15
5.08 2.0 1.5 #1 #2
Reference land pattern
2.2 4.4 2.4
#4
#3 5.08
cu38_071108_NX1255GB_e1
If you have any queries concerning our standard frequencies and numbers for specifying orders, please contact our sales representatives or visit our homepage (/).
For Car Electronics
n Specifications
Item Frequency Range Overtone Order Frequency Tolerance (25 ±3℃) Temperature Characteristics (with reference to +25°C) Operating Temperature Range Equivalent Series Resistance Drive Level Load Capacitance Model NX1255GB 3.5 to 25MHz Fundamental ±50 × 10−6 ±150 × 10−6 −40 to +125℃ Refer to *1 50μW(Max:500μW) 12pF
FPGA可编程逻辑器件芯片XC7V585T-3FFG1157C中文规格书
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching CharacteristicsDS191 (v1.18.1) July 2, 2018Product Specification T DSPDO_A_PA input to P output not using multiplier 1.30 1.48 1.76 1.76ns T DSPDO_C_PC input to P output 1.13 1.30 1.55 1.55ns Combinatorial Delays from Input Pins to Cascading Output Pins T DSPDO_{A; B}_{ACOUT; BCOUT}{A, B} input to {ACOUT, BCOUT} output 0.470.530.630.63ns T DSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input toC ARRYC ASC OUT output usingmultiplier3.44 3.944.69 4.69ns T DSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUToutput using multiplier3.36 3.854.58 4.58ns T DSPDO_{A, B}_CARRYCASCOUT {A, B} input toCARRYCASCOUT output notusing multiplier1.50 1.722.04 2.04ns T DSPDO_C_CARRYCASCOUT C input to CARRYCASCOUToutput1.34 1.53 1.83 1.83ns Combinatorial Delays from Cascading Input Pins to All Output Pins T DSPDO_ACIN_P_MULT ACIN input to P output usingmultiplier3.09 3.554.24 4.24ns T DSPDO_ACIN_P ACIN input to P output not usingmultiplier1.16 1.33 1.59 1.59ns T DSPDO_ACIN_ACOUT ACIN input to ACOUT output0.320.370.450.45ns T DSPDO_ACIN_CARRYCASCOUT_MULT ACIN input toC ARRYC ASC OUT output usingmultiplier3.30 3.794.52 4.52ns T DSPDO_ACIN_CARRYCASCOUT ACIN input toCARRYCASCOUT output notusing multiplier1.37 1.57 1.87 1.87ns T DSPDO_PCIN_P PCIN input to P output0.94 1.08 1.29 1.29ns T DSPDO_PCIN_CARRYCASCOUT PCIN input toCARRYCASCOUT output1.15 1.32 1.57 1.57ns Clock to Outs from Output Register Clock to Output Pins T DSPCKO_P_PREG CLK PREG to P output0.330.350.390.39ns T DSPCKO_CARRYCASCOUT_PREG CLK PREG toCARRYCASCOUT output0.440.500.590.59ns Clock to Outs from Pipeline Register Clock to Output Pins T DSPCKO_P_MREG CLK MREG to P output1.42 1.64 1.96 1.96ns T DSPCKO_CARRYCASCOUT_MREG CLK MREG toCARRYCASCOUT output1.63 1.872.24 2.24ns T DSPCKO_P_ADREG_MULT CLK ADREG to P output usingmultiplier2.30 2.633.13 3.13ns T DSPCKO_CARRYCASCOUT_ADREG_MULT CLK ADREG toC ARRYC ASC OUT output usingmultiplier 2.51 2.87 3.41 3.41nsTable 70:DSP48E1 Switching Characteristics (Cont’d)SymbolDescription Speed Grade Units -3E -2E/-2I/-2LI -1C/-1I -1Q/-1LQZynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching CharacteristicsDS191 (v1.18.1) July 2, 2018Product Specification Clock to Outs from Input Register Clock to Output Pins T DSPCKO_P_AREG_MULT CLK AREG to P output using multiplier 3.343.834.55 4.55ns T DSPCKO_P_BREG CLK BREG to P output not using multiplier 1.391.59 1.88 1.88ns T DSPCKO_P_CREG CLK CREG to P output not using multiplier 1.431.64 1.95 1.95ns T DSPCKO_P_DREG_MULT CLK DREG to P output usingmultiplier3.32 3.804.51 4.51ns Clock to Outs from Input Register Clock to Cascading Output Pins T DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}CLK (ACOUT, BCOUT) to {A,B}register output 0.550.620.740.74ns T DSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT CLK (AREG, BREG) toC ARRYC ASC OUT output usingmultiplier3.554.06 4.84 4.84ns T DSPCKO_CARRYCASCOUT_BREG CLK BREG toCARRYCASCOUT output notusing multiplier1.60 1.822.16 2.16ns T DSPCKO_CARRYCASCOUT_DREG_MULT CLK DREG toC ARRYC ASC OUT output usingmultiplier3.524.03 4.79 4.79ns T DSPCKO_CARRYCASCOUT_CREG CLK CREG toCARRYCASCOUT output1.64 1.882.23 2.23ns Maximum Frequency F MAX With all registers used741.84650.20547.95547.95MHz F MAX_PATDET With pattern detector627.35549.75463.61463.61MHz F MAX_MULT_NOMREG Two register multiply withoutMREG412.20360.75303.77303.77MHz F MAX_MULT_NOMREG_PATDET Two register multiply withoutMREG with pattern detect374.25327.65276.01276.01MHz F MAX_PREADD_MULT_NOADREG Without ADREG468.82408.66342.70342.70MHz F MAX_PREADD_MULT_NOADREG_PATDET Without ADREG with patterndetect468.82408.66342.70342.70MHz F MAX_NOPIPELINEREG Without pipeline registers(MREG, ADREG)306.84267.81225.02225.02MHz F MAX_NOPIPELINEREG_PATDET Without pipeline registers(MREG, ADREG) with patterndetect 285.23249.13209.38209.38MHzTable 70:DSP48E1 Switching Characteristics (Cont’d)Symbol Description Speed GradeUnits -3E-2E/-2I/-2LI -1C/-1I -1Q/-1LQ。
8XC58资料
Y Y
6 Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Microcontroller Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Four-Level Interrupt Priority Extended Temperature Range Except for 33 MHz Offering ( b 40 C to a 85 C)
PIN DESCRIPTIONS
VCC Supply voltage VSS Circuit ground VSS1 Secondary ground (not on DIP) Provided to reduce ground bounce and improve power supply by-passing NOTE This pin is not a substitute for the VSS pin (pin 22) (Connection not necessary for proper operation ) Port 0 Port 0 is an 8-bit open drain bidirectional I O port As an output port each pin can sink several LS TTL inputs Port 0 pins that have 1’s written to them float and in that state can be used as high-impedance inputs Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory In this application it uses strong internal pullups when emitting 1’s and can source and sink several LS TTL inputs Port 0 also receives the code bytes during EPROM programming and outputs the code bytes during program verification External pullup resistors are required during program verification Port 1 Port 1 is an 8-bit bidirectional I O port with internal pullups The Port 1 output buffers can drive LS TTL inputs Port 1 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 1 pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups In addition Port 1 serves the functions of the following special features of the 8XC5X Port Pin P1 0 P1 1 Alternate Function T2 (External Count Input to Timer Counter 2) Clock-Out T2EX (Timer Counter 2 Capture Reload Trigger and Direction Control)
SM8577B资料
SM8577BReal-time Clock IC OVERVIEWPINOUTSM8577BBLOCK DIAGRAMPIN DESCRIPTIONN u m b e r N a m e I/O Description1CE I Chip enable. With pull-down resistor built-in.HIGH: EnableLOW: DATA goes high impedance; input on CLK and DATA stops; and the TM bit is cleared.2DATA I/O Data read and write input/output3CLK I Serial clock input.Data is input (write mode) and output (read mode) on the rising edge of CLK.4FOUT O Frequency output (controlled by the 4th data bit of the ‘week’ data, FSEL).1 Hz output when FSEL is 0, and 32.768 kHz output when FSEL is 1.In 1 Hz output mode, the 1 Hz signal is synchronized to the internal 1 second signal. FOUT output is not affected by the CE signal.5VSS–Ground6XT I Crystal oscillator element connection pin7XTN O Crystal oscillator element connection pin. Oscillator capacitor C D is built-in.8VDD–Supply voltage.Connect a ≥ 0.1 µF capacitor between VDD and VSS.SM8577BSPECIFICATIONSAbsolute Maximum RatingsV SS = 0 VRecommended Operating ConditionsV SS = 0 VOscillator CharacteristicsV SS = 0 V , T a = 25 ° C, C G = 12 pF, Seiko Epson C-002SH crystal (C I = 30 k Ω , C L = 6 pF) unless otherwise notedParameterSymbol ConditionRating Unit Supply voltage range V DD − 0.3 to 7.0V Input voltage range V IN V SS − 0.3 to V DD + 0.3V Output voltage range V OUT V SS − 0.3 to V DD + 0.3V Storage temperature range T stg − 55 to 125 ° C Power dissipation P D 150mW Soldering temperature T sld 255 ° C Soldering timet sld10sParameterSymbol ConditionRating Unit Supply voltage range V DD 2.5 to 5.5V Operating temperature rangeT opr− 40 to 85° CParameterSymbol ConditionRatingUnit min typ m a x Oscillator start time t STA V DD = 2.5 V––3s Oscillator start voltage V STA 1.5––V Oscillator stop voltage V STO –– 1.5V Frequency voltage characteristic f/V V DD = 2.0 to 5.5 V − 2–+2ppm/V Frequency accuracy ε V DD = 5.0 V − 10–+10ppm Output capacitanceC DV DD= 5.0 V–12–pFSM8577BDC Electrical CharacteristicsV SS = 0 V, V DD = 5.0 V ± 10%, T a = −40 to 85 °C unless otherwise notedParameter Symbol ConditionRatingUnit min typ m a xCurrent consumption I DD1V DD = 5.0 VCE = V SS– 1.5 3.0µA I DD2V DD = 3.0 V– 1.0 2.0µAHIGH-level input voltage V IH CE, CLK, DATA0.8V DD––V LOW-level input voltage V IL CE, CLK, DATA––0.2V DD V Input resistance R IN CE: V IN = 5.0 V––800kΩInput OFF leakage current I leak CLK: V IN = V DD or V SSCE: V IN = V SS––0.5µAHIGH-level output voltage V OH1V DD = 5.0 V DATA, FOUT:I OH = −1.0 mA4.5––V V OH2V DD = 3.0 V 2.0––VLOW-level output voltage V OL1V DD = 5.0 V DATA, FOUT:I OL = 1.0 mA––V SS + 0.5V V OL2V DD = 3.0 V––V SS + 0.8VOutput leakage current I OZH DATA, FOUT: V OUT = 5.5 V−1.0– 1.0µA I OZL DATA, FOUT: V OUT = 0 V−1.0– 1.0µASupply voltage detect thresholdvoltageV DET 1.4 1.7 2.0VSM8577BAC CharacteristicsV DD = 5 V ± 10%, V SS = 0 V , T a = − 40 to 85 ° C, C L = 50 pF unless otherwise notedV DD = 3 V ± 10%, V SS = 0 V , T a = − 40 to 85 ° C, C L = 50 pF unless otherwise notedParameterSymbol ConditionRatingUnit min m a x min CLK clock period t CLK 0.75–7800µs CLK LOW-level pulsewidth t CLKL 0.375–3900µs CLK HIGH-level pulsewidth t CLKH 0.375–3900µs CE setup time t CES 0.375–3900µs CE hold time t CEH 0.375––µs CE enable time t CE ––0.9s Write data setup time t SD 0.1––µs Write data hold time t HD 0.1––µs DATA output delay time t DATD ––0.2µs DATA output floating time t DZ See measurement circuit.––0.1µs Clock rise time t r1 ––50ns Clock fall time t f1 ––50ns FOUT rise time t r2 C L = 30 pF ––100ns FOUT fall time t f2 C L = 30 pF––100ns FOUT duty cycle Duty C L = 30 pF , 32 kHz output 40–60%Wait timet RCV0.95––µsParameterSymbol ConditionRatingUnit min m a x min CLK clock period t CLK 1.5–7800µs CLK LOW-level pulsewidth t CLKL 0.75–3900µs CLK HIGH-level pulsewidth t CLKH 0.75–3900µs CE setup time t CES 0.75–3900µs CE hold time t CEH 0.75––µs CE enable time t CE ––0.9s Write data setup time t SD 0.2––µs Write data hold time t HD 0.1––µs DATA output delay time t DATD ––0.4µs DATA output floating time t DZ See measurement circuit.––0.2µs Clock rise time t r1 ––100ns Clock fall time t f1 ––100ns FOUT rise time t r2 C L = 30 pF ––200ns FOUT fall time t f2 C L = 30 pF––200ns FOUT duty cycle Duty C L = 30 pF , 32 kHz output 40–60%Wait timet RCV1.9––µsMeasurement CircuitDATA Output Floating TimingTiming DiagramsData readData writeFOUT outputNote that the 1 Hz and 32 kHz oscillators are not synchronized to each other, so switching between 1 Hz and 32 kHz output temporarily shortens the duty cycle. Accordingly, a wait time (≥ output frequency period) should be incorporated when switching during normal operation.FUNCTIONAL DESCRIPTION Timer Data ConfigurationCounter data is stored in BCD format. The IC performs long/short month and leap-year adjustment automatically. Leap-year adjustment occurs:•when the decade digit is odd and the year digit is a 2 or 6, and•when the decade digit is even and the year digit is a 0, 4 or 8.The time display is 24-hour mode. All data is written and read with the LSB first.* bits are don’t care write bits.FDT is the supply voltage detect bit. FDT is set to 1 when the voltage between VDD and VSS falls below 1.7 ± 0.3 V. It is reset to 0 for data reads longer than 56 bits. Note that the FDT bit is not reset to 0 for data reads of 55 bits or less. The read/write data bits should initially be set to 0. After the supply voltage is first applied, the FDT bit should also be set to 0.FSEL is the FOUT output frequency switch control bit. 1 Hz output is selected when FSEL is 0, and 32 kHz output is selected when FSEL is 1. After power is first applied, 1 Hz default mode is selected.TM is the factory test bit. It should be set to 0 for normal use.Data ReadWhen CE is HIGH, data read mode starts from the first rising edge of CLK for which DATA is LOW. Valid data is then output on DATA from the 9th rising edge of CLK. Time and date data is loaded into the shift register on the 8th falling edge of CLK and then output on DATA in sync with the rising edge of CLK, starting with the seconds’ digit LSB. Data is loaded and shifted in the sequence second, minute, hour, week, day, and month. The output data is valid for the first 60 rising edges of CLK. Output data does not change after the 60th rising edge, even if clock input continues.Within the 60 cycles of valid data output, partial data output can be obtained by taking CE LOW after the corresponding number of cycles. For example, if only the ‘second’ to ‘week’ data output is required, then that data only is output if CE goes LOW after 36 clock cycles.For continuous data reads, a wait time (t RCV) is required before the next data cycle after CE goes LOW.Note that if a timer counter update operation (a 1 s carry) occurs during a data read cycle, the data in the shift register is not updated and, as a result, the output data contains an error of −1 s.The data read cycle should be completed within t CE≤ 0.9 s.Data WriteNC9617AE1997.04NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.When CE is HIGH, data write mode starts from the first rising edge of CLK for which DATA is HIGH.Valid data is then input on DATA from the 9th rising edge of CLK. Time and date data is loaded into the shift register in sync with the rising edge of CLK,starting with the seconds’ digit LSB. Data is loaded and shifted in the sequence second, minute, hour,week, day, and month. After 60 rising edges of CLK,the shift register contents are then transferred to the timer counters.Note that a data write cycle must contain 60 bits of input data. If CE goes LOW before 60 bits are input,the input data is invalid. If the input data exceeds 60bits, data from the 61st bit is ignored (the first 60 bits remain valid).During a data write cycle, timer counter operation stops on the first falling edge of CLK, and the 1 Hz to 128 Hz frequency divider step counters are reset.The 1 s counter increment signal is stopped and does not restart until CE goes LOW. The divider step counters are reset during the interval between the first falling edge of CLK and the 2nd rising edge of CLK.The data write cycle should be completed within t CE ≤ 0.9 s.If a data read cycle occurs immediately after a data write cycle, a wait time (t RCV ) is required after CE goes LOW.Note that activating a read cycle when no valid data is present will cause incorrect operation. All bits must be valid data bits.Supply Voltage DetectionThe supply voltage detector tests the level of the supply voltage once every 0.5 seconds. If the supply voltage falls below the detector threshold, the FDT bit is set to 1. The FDT bit is reset to 0 after a dataread cycle that contains at least 56 data bits. The FDT bit is not reset for data read cycles of 55 bits or less.。
NC7SP58资料
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation. Quiet Series and MicroPak are trademarks of Fairchild Semiconductor Corporation.
General Description
The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power (ULP) Series of TinyLogic. Ideal for applications where battery life is critical, this product is designed for ultra low power consumption within the VCC operating range of 0.9V to 3.6V. Each device is capable of being configured for 1 of 5 unique 2-input logic functions. Any possible 2-input combinatorial logic function can be implemented as shown in the Function Selection Table. Device functionality is selected by how the device is wired at the board level. Figure 1 through Figure 10 illustrate how to connect the NC7SP57 and NC7SP58 respectively for the desired logic function. All inputs have been implemented with hysteresis. The internal circuit is composed of a minimum of inverter stages including the output buffer, to enable ultra low dynamic power. The NC7SP57 and NC7SP58, for lower drive requirements, are uniquely designed for optimized power and speed, and are fabricated with an advanced CMOS technology to achieve best in class operation while maintaining extremely low CMOS power dissipation.